1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_TYPES_H 29 #define _DPAA2_TYPES_H 30 31 #include <sys/param.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 35 #include <machine/atomic.h> 36 #include <machine/bus.h> 37 38 #define DPAA2_MAGIC ((uint32_t) 0xD4AA2C0Du) 39 40 #define DPAA2_MAX_CHANNELS 16 /* CPU cores */ 41 #define DPAA2_MAX_TCS 8 /* Traffic classes */ 42 43 #define DPAA2_TX_SEGLIMIT (16u) /* for 64 KiB frames */ 44 #define DPAA2_TX_SEG_SZ (PAGE_SIZE) 45 #define DPAA2_TX_SEGS_MAXSZ (DPAA2_TX_SEGLIMIT * DPAA2_TX_SEG_SZ) 46 #define DPAA2_TX_SGT_SZ (PAGE_SIZE) /* in bytes */ 47 48 /** 49 * @brief Types of the DPAA2 devices. 50 */ 51 enum dpaa2_dev_type { 52 DPAA2_DEV_MC = 7500, /* Management Complex (firmware bus) */ 53 DPAA2_DEV_RC, /* Resource Container (firmware bus) */ 54 DPAA2_DEV_IO, /* I/O object (to work with QBMan portal) */ 55 DPAA2_DEV_NI, /* Network Interface */ 56 DPAA2_DEV_MCP, /* MC portal */ 57 DPAA2_DEV_BP, /* Buffer Pool */ 58 DPAA2_DEV_CON, /* Concentrator */ 59 DPAA2_DEV_MAC, /* MAC object */ 60 DPAA2_DEV_MUX, /* MUX (Datacenter bridge) object */ 61 DPAA2_DEV_SW, /* Ethernet Switch */ 62 63 DPAA2_DEV_NOTYPE /* Shouldn't be assigned to any DPAA2 device. */ 64 }; 65 66 /** 67 * @brief Types of the DPNI queues. 68 */ 69 enum dpaa2_ni_queue_type { 70 DPAA2_NI_QUEUE_RX = 0, 71 DPAA2_NI_QUEUE_TX, 72 DPAA2_NI_QUEUE_TX_CONF, 73 DPAA2_NI_QUEUE_RX_ERR 74 }; 75 76 struct dpaa2_atomic { 77 volatile int counter; 78 }; 79 80 /** 81 * @brief Tx ring. 82 * 83 * fq: Parent (TxConf) frame queue. 84 * fqid: ID of the logical Tx queue. 85 * br: Ring buffer for mbufs to transmit. 86 * lock: Lock for the ring buffer. 87 */ 88 struct dpaa2_ni_tx_ring { 89 struct dpaa2_ni_fq *fq; 90 uint32_t fqid; 91 uint32_t txid; /* Tx ring index */ 92 93 struct buf_ring *br; 94 struct mtx lock; 95 } __aligned(CACHE_LINE_SIZE); 96 97 /** 98 * @brief Frame Queue is the basic queuing structure used by the QMan. 99 * 100 * It comprises a list of frame descriptors (FDs), so it can be thought of 101 * as a queue of frames. 102 * 103 * NOTE: When frames on a FQ are ready to be processed, the FQ is enqueued 104 * onto a work queue (WQ). 105 * 106 * fqid: Frame queue ID, can be used to enqueue/dequeue or execute other 107 * commands on the queue through DPIO. 108 * txq_n: Number of configured Tx queues. 109 * tx_fqid: Frame queue IDs of the Tx queues which belong to the same flowid. 110 * Note that Tx queues are logical queues and not all management 111 * commands are available on these queue types. 112 * qdbin: Queue destination bin. Can be used with the DPIO enqueue 113 * operation based on QDID, QDBIN and QPRI. Note that all Tx queues 114 * with the same flowid have the same destination bin. 115 */ 116 struct dpaa2_ni_fq { 117 struct dpaa2_channel *chan; 118 uint32_t fqid; 119 uint16_t flowid; 120 uint8_t tc; 121 enum dpaa2_ni_queue_type type; 122 123 /* Optional fields (for TxConf queue). */ 124 struct dpaa2_ni_tx_ring tx_rings[DPAA2_MAX_TCS]; 125 uint32_t tx_qdbin; 126 } __aligned(CACHE_LINE_SIZE); 127 128 /* Handy wrappers over atomic operations. */ 129 #define DPAA2_ATOMIC_XCHG(a, val) \ 130 (atomic_swap_int(&(a)->counter, (val))) 131 #define DPAA2_ATOMIC_READ(a) \ 132 (atomic_load_acq_int(&(a)->counter)) 133 #define DPAA2_ATOMIC_ADD(a, val) \ 134 (atomic_add_acq_int(&(a)->counter, (val))) 135 136 const char *dpaa2_ttos(enum dpaa2_dev_type); 137 enum dpaa2_dev_type dpaa2_stot(const char *); 138 void dpaa2_dmamap_oneseg_cb(void *, bus_dma_segment_t *, int, int); 139 140 #endif /* _DPAA2_TYPES_H */ 141