1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright © 2021-2023 Dmitry Salychev 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #ifndef _DPAA2_TYPES_H 29 #define _DPAA2_TYPES_H 30 31 #include <sys/param.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 35 #include <machine/atomic.h> 36 #include <machine/bus.h> 37 38 #define DPAA2_MAGIC ((uint32_t) 0xD4AA2C0Du) 39 40 #define DPAA2_MAX_CHANNELS 16 /* CPU cores */ 41 #define DPAA2_MAX_TCS 8 /* Traffic classes */ 42 43 /** 44 * @brief Types of the DPAA2 devices. 45 */ 46 enum dpaa2_dev_type { 47 DPAA2_DEV_MC = 7500, /* Management Complex (firmware bus) */ 48 DPAA2_DEV_RC, /* Resource Container (firmware bus) */ 49 DPAA2_DEV_IO, /* I/O object (to work with QBMan portal) */ 50 DPAA2_DEV_NI, /* Network Interface */ 51 DPAA2_DEV_MCP, /* MC portal */ 52 DPAA2_DEV_BP, /* Buffer Pool */ 53 DPAA2_DEV_CON, /* Concentrator */ 54 DPAA2_DEV_MAC, /* MAC object */ 55 DPAA2_DEV_MUX, /* MUX (Datacenter bridge) object */ 56 DPAA2_DEV_SW, /* Ethernet Switch */ 57 58 DPAA2_DEV_NOTYPE /* Shouldn't be assigned to any DPAA2 device. */ 59 }; 60 61 /** 62 * @brief Types of the DPNI queues. 63 */ 64 enum dpaa2_ni_queue_type { 65 DPAA2_NI_QUEUE_RX = 0, 66 DPAA2_NI_QUEUE_TX, 67 DPAA2_NI_QUEUE_TX_CONF, 68 DPAA2_NI_QUEUE_RX_ERR 69 }; 70 71 struct dpaa2_atomic { 72 volatile int counter; 73 }; 74 75 /** 76 * @brief Tx ring. 77 * 78 * fq: Parent (TxConf) frame queue. 79 * fqid: ID of the logical Tx queue. 80 * br: Ring buffer for mbufs to transmit. 81 * lock: Lock for the ring buffer. 82 */ 83 struct dpaa2_ni_tx_ring { 84 struct dpaa2_ni_fq *fq; 85 uint32_t fqid; 86 uint32_t txid; /* Tx ring index */ 87 88 struct buf_ring *br; 89 struct mtx lock; 90 } __aligned(CACHE_LINE_SIZE); 91 92 /** 93 * @brief Frame Queue is the basic queuing structure used by the QMan. 94 * 95 * It comprises a list of frame descriptors (FDs), so it can be thought of 96 * as a queue of frames. 97 * 98 * NOTE: When frames on a FQ are ready to be processed, the FQ is enqueued 99 * onto a work queue (WQ). 100 * 101 * fqid: Frame queue ID, can be used to enqueue/dequeue or execute other 102 * commands on the queue through DPIO. 103 * txq_n: Number of configured Tx queues. 104 * tx_fqid: Frame queue IDs of the Tx queues which belong to the same flowid. 105 * Note that Tx queues are logical queues and not all management 106 * commands are available on these queue types. 107 * qdbin: Queue destination bin. Can be used with the DPIO enqueue 108 * operation based on QDID, QDBIN and QPRI. Note that all Tx queues 109 * with the same flowid have the same destination bin. 110 */ 111 struct dpaa2_ni_fq { 112 struct dpaa2_channel *chan; 113 uint32_t fqid; 114 uint16_t flowid; 115 uint8_t tc; 116 enum dpaa2_ni_queue_type type; 117 118 /* Optional fields (for TxConf queue). */ 119 struct dpaa2_ni_tx_ring tx_rings[DPAA2_MAX_TCS]; 120 uint32_t tx_qdbin; 121 } __aligned(CACHE_LINE_SIZE); 122 123 /* Handy wrappers over atomic operations. */ 124 #define DPAA2_ATOMIC_XCHG(a, val) \ 125 (atomic_swap_int(&(a)->counter, (val))) 126 #define DPAA2_ATOMIC_READ(a) \ 127 (atomic_load_acq_int(&(a)->counter)) 128 #define DPAA2_ATOMIC_ADD(a, val) \ 129 (atomic_add_acq_int(&(a)->counter, (val))) 130 131 const char *dpaa2_ttos(enum dpaa2_dev_type); 132 enum dpaa2_dev_type dpaa2_stot(const char *); 133 void dpaa2_dmamap_oneseg_cb(void *, bus_dma_segment_t *, int, int); 134 135 #endif /* _DPAA2_TYPES_H */ 136