1 /* $NetBSD: if_stge.c,v 1.32 2005/12/11 12:22:49 christos Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
5 *
6 * Copyright (c) 2001 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * This code is derived from software contributed to The NetBSD Foundation
10 * by Jason R. Thorpe.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Device driver for the Sundance Tech. TC9021 10/100/1000
36 * Ethernet controller.
37 */
38
39 #include <sys/cdefs.h>
40 #ifdef HAVE_KERNEL_OPTION_HEADERS
41 #include "opt_device_polling.h"
42 #endif
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/endian.h>
47 #include <sys/mbuf.h>
48 #include <sys/malloc.h>
49 #include <sys/kernel.h>
50 #include <sys/module.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/taskqueue.h>
55
56 #include <net/bpf.h>
57 #include <net/ethernet.h>
58 #include <net/if.h>
59 #include <net/if_var.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
64
65 #include <machine/bus.h>
66 #include <machine/resource.h>
67 #include <sys/bus.h>
68 #include <sys/rman.h>
69
70 #include <dev/mii/mii.h>
71 #include <dev/mii/mii_bitbang.h>
72 #include <dev/mii/miivar.h>
73
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
76
77 #include <dev/stge/if_stgereg.h>
78
79 #define STGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80
81 MODULE_DEPEND(stge, pci, 1, 1, 1);
82 MODULE_DEPEND(stge, ether, 1, 1, 1);
83 MODULE_DEPEND(stge, miibus, 1, 1, 1);
84
85 /* "device miibus" required. See GENERIC if you get errors here. */
86 #include "miibus_if.h"
87
88 /*
89 * Devices supported by this driver.
90 */
91 static const struct stge_product {
92 uint16_t stge_vendorid;
93 uint16_t stge_deviceid;
94 const char *stge_name;
95 } stge_products[] = {
96 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST1023,
97 "Sundance ST-1023 Gigabit Ethernet" },
98
99 { VENDOR_SUNDANCETI, DEVICEID_SUNDANCETI_ST2021,
100 "Sundance ST-2021 Gigabit Ethernet" },
101
102 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021,
103 "Tamarack TC9021 Gigabit Ethernet" },
104
105 { VENDOR_TAMARACK, DEVICEID_TAMARACK_TC9021_ALT,
106 "Tamarack TC9021 Gigabit Ethernet" },
107
108 /*
109 * The Sundance sample boards use the Sundance vendor ID,
110 * but the Tamarack product ID.
111 */
112 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021,
113 "Sundance TC9021 Gigabit Ethernet" },
114
115 { VENDOR_SUNDANCETI, DEVICEID_TAMARACK_TC9021_ALT,
116 "Sundance TC9021 Gigabit Ethernet" },
117
118 { VENDOR_DLINK, DEVICEID_DLINK_DL4000,
119 "D-Link DL-4000 Gigabit Ethernet" },
120
121 { VENDOR_ANTARES, DEVICEID_ANTARES_TC9021,
122 "Antares Gigabit Ethernet" }
123 };
124
125 static int stge_probe(device_t);
126 static int stge_attach(device_t);
127 static int stge_detach(device_t);
128 static int stge_shutdown(device_t);
129 static int stge_suspend(device_t);
130 static int stge_resume(device_t);
131
132 static int stge_encap(struct stge_softc *, struct mbuf **);
133 static void stge_start(if_t);
134 static void stge_start_locked(if_t);
135 static void stge_watchdog(struct stge_softc *);
136 static int stge_ioctl(if_t, u_long, caddr_t);
137 static void stge_init(void *);
138 static void stge_init_locked(struct stge_softc *);
139 static void stge_vlan_setup(struct stge_softc *);
140 static void stge_stop(struct stge_softc *);
141 static void stge_start_tx(struct stge_softc *);
142 static void stge_start_rx(struct stge_softc *);
143 static void stge_stop_tx(struct stge_softc *);
144 static void stge_stop_rx(struct stge_softc *);
145
146 static void stge_reset(struct stge_softc *, uint32_t);
147 static int stge_eeprom_wait(struct stge_softc *);
148 static void stge_read_eeprom(struct stge_softc *, int, uint16_t *);
149 static void stge_tick(void *);
150 static void stge_stats_update(struct stge_softc *);
151 static void stge_set_filter(struct stge_softc *);
152 static void stge_set_multi(struct stge_softc *);
153
154 static void stge_link_task(void *, int);
155 static void stge_intr(void *);
156 static __inline int stge_tx_error(struct stge_softc *);
157 static void stge_txeof(struct stge_softc *);
158 static int stge_rxeof(struct stge_softc *);
159 static __inline void stge_discard_rxbuf(struct stge_softc *, int);
160 static int stge_newbuf(struct stge_softc *, int);
161 #ifndef __NO_STRICT_ALIGNMENT
162 static __inline struct mbuf *stge_fixup_rx(struct stge_softc *, struct mbuf *);
163 #endif
164
165 static int stge_miibus_readreg(device_t, int, int);
166 static int stge_miibus_writereg(device_t, int, int, int);
167 static void stge_miibus_statchg(device_t);
168 static int stge_mediachange(if_t);
169 static void stge_mediastatus(if_t, struct ifmediareq *);
170
171 static void stge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
172 static int stge_dma_alloc(struct stge_softc *);
173 static void stge_dma_free(struct stge_softc *);
174 static void stge_dma_wait(struct stge_softc *);
175 static void stge_init_tx_ring(struct stge_softc *);
176 static int stge_init_rx_ring(struct stge_softc *);
177 #ifdef DEVICE_POLLING
178 static int stge_poll(if_t, enum poll_cmd, int);
179 #endif
180
181 static void stge_setwol(struct stge_softc *);
182 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
183 static int sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS);
184 static int sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS);
185
186 /*
187 * MII bit-bang glue
188 */
189 static uint32_t stge_mii_bitbang_read(device_t);
190 static void stge_mii_bitbang_write(device_t, uint32_t);
191
192 static const struct mii_bitbang_ops stge_mii_bitbang_ops = {
193 stge_mii_bitbang_read,
194 stge_mii_bitbang_write,
195 {
196 PC_MgmtData, /* MII_BIT_MDO */
197 PC_MgmtData, /* MII_BIT_MDI */
198 PC_MgmtClk, /* MII_BIT_MDC */
199 PC_MgmtDir, /* MII_BIT_DIR_HOST_PHY */
200 0, /* MII_BIT_DIR_PHY_HOST */
201 }
202 };
203
204 static device_method_t stge_methods[] = {
205 /* Device interface */
206 DEVMETHOD(device_probe, stge_probe),
207 DEVMETHOD(device_attach, stge_attach),
208 DEVMETHOD(device_detach, stge_detach),
209 DEVMETHOD(device_shutdown, stge_shutdown),
210 DEVMETHOD(device_suspend, stge_suspend),
211 DEVMETHOD(device_resume, stge_resume),
212
213 /* MII interface */
214 DEVMETHOD(miibus_readreg, stge_miibus_readreg),
215 DEVMETHOD(miibus_writereg, stge_miibus_writereg),
216 DEVMETHOD(miibus_statchg, stge_miibus_statchg),
217
218 DEVMETHOD_END
219 };
220
221 static driver_t stge_driver = {
222 "stge",
223 stge_methods,
224 sizeof(struct stge_softc)
225 };
226
227 DRIVER_MODULE(stge, pci, stge_driver, 0, 0);
228 DRIVER_MODULE(miibus, stge, miibus_driver, 0, 0);
229
230 static struct resource_spec stge_res_spec_io[] = {
231 { SYS_RES_IOPORT, PCIR_BAR(0), RF_ACTIVE },
232 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
233 { -1, 0, 0 }
234 };
235
236 static struct resource_spec stge_res_spec_mem[] = {
237 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE },
238 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
239 { -1, 0, 0 }
240 };
241
242 /*
243 * stge_mii_bitbang_read: [mii bit-bang interface function]
244 *
245 * Read the MII serial port for the MII bit-bang module.
246 */
247 static uint32_t
stge_mii_bitbang_read(device_t dev)248 stge_mii_bitbang_read(device_t dev)
249 {
250 struct stge_softc *sc;
251 uint32_t val;
252
253 sc = device_get_softc(dev);
254
255 val = CSR_READ_1(sc, STGE_PhyCtrl);
256 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
257 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
258 return (val);
259 }
260
261 /*
262 * stge_mii_bitbang_write: [mii big-bang interface function]
263 *
264 * Write the MII serial port for the MII bit-bang module.
265 */
266 static void
stge_mii_bitbang_write(device_t dev,uint32_t val)267 stge_mii_bitbang_write(device_t dev, uint32_t val)
268 {
269 struct stge_softc *sc;
270
271 sc = device_get_softc(dev);
272
273 CSR_WRITE_1(sc, STGE_PhyCtrl, val);
274 CSR_BARRIER(sc, STGE_PhyCtrl, 1,
275 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
276 }
277
278 /*
279 * sc_miibus_readreg: [mii interface function]
280 *
281 * Read a PHY register on the MII of the TC9021.
282 */
283 static int
stge_miibus_readreg(device_t dev,int phy,int reg)284 stge_miibus_readreg(device_t dev, int phy, int reg)
285 {
286 struct stge_softc *sc;
287 int error, val;
288
289 sc = device_get_softc(dev);
290
291 if (reg == STGE_PhyCtrl) {
292 /* XXX allow ip1000phy read STGE_PhyCtrl register. */
293 STGE_MII_LOCK(sc);
294 error = CSR_READ_1(sc, STGE_PhyCtrl);
295 STGE_MII_UNLOCK(sc);
296 return (error);
297 }
298
299 STGE_MII_LOCK(sc);
300 val = mii_bitbang_readreg(dev, &stge_mii_bitbang_ops, phy, reg);
301 STGE_MII_UNLOCK(sc);
302 return (val);
303 }
304
305 /*
306 * stge_miibus_writereg: [mii interface function]
307 *
308 * Write a PHY register on the MII of the TC9021.
309 */
310 static int
stge_miibus_writereg(device_t dev,int phy,int reg,int val)311 stge_miibus_writereg(device_t dev, int phy, int reg, int val)
312 {
313 struct stge_softc *sc;
314
315 sc = device_get_softc(dev);
316
317 STGE_MII_LOCK(sc);
318 mii_bitbang_writereg(dev, &stge_mii_bitbang_ops, phy, reg, val);
319 STGE_MII_UNLOCK(sc);
320 return (0);
321 }
322
323 /*
324 * stge_miibus_statchg: [mii interface function]
325 *
326 * Callback from MII layer when media changes.
327 */
328 static void
stge_miibus_statchg(device_t dev)329 stge_miibus_statchg(device_t dev)
330 {
331 struct stge_softc *sc;
332
333 sc = device_get_softc(dev);
334 taskqueue_enqueue(taskqueue_swi, &sc->sc_link_task);
335 }
336
337 /*
338 * stge_mediastatus: [ifmedia interface function]
339 *
340 * Get the current interface media status.
341 */
342 static void
stge_mediastatus(if_t ifp,struct ifmediareq * ifmr)343 stge_mediastatus(if_t ifp, struct ifmediareq *ifmr)
344 {
345 struct stge_softc *sc;
346 struct mii_data *mii;
347
348 sc = if_getsoftc(ifp);
349 mii = device_get_softc(sc->sc_miibus);
350
351 mii_pollstat(mii);
352 ifmr->ifm_status = mii->mii_media_status;
353 ifmr->ifm_active = mii->mii_media_active;
354 }
355
356 /*
357 * stge_mediachange: [ifmedia interface function]
358 *
359 * Set hardware to newly-selected media.
360 */
361 static int
stge_mediachange(if_t ifp)362 stge_mediachange(if_t ifp)
363 {
364 struct stge_softc *sc;
365 struct mii_data *mii;
366
367 sc = if_getsoftc(ifp);
368 mii = device_get_softc(sc->sc_miibus);
369 mii_mediachg(mii);
370
371 return (0);
372 }
373
374 static int
stge_eeprom_wait(struct stge_softc * sc)375 stge_eeprom_wait(struct stge_softc *sc)
376 {
377 int i;
378
379 for (i = 0; i < STGE_TIMEOUT; i++) {
380 DELAY(1000);
381 if ((CSR_READ_2(sc, STGE_EepromCtrl) & EC_EepromBusy) == 0)
382 return (0);
383 }
384 return (1);
385 }
386
387 /*
388 * stge_read_eeprom:
389 *
390 * Read data from the serial EEPROM.
391 */
392 static void
stge_read_eeprom(struct stge_softc * sc,int offset,uint16_t * data)393 stge_read_eeprom(struct stge_softc *sc, int offset, uint16_t *data)
394 {
395
396 if (stge_eeprom_wait(sc))
397 device_printf(sc->sc_dev, "EEPROM failed to come ready\n");
398
399 CSR_WRITE_2(sc, STGE_EepromCtrl,
400 EC_EepromAddress(offset) | EC_EepromOpcode(EC_OP_RR));
401 if (stge_eeprom_wait(sc))
402 device_printf(sc->sc_dev, "EEPROM read timed out\n");
403 *data = CSR_READ_2(sc, STGE_EepromData);
404 }
405
406 static int
stge_probe(device_t dev)407 stge_probe(device_t dev)
408 {
409 const struct stge_product *sp;
410 int i;
411 uint16_t vendor, devid;
412
413 vendor = pci_get_vendor(dev);
414 devid = pci_get_device(dev);
415 sp = stge_products;
416 for (i = 0; i < nitems(stge_products); i++, sp++) {
417 if (vendor == sp->stge_vendorid &&
418 devid == sp->stge_deviceid) {
419 device_set_desc(dev, sp->stge_name);
420 return (BUS_PROBE_DEFAULT);
421 }
422 }
423
424 return (ENXIO);
425 }
426
427 static int
stge_attach(device_t dev)428 stge_attach(device_t dev)
429 {
430 struct stge_softc *sc;
431 if_t ifp;
432 uint8_t enaddr[ETHER_ADDR_LEN];
433 int error, flags, i;
434 uint16_t cmd;
435 uint32_t val;
436
437 error = 0;
438 sc = device_get_softc(dev);
439 sc->sc_dev = dev;
440
441 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
442 MTX_DEF);
443 mtx_init(&sc->sc_mii_mtx, "stge_mii_mutex", NULL, MTX_DEF);
444 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
445 TASK_INIT(&sc->sc_link_task, 0, stge_link_task, sc);
446
447 /*
448 * Map the device.
449 */
450 pci_enable_busmaster(dev);
451 cmd = pci_read_config(dev, PCIR_COMMAND, 2);
452 val = pci_read_config(dev, PCIR_BAR(1), 4);
453 if (PCI_BAR_IO(val))
454 sc->sc_spec = stge_res_spec_mem;
455 else {
456 val = pci_read_config(dev, PCIR_BAR(0), 4);
457 if (!PCI_BAR_IO(val)) {
458 device_printf(sc->sc_dev, "couldn't locate IO BAR\n");
459 error = ENXIO;
460 goto fail;
461 }
462 sc->sc_spec = stge_res_spec_io;
463 }
464 error = bus_alloc_resources(dev, sc->sc_spec, sc->sc_res);
465 if (error != 0) {
466 device_printf(dev, "couldn't allocate %s resources\n",
467 sc->sc_spec == stge_res_spec_mem ? "memory" : "I/O");
468 goto fail;
469 }
470 sc->sc_rev = pci_get_revid(dev);
471
472 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
474 "rxint_nframe", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
475 &sc->sc_rxint_nframe, 0, sysctl_hw_stge_rxint_nframe, "I",
476 "stge rx interrupt nframe");
477
478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
480 "rxint_dmawait", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
481 &sc->sc_rxint_dmawait, 0, sysctl_hw_stge_rxint_dmawait, "I",
482 "stge rx interrupt dmawait");
483
484 /* Pull in device tunables. */
485 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
486 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
487 "rxint_nframe", &sc->sc_rxint_nframe);
488 if (error == 0) {
489 if (sc->sc_rxint_nframe < STGE_RXINT_NFRAME_MIN ||
490 sc->sc_rxint_nframe > STGE_RXINT_NFRAME_MAX) {
491 device_printf(dev, "rxint_nframe value out of range; "
492 "using default: %d\n", STGE_RXINT_NFRAME_DEFAULT);
493 sc->sc_rxint_nframe = STGE_RXINT_NFRAME_DEFAULT;
494 }
495 }
496
497 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
498 error = resource_int_value(device_get_name(dev), device_get_unit(dev),
499 "rxint_dmawait", &sc->sc_rxint_dmawait);
500 if (error == 0) {
501 if (sc->sc_rxint_dmawait < STGE_RXINT_DMAWAIT_MIN ||
502 sc->sc_rxint_dmawait > STGE_RXINT_DMAWAIT_MAX) {
503 device_printf(dev, "rxint_dmawait value out of range; "
504 "using default: %d\n", STGE_RXINT_DMAWAIT_DEFAULT);
505 sc->sc_rxint_dmawait = STGE_RXINT_DMAWAIT_DEFAULT;
506 }
507 }
508
509 if ((error = stge_dma_alloc(sc)) != 0)
510 goto fail;
511
512 /*
513 * Determine if we're copper or fiber. It affects how we
514 * reset the card.
515 */
516 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
517 sc->sc_usefiber = 1;
518 else
519 sc->sc_usefiber = 0;
520
521 /* Load LED configuration from EEPROM. */
522 stge_read_eeprom(sc, STGE_EEPROM_LEDMode, &sc->sc_led);
523
524 /*
525 * Reset the chip to a known state.
526 */
527 STGE_LOCK(sc);
528 stge_reset(sc, STGE_RESET_FULL);
529 STGE_UNLOCK(sc);
530
531 /*
532 * Reading the station address from the EEPROM doesn't seem
533 * to work, at least on my sample boards. Instead, since
534 * the reset sequence does AutoInit, read it from the station
535 * address registers. For Sundance 1023 you can only read it
536 * from EEPROM.
537 */
538 if (pci_get_device(dev) != DEVICEID_SUNDANCETI_ST1023) {
539 uint16_t v;
540
541 v = CSR_READ_2(sc, STGE_StationAddress0);
542 enaddr[0] = v & 0xff;
543 enaddr[1] = v >> 8;
544 v = CSR_READ_2(sc, STGE_StationAddress1);
545 enaddr[2] = v & 0xff;
546 enaddr[3] = v >> 8;
547 v = CSR_READ_2(sc, STGE_StationAddress2);
548 enaddr[4] = v & 0xff;
549 enaddr[5] = v >> 8;
550 sc->sc_stge1023 = 0;
551 } else {
552 uint16_t myaddr[ETHER_ADDR_LEN / 2];
553 for (i = 0; i <ETHER_ADDR_LEN / 2; i++) {
554 stge_read_eeprom(sc, STGE_EEPROM_StationAddress0 + i,
555 &myaddr[i]);
556 myaddr[i] = le16toh(myaddr[i]);
557 }
558 bcopy(myaddr, enaddr, sizeof(enaddr));
559 sc->sc_stge1023 = 1;
560 }
561
562 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
563 if_setsoftc(ifp, sc);
564 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
565 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
566 if_setioctlfn(ifp, stge_ioctl);
567 if_setstartfn(ifp, stge_start);
568 if_setinitfn(ifp, stge_init);
569 if_setsendqlen(ifp, STGE_TX_RING_CNT - 1);
570 if_setsendqready(ifp);
571 /* Revision B3 and earlier chips have checksum bug. */
572 if (sc->sc_rev >= 0x0c) {
573 if_sethwassist(ifp, STGE_CSUM_FEATURES);
574 if_setcapabilities(ifp, IFCAP_HWCSUM);
575 } else {
576 if_sethwassist(ifp, 0);
577 if_setcapabilities(ifp, 0);
578 }
579 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
580 if_setcapenable(ifp, if_getcapabilities(ifp));
581
582 /*
583 * Read some important bits from the PhyCtrl register.
584 */
585 sc->sc_PhyCtrl = CSR_READ_1(sc, STGE_PhyCtrl) &
586 (PC_PhyDuplexPolarity | PC_PhyLnkPolarity);
587
588 /* Set up MII bus. */
589 flags = MIIF_DOPAUSE;
590 if (sc->sc_rev >= 0x40 && sc->sc_rev <= 0x4e)
591 flags |= MIIF_MACPRIV0;
592 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, stge_mediachange,
593 stge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
594 flags);
595 if (error != 0) {
596 device_printf(sc->sc_dev, "attaching PHYs failed\n");
597 goto fail;
598 }
599
600 ether_ifattach(ifp, enaddr);
601
602 /* VLAN capability setup */
603 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0);
604 if (sc->sc_rev >= 0x0c)
605 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
606 if_setcapenable(ifp, if_getcapabilities(ifp));
607 #ifdef DEVICE_POLLING
608 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
609 #endif
610 /*
611 * Tell the upper layer(s) we support long frames.
612 * Must appear after the call to ether_ifattach() because
613 * ether_ifattach() sets ifi_hdrlen to the default value.
614 */
615 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
616
617 /*
618 * The manual recommends disabling early transmit, so we
619 * do. It's disabled anyway, if using IP checksumming,
620 * since the entire packet must be in the FIFO in order
621 * for the chip to perform the checksum.
622 */
623 sc->sc_txthresh = 0x0fff;
624
625 /*
626 * Disable MWI if the PCI layer tells us to.
627 */
628 sc->sc_DMACtrl = 0;
629 if ((cmd & PCIM_CMD_MWRICEN) == 0)
630 sc->sc_DMACtrl |= DMAC_MWIDisable;
631
632 /*
633 * Hookup IRQ
634 */
635 error = bus_setup_intr(dev, sc->sc_res[1], INTR_TYPE_NET | INTR_MPSAFE,
636 NULL, stge_intr, sc, &sc->sc_ih);
637 if (error != 0) {
638 ether_ifdetach(ifp);
639 device_printf(sc->sc_dev, "couldn't set up IRQ\n");
640 sc->sc_ifp = NULL;
641 goto fail;
642 }
643
644 fail:
645 if (error != 0)
646 stge_detach(dev);
647
648 return (error);
649 }
650
651 static int
stge_detach(device_t dev)652 stge_detach(device_t dev)
653 {
654 struct stge_softc *sc;
655 if_t ifp;
656
657 sc = device_get_softc(dev);
658
659 ifp = sc->sc_ifp;
660 #ifdef DEVICE_POLLING
661 if (ifp && if_getcapenable(ifp) & IFCAP_POLLING)
662 ether_poll_deregister(ifp);
663 #endif
664 if (device_is_attached(dev)) {
665 STGE_LOCK(sc);
666 /* XXX */
667 sc->sc_detach = 1;
668 stge_stop(sc);
669 STGE_UNLOCK(sc);
670 callout_drain(&sc->sc_tick_ch);
671 taskqueue_drain(taskqueue_swi, &sc->sc_link_task);
672 ether_ifdetach(ifp);
673 }
674
675 bus_generic_detach(dev);
676 stge_dma_free(sc);
677
678 if (ifp != NULL) {
679 if_free(ifp);
680 sc->sc_ifp = NULL;
681 }
682
683 if (sc->sc_ih) {
684 bus_teardown_intr(dev, sc->sc_res[1], sc->sc_ih);
685 sc->sc_ih = NULL;
686 }
687
688 if (sc->sc_spec)
689 bus_release_resources(dev, sc->sc_spec, sc->sc_res);
690
691 mtx_destroy(&sc->sc_mii_mtx);
692 mtx_destroy(&sc->sc_mtx);
693
694 return (0);
695 }
696
697 struct stge_dmamap_arg {
698 bus_addr_t stge_busaddr;
699 };
700
701 static void
stge_dmamap_cb(void * arg,bus_dma_segment_t * segs,int nseg,int error)702 stge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
703 {
704 struct stge_dmamap_arg *ctx;
705
706 if (error != 0)
707 return;
708
709 ctx = (struct stge_dmamap_arg *)arg;
710 ctx->stge_busaddr = segs[0].ds_addr;
711 }
712
713 static int
stge_dma_alloc(struct stge_softc * sc)714 stge_dma_alloc(struct stge_softc *sc)
715 {
716 struct stge_dmamap_arg ctx;
717 struct stge_txdesc *txd;
718 struct stge_rxdesc *rxd;
719 int error, i;
720
721 /* create parent tag. */
722 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev),/* parent */
723 1, 0, /* algnmnt, boundary */
724 STGE_DMA_MAXADDR, /* lowaddr */
725 BUS_SPACE_MAXADDR, /* highaddr */
726 NULL, NULL, /* filter, filterarg */
727 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
728 0, /* nsegments */
729 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
730 0, /* flags */
731 NULL, NULL, /* lockfunc, lockarg */
732 &sc->sc_cdata.stge_parent_tag);
733 if (error != 0) {
734 device_printf(sc->sc_dev, "failed to create parent DMA tag\n");
735 goto fail;
736 }
737 /* create tag for Tx ring. */
738 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
739 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
740 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
741 BUS_SPACE_MAXADDR, /* highaddr */
742 NULL, NULL, /* filter, filterarg */
743 STGE_TX_RING_SZ, /* maxsize */
744 1, /* nsegments */
745 STGE_TX_RING_SZ, /* maxsegsize */
746 0, /* flags */
747 NULL, NULL, /* lockfunc, lockarg */
748 &sc->sc_cdata.stge_tx_ring_tag);
749 if (error != 0) {
750 device_printf(sc->sc_dev,
751 "failed to allocate Tx ring DMA tag\n");
752 goto fail;
753 }
754
755 /* create tag for Rx ring. */
756 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
757 STGE_RING_ALIGN, 0, /* algnmnt, boundary */
758 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
759 BUS_SPACE_MAXADDR, /* highaddr */
760 NULL, NULL, /* filter, filterarg */
761 STGE_RX_RING_SZ, /* maxsize */
762 1, /* nsegments */
763 STGE_RX_RING_SZ, /* maxsegsize */
764 0, /* flags */
765 NULL, NULL, /* lockfunc, lockarg */
766 &sc->sc_cdata.stge_rx_ring_tag);
767 if (error != 0) {
768 device_printf(sc->sc_dev,
769 "failed to allocate Rx ring DMA tag\n");
770 goto fail;
771 }
772
773 /* create tag for Tx buffers. */
774 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
775 1, 0, /* algnmnt, boundary */
776 BUS_SPACE_MAXADDR, /* lowaddr */
777 BUS_SPACE_MAXADDR, /* highaddr */
778 NULL, NULL, /* filter, filterarg */
779 MCLBYTES * STGE_MAXTXSEGS, /* maxsize */
780 STGE_MAXTXSEGS, /* nsegments */
781 MCLBYTES, /* maxsegsize */
782 0, /* flags */
783 NULL, NULL, /* lockfunc, lockarg */
784 &sc->sc_cdata.stge_tx_tag);
785 if (error != 0) {
786 device_printf(sc->sc_dev, "failed to allocate Tx DMA tag\n");
787 goto fail;
788 }
789
790 /* create tag for Rx buffers. */
791 error = bus_dma_tag_create(sc->sc_cdata.stge_parent_tag,/* parent */
792 1, 0, /* algnmnt, boundary */
793 BUS_SPACE_MAXADDR, /* lowaddr */
794 BUS_SPACE_MAXADDR, /* highaddr */
795 NULL, NULL, /* filter, filterarg */
796 MCLBYTES, /* maxsize */
797 1, /* nsegments */
798 MCLBYTES, /* maxsegsize */
799 0, /* flags */
800 NULL, NULL, /* lockfunc, lockarg */
801 &sc->sc_cdata.stge_rx_tag);
802 if (error != 0) {
803 device_printf(sc->sc_dev, "failed to allocate Rx DMA tag\n");
804 goto fail;
805 }
806
807 /* allocate DMA'able memory and load the DMA map for Tx ring. */
808 error = bus_dmamem_alloc(sc->sc_cdata.stge_tx_ring_tag,
809 (void **)&sc->sc_rdata.stge_tx_ring, BUS_DMA_NOWAIT |
810 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_tx_ring_map);
811 if (error != 0) {
812 device_printf(sc->sc_dev,
813 "failed to allocate DMA'able memory for Tx ring\n");
814 goto fail;
815 }
816
817 ctx.stge_busaddr = 0;
818 error = bus_dmamap_load(sc->sc_cdata.stge_tx_ring_tag,
819 sc->sc_cdata.stge_tx_ring_map, sc->sc_rdata.stge_tx_ring,
820 STGE_TX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
821 if (error != 0 || ctx.stge_busaddr == 0) {
822 device_printf(sc->sc_dev,
823 "failed to load DMA'able memory for Tx ring\n");
824 goto fail;
825 }
826 sc->sc_rdata.stge_tx_ring_paddr = ctx.stge_busaddr;
827
828 /* allocate DMA'able memory and load the DMA map for Rx ring. */
829 error = bus_dmamem_alloc(sc->sc_cdata.stge_rx_ring_tag,
830 (void **)&sc->sc_rdata.stge_rx_ring, BUS_DMA_NOWAIT |
831 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->sc_cdata.stge_rx_ring_map);
832 if (error != 0) {
833 device_printf(sc->sc_dev,
834 "failed to allocate DMA'able memory for Rx ring\n");
835 goto fail;
836 }
837
838 ctx.stge_busaddr = 0;
839 error = bus_dmamap_load(sc->sc_cdata.stge_rx_ring_tag,
840 sc->sc_cdata.stge_rx_ring_map, sc->sc_rdata.stge_rx_ring,
841 STGE_RX_RING_SZ, stge_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
842 if (error != 0 || ctx.stge_busaddr == 0) {
843 device_printf(sc->sc_dev,
844 "failed to load DMA'able memory for Rx ring\n");
845 goto fail;
846 }
847 sc->sc_rdata.stge_rx_ring_paddr = ctx.stge_busaddr;
848
849 /* create DMA maps for Tx buffers. */
850 for (i = 0; i < STGE_TX_RING_CNT; i++) {
851 txd = &sc->sc_cdata.stge_txdesc[i];
852 txd->tx_m = NULL;
853 txd->tx_dmamap = 0;
854 error = bus_dmamap_create(sc->sc_cdata.stge_tx_tag, 0,
855 &txd->tx_dmamap);
856 if (error != 0) {
857 device_printf(sc->sc_dev,
858 "failed to create Tx dmamap\n");
859 goto fail;
860 }
861 }
862 /* create DMA maps for Rx buffers. */
863 if ((error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
864 &sc->sc_cdata.stge_rx_sparemap)) != 0) {
865 device_printf(sc->sc_dev, "failed to create spare Rx dmamap\n");
866 goto fail;
867 }
868 for (i = 0; i < STGE_RX_RING_CNT; i++) {
869 rxd = &sc->sc_cdata.stge_rxdesc[i];
870 rxd->rx_m = NULL;
871 rxd->rx_dmamap = 0;
872 error = bus_dmamap_create(sc->sc_cdata.stge_rx_tag, 0,
873 &rxd->rx_dmamap);
874 if (error != 0) {
875 device_printf(sc->sc_dev,
876 "failed to create Rx dmamap\n");
877 goto fail;
878 }
879 }
880
881 fail:
882 return (error);
883 }
884
885 static void
stge_dma_free(struct stge_softc * sc)886 stge_dma_free(struct stge_softc *sc)
887 {
888 struct stge_txdesc *txd;
889 struct stge_rxdesc *rxd;
890 int i;
891
892 /* Tx ring */
893 if (sc->sc_cdata.stge_tx_ring_tag) {
894 if (sc->sc_rdata.stge_tx_ring_paddr)
895 bus_dmamap_unload(sc->sc_cdata.stge_tx_ring_tag,
896 sc->sc_cdata.stge_tx_ring_map);
897 if (sc->sc_rdata.stge_tx_ring)
898 bus_dmamem_free(sc->sc_cdata.stge_tx_ring_tag,
899 sc->sc_rdata.stge_tx_ring,
900 sc->sc_cdata.stge_tx_ring_map);
901 sc->sc_rdata.stge_tx_ring = NULL;
902 sc->sc_rdata.stge_tx_ring_paddr = 0;
903 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_ring_tag);
904 sc->sc_cdata.stge_tx_ring_tag = NULL;
905 }
906 /* Rx ring */
907 if (sc->sc_cdata.stge_rx_ring_tag) {
908 if (sc->sc_rdata.stge_rx_ring_paddr)
909 bus_dmamap_unload(sc->sc_cdata.stge_rx_ring_tag,
910 sc->sc_cdata.stge_rx_ring_map);
911 if (sc->sc_rdata.stge_rx_ring)
912 bus_dmamem_free(sc->sc_cdata.stge_rx_ring_tag,
913 sc->sc_rdata.stge_rx_ring,
914 sc->sc_cdata.stge_rx_ring_map);
915 sc->sc_rdata.stge_rx_ring = NULL;
916 sc->sc_rdata.stge_rx_ring_paddr = 0;
917 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_ring_tag);
918 sc->sc_cdata.stge_rx_ring_tag = NULL;
919 }
920 /* Tx buffers */
921 if (sc->sc_cdata.stge_tx_tag) {
922 for (i = 0; i < STGE_TX_RING_CNT; i++) {
923 txd = &sc->sc_cdata.stge_txdesc[i];
924 if (txd->tx_dmamap) {
925 bus_dmamap_destroy(sc->sc_cdata.stge_tx_tag,
926 txd->tx_dmamap);
927 txd->tx_dmamap = 0;
928 }
929 }
930 bus_dma_tag_destroy(sc->sc_cdata.stge_tx_tag);
931 sc->sc_cdata.stge_tx_tag = NULL;
932 }
933 /* Rx buffers */
934 if (sc->sc_cdata.stge_rx_tag) {
935 for (i = 0; i < STGE_RX_RING_CNT; i++) {
936 rxd = &sc->sc_cdata.stge_rxdesc[i];
937 if (rxd->rx_dmamap) {
938 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
939 rxd->rx_dmamap);
940 rxd->rx_dmamap = 0;
941 }
942 }
943 if (sc->sc_cdata.stge_rx_sparemap) {
944 bus_dmamap_destroy(sc->sc_cdata.stge_rx_tag,
945 sc->sc_cdata.stge_rx_sparemap);
946 sc->sc_cdata.stge_rx_sparemap = 0;
947 }
948 bus_dma_tag_destroy(sc->sc_cdata.stge_rx_tag);
949 sc->sc_cdata.stge_rx_tag = NULL;
950 }
951
952 if (sc->sc_cdata.stge_parent_tag) {
953 bus_dma_tag_destroy(sc->sc_cdata.stge_parent_tag);
954 sc->sc_cdata.stge_parent_tag = NULL;
955 }
956 }
957
958 /*
959 * stge_shutdown:
960 *
961 * Make sure the interface is stopped at reboot time.
962 */
963 static int
stge_shutdown(device_t dev)964 stge_shutdown(device_t dev)
965 {
966
967 return (stge_suspend(dev));
968 }
969
970 static void
stge_setwol(struct stge_softc * sc)971 stge_setwol(struct stge_softc *sc)
972 {
973 if_t ifp;
974 uint8_t v;
975
976 STGE_LOCK_ASSERT(sc);
977
978 ifp = sc->sc_ifp;
979 v = CSR_READ_1(sc, STGE_WakeEvent);
980 /* Disable all WOL bits. */
981 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
982 WE_WakeOnLanEnable);
983 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0)
984 v |= WE_MagicPktEnable | WE_WakeOnLanEnable;
985 CSR_WRITE_1(sc, STGE_WakeEvent, v);
986 /* Reset Tx and prevent transmission. */
987 CSR_WRITE_4(sc, STGE_AsicCtrl,
988 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset);
989 /*
990 * TC9021 automatically reset link speed to 100Mbps when it's put
991 * into sleep so there is no need to try to resetting link speed.
992 */
993 }
994
995 static int
stge_suspend(device_t dev)996 stge_suspend(device_t dev)
997 {
998 struct stge_softc *sc;
999
1000 sc = device_get_softc(dev);
1001
1002 STGE_LOCK(sc);
1003 stge_stop(sc);
1004 sc->sc_suspended = 1;
1005 stge_setwol(sc);
1006 STGE_UNLOCK(sc);
1007
1008 return (0);
1009 }
1010
1011 static int
stge_resume(device_t dev)1012 stge_resume(device_t dev)
1013 {
1014 struct stge_softc *sc;
1015 if_t ifp;
1016 uint8_t v;
1017
1018 sc = device_get_softc(dev);
1019
1020 STGE_LOCK(sc);
1021 /*
1022 * Clear WOL bits, so special frames wouldn't interfere
1023 * normal Rx operation anymore.
1024 */
1025 v = CSR_READ_1(sc, STGE_WakeEvent);
1026 v &= ~(WE_WakePktEnable | WE_MagicPktEnable | WE_LinkEventEnable |
1027 WE_WakeOnLanEnable);
1028 CSR_WRITE_1(sc, STGE_WakeEvent, v);
1029 ifp = sc->sc_ifp;
1030 if (if_getflags(ifp) & IFF_UP)
1031 stge_init_locked(sc);
1032
1033 sc->sc_suspended = 0;
1034 STGE_UNLOCK(sc);
1035
1036 return (0);
1037 }
1038
1039 static void
stge_dma_wait(struct stge_softc * sc)1040 stge_dma_wait(struct stge_softc *sc)
1041 {
1042 int i;
1043
1044 for (i = 0; i < STGE_TIMEOUT; i++) {
1045 DELAY(2);
1046 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1047 break;
1048 }
1049
1050 if (i == STGE_TIMEOUT)
1051 device_printf(sc->sc_dev, "DMA wait timed out\n");
1052 }
1053
1054 static int
stge_encap(struct stge_softc * sc,struct mbuf ** m_head)1055 stge_encap(struct stge_softc *sc, struct mbuf **m_head)
1056 {
1057 struct stge_txdesc *txd;
1058 struct stge_tfd *tfd;
1059 struct mbuf *m;
1060 bus_dma_segment_t txsegs[STGE_MAXTXSEGS];
1061 int error, i, nsegs, si;
1062 uint64_t csum_flags, tfc;
1063
1064 STGE_LOCK_ASSERT(sc);
1065
1066 if ((txd = STAILQ_FIRST(&sc->sc_cdata.stge_txfreeq)) == NULL)
1067 return (ENOBUFS);
1068
1069 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1070 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1071 if (error == EFBIG) {
1072 m = m_collapse(*m_head, M_NOWAIT, STGE_MAXTXSEGS);
1073 if (m == NULL) {
1074 m_freem(*m_head);
1075 *m_head = NULL;
1076 return (ENOMEM);
1077 }
1078 *m_head = m;
1079 error = bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_tx_tag,
1080 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0);
1081 if (error != 0) {
1082 m_freem(*m_head);
1083 *m_head = NULL;
1084 return (error);
1085 }
1086 } else if (error != 0)
1087 return (error);
1088 if (nsegs == 0) {
1089 m_freem(*m_head);
1090 *m_head = NULL;
1091 return (EIO);
1092 }
1093
1094 m = *m_head;
1095 csum_flags = 0;
1096 if ((m->m_pkthdr.csum_flags & STGE_CSUM_FEATURES) != 0) {
1097 if (m->m_pkthdr.csum_flags & CSUM_IP)
1098 csum_flags |= TFD_IPChecksumEnable;
1099 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1100 csum_flags |= TFD_TCPChecksumEnable;
1101 else if (m->m_pkthdr.csum_flags & CSUM_UDP)
1102 csum_flags |= TFD_UDPChecksumEnable;
1103 }
1104
1105 si = sc->sc_cdata.stge_tx_prod;
1106 tfd = &sc->sc_rdata.stge_tx_ring[si];
1107 for (i = 0; i < nsegs; i++)
1108 tfd->tfd_frags[i].frag_word0 =
1109 htole64(FRAG_ADDR(txsegs[i].ds_addr) |
1110 FRAG_LEN(txsegs[i].ds_len));
1111 sc->sc_cdata.stge_tx_cnt++;
1112
1113 tfc = TFD_FrameId(si) | TFD_WordAlign(TFD_WordAlign_disable) |
1114 TFD_FragCount(nsegs) | csum_flags;
1115 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT)
1116 tfc |= TFD_TxDMAIndicate;
1117
1118 /* Update producer index. */
1119 sc->sc_cdata.stge_tx_prod = (si + 1) % STGE_TX_RING_CNT;
1120
1121 /* Check if we have a VLAN tag to insert. */
1122 if (m->m_flags & M_VLANTAG)
1123 tfc |= (TFD_VLANTagInsert | TFD_VID(m->m_pkthdr.ether_vtag));
1124 tfd->tfd_control = htole64(tfc);
1125
1126 /* Update Tx Queue. */
1127 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txfreeq, tx_q);
1128 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txbusyq, txd, tx_q);
1129 txd->tx_m = m;
1130
1131 /* Sync descriptors. */
1132 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1133 BUS_DMASYNC_PREWRITE);
1134 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1135 sc->sc_cdata.stge_tx_ring_map,
1136 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1137
1138 return (0);
1139 }
1140
1141 /*
1142 * stge_start: [ifnet interface function]
1143 *
1144 * Start packet transmission on the interface.
1145 */
1146 static void
stge_start(if_t ifp)1147 stge_start(if_t ifp)
1148 {
1149 struct stge_softc *sc;
1150
1151 sc = if_getsoftc(ifp);
1152 STGE_LOCK(sc);
1153 stge_start_locked(ifp);
1154 STGE_UNLOCK(sc);
1155 }
1156
1157 static void
stge_start_locked(if_t ifp)1158 stge_start_locked(if_t ifp)
1159 {
1160 struct stge_softc *sc;
1161 struct mbuf *m_head;
1162 int enq;
1163
1164 sc = if_getsoftc(ifp);
1165
1166 STGE_LOCK_ASSERT(sc);
1167
1168 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
1169 IFF_DRV_RUNNING || sc->sc_link == 0)
1170 return;
1171
1172 for (enq = 0; !if_sendq_empty(ifp); ) {
1173 if (sc->sc_cdata.stge_tx_cnt >= STGE_TX_HIWAT) {
1174 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1175 break;
1176 }
1177
1178 m_head = if_dequeue(ifp);
1179 if (m_head == NULL)
1180 break;
1181 /*
1182 * Pack the data into the transmit ring. If we
1183 * don't have room, set the OACTIVE flag and wait
1184 * for the NIC to drain the ring.
1185 */
1186 if (stge_encap(sc, &m_head)) {
1187 if (m_head == NULL)
1188 break;
1189 if_sendq_prepend(ifp, m_head);
1190 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1191 break;
1192 }
1193
1194 enq++;
1195 /*
1196 * If there's a BPF listener, bounce a copy of this frame
1197 * to him.
1198 */
1199 ETHER_BPF_MTAP(ifp, m_head);
1200 }
1201
1202 if (enq > 0) {
1203 /* Transmit */
1204 CSR_WRITE_4(sc, STGE_DMACtrl, DMAC_TxDMAPollNow);
1205
1206 /* Set a timeout in case the chip goes out to lunch. */
1207 sc->sc_watchdog_timer = 5;
1208 }
1209 }
1210
1211 /*
1212 * stge_watchdog:
1213 *
1214 * Watchdog timer handler.
1215 */
1216 static void
stge_watchdog(struct stge_softc * sc)1217 stge_watchdog(struct stge_softc *sc)
1218 {
1219 if_t ifp;
1220
1221 STGE_LOCK_ASSERT(sc);
1222
1223 if (sc->sc_watchdog_timer == 0 || --sc->sc_watchdog_timer)
1224 return;
1225
1226 ifp = sc->sc_ifp;
1227 if_printf(sc->sc_ifp, "device timeout\n");
1228 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1229 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1230 stge_init_locked(sc);
1231 if (!if_sendq_empty(ifp))
1232 stge_start_locked(ifp);
1233 }
1234
1235 /*
1236 * stge_ioctl: [ifnet interface function]
1237 *
1238 * Handle control requests from the operator.
1239 */
1240 static int
stge_ioctl(if_t ifp,u_long cmd,caddr_t data)1241 stge_ioctl(if_t ifp, u_long cmd, caddr_t data)
1242 {
1243 struct stge_softc *sc;
1244 struct ifreq *ifr;
1245 struct mii_data *mii;
1246 int error, mask;
1247
1248 sc = if_getsoftc(ifp);
1249 ifr = (struct ifreq *)data;
1250 error = 0;
1251 switch (cmd) {
1252 case SIOCSIFMTU:
1253 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > STGE_JUMBO_MTU)
1254 error = EINVAL;
1255 else if (if_getmtu(ifp) != ifr->ifr_mtu) {
1256 if_setmtu(ifp, ifr->ifr_mtu);
1257 STGE_LOCK(sc);
1258 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1259 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1260 stge_init_locked(sc);
1261 }
1262 STGE_UNLOCK(sc);
1263 }
1264 break;
1265 case SIOCSIFFLAGS:
1266 STGE_LOCK(sc);
1267 if ((if_getflags(ifp) & IFF_UP) != 0) {
1268 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1269 if (((if_getflags(ifp) ^ sc->sc_if_flags)
1270 & IFF_PROMISC) != 0)
1271 stge_set_filter(sc);
1272 } else {
1273 if (sc->sc_detach == 0)
1274 stge_init_locked(sc);
1275 }
1276 } else {
1277 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1278 stge_stop(sc);
1279 }
1280 sc->sc_if_flags = if_getflags(ifp);
1281 STGE_UNLOCK(sc);
1282 break;
1283 case SIOCADDMULTI:
1284 case SIOCDELMULTI:
1285 STGE_LOCK(sc);
1286 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1287 stge_set_multi(sc);
1288 STGE_UNLOCK(sc);
1289 break;
1290 case SIOCSIFMEDIA:
1291 case SIOCGIFMEDIA:
1292 mii = device_get_softc(sc->sc_miibus);
1293 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1294 break;
1295 case SIOCSIFCAP:
1296 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
1297 #ifdef DEVICE_POLLING
1298 if ((mask & IFCAP_POLLING) != 0) {
1299 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) {
1300 error = ether_poll_register(stge_poll, ifp);
1301 if (error != 0)
1302 break;
1303 STGE_LOCK(sc);
1304 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1305 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1306 STGE_UNLOCK(sc);
1307 } else {
1308 error = ether_poll_deregister(ifp);
1309 if (error != 0)
1310 break;
1311 STGE_LOCK(sc);
1312 CSR_WRITE_2(sc, STGE_IntEnable,
1313 sc->sc_IntEnable);
1314 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1315 STGE_UNLOCK(sc);
1316 }
1317 }
1318 #endif
1319 if ((mask & IFCAP_HWCSUM) != 0) {
1320 if_togglecapenable(ifp, IFCAP_HWCSUM);
1321 if ((IFCAP_HWCSUM & if_getcapenable(ifp)) != 0 &&
1322 (IFCAP_HWCSUM & if_getcapabilities(ifp)) != 0)
1323 if_sethwassist(ifp, STGE_CSUM_FEATURES);
1324 else
1325 if_sethwassist(ifp, 0);
1326 }
1327 if ((mask & IFCAP_WOL) != 0 &&
1328 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) {
1329 if ((mask & IFCAP_WOL_MAGIC) != 0)
1330 if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
1331 }
1332 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
1333 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
1334 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1335 STGE_LOCK(sc);
1336 stge_vlan_setup(sc);
1337 STGE_UNLOCK(sc);
1338 }
1339 }
1340 VLAN_CAPABILITIES(ifp);
1341 break;
1342 default:
1343 error = ether_ioctl(ifp, cmd, data);
1344 break;
1345 }
1346
1347 return (error);
1348 }
1349
1350 static void
stge_link_task(void * arg,int pending)1351 stge_link_task(void *arg, int pending)
1352 {
1353 struct stge_softc *sc;
1354 struct mii_data *mii;
1355 uint32_t v, ac;
1356 int i;
1357
1358 sc = (struct stge_softc *)arg;
1359 STGE_LOCK(sc);
1360
1361 mii = device_get_softc(sc->sc_miibus);
1362 if (mii->mii_media_status & IFM_ACTIVE) {
1363 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1364 sc->sc_link = 1;
1365 } else
1366 sc->sc_link = 0;
1367
1368 sc->sc_MACCtrl = 0;
1369 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0)
1370 sc->sc_MACCtrl |= MC_DuplexSelect;
1371 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_RXPAUSE) != 0)
1372 sc->sc_MACCtrl |= MC_RxFlowControlEnable;
1373 if (((mii->mii_media_active & IFM_GMASK) & IFM_ETH_TXPAUSE) != 0)
1374 sc->sc_MACCtrl |= MC_TxFlowControlEnable;
1375 /*
1376 * Update STGE_MACCtrl register depending on link status.
1377 * (duplex, flow control etc)
1378 */
1379 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
1380 v &= ~(MC_DuplexSelect|MC_RxFlowControlEnable|MC_TxFlowControlEnable);
1381 v |= sc->sc_MACCtrl;
1382 CSR_WRITE_4(sc, STGE_MACCtrl, v);
1383 if (((ac ^ sc->sc_MACCtrl) & MC_DuplexSelect) != 0) {
1384 /* Duplex setting changed, reset Tx/Rx functions. */
1385 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1386 ac |= AC_TxReset | AC_RxReset;
1387 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1388 for (i = 0; i < STGE_TIMEOUT; i++) {
1389 DELAY(100);
1390 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1391 break;
1392 }
1393 if (i == STGE_TIMEOUT)
1394 device_printf(sc->sc_dev, "reset failed to complete\n");
1395 }
1396 STGE_UNLOCK(sc);
1397 }
1398
1399 static __inline int
stge_tx_error(struct stge_softc * sc)1400 stge_tx_error(struct stge_softc *sc)
1401 {
1402 uint32_t txstat;
1403 int error;
1404
1405 for (error = 0;;) {
1406 txstat = CSR_READ_4(sc, STGE_TxStatus);
1407 if ((txstat & TS_TxComplete) == 0)
1408 break;
1409 /* Tx underrun */
1410 if ((txstat & TS_TxUnderrun) != 0) {
1411 /*
1412 * XXX
1413 * There should be a more better way to recover
1414 * from Tx underrun instead of a full reset.
1415 */
1416 if (sc->sc_nerr++ < STGE_MAXERR)
1417 device_printf(sc->sc_dev, "Tx underrun, "
1418 "resetting...\n");
1419 if (sc->sc_nerr == STGE_MAXERR)
1420 device_printf(sc->sc_dev, "too many errors; "
1421 "not reporting any more\n");
1422 error = -1;
1423 break;
1424 }
1425 /* Maximum/Late collisions, Re-enable Tx MAC. */
1426 if ((txstat & (TS_MaxCollisions|TS_LateCollision)) != 0)
1427 CSR_WRITE_4(sc, STGE_MACCtrl,
1428 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) |
1429 MC_TxEnable);
1430 }
1431
1432 return (error);
1433 }
1434
1435 /*
1436 * stge_intr:
1437 *
1438 * Interrupt service routine.
1439 */
1440 static void
stge_intr(void * arg)1441 stge_intr(void *arg)
1442 {
1443 struct stge_softc *sc;
1444 if_t ifp;
1445 int reinit;
1446 uint16_t status;
1447
1448 sc = (struct stge_softc *)arg;
1449 ifp = sc->sc_ifp;
1450
1451 STGE_LOCK(sc);
1452
1453 #ifdef DEVICE_POLLING
1454 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0)
1455 goto done_locked;
1456 #endif
1457 status = CSR_READ_2(sc, STGE_IntStatus);
1458 if (sc->sc_suspended || (status & IS_InterruptStatus) == 0)
1459 goto done_locked;
1460
1461 /* Disable interrupts. */
1462 for (reinit = 0;;) {
1463 status = CSR_READ_2(sc, STGE_IntStatusAck);
1464 status &= sc->sc_IntEnable;
1465 if (status == 0)
1466 break;
1467 /* Host interface errors. */
1468 if ((status & IS_HostError) != 0) {
1469 device_printf(sc->sc_dev,
1470 "Host interface error, resetting...\n");
1471 reinit = 1;
1472 goto force_init;
1473 }
1474
1475 /* Receive interrupts. */
1476 if ((status & IS_RxDMAComplete) != 0) {
1477 stge_rxeof(sc);
1478 if ((status & IS_RFDListEnd) != 0)
1479 CSR_WRITE_4(sc, STGE_DMACtrl,
1480 DMAC_RxDMAPollNow);
1481 }
1482
1483 /* Transmit interrupts. */
1484 if ((status & (IS_TxDMAComplete | IS_TxComplete)) != 0)
1485 stge_txeof(sc);
1486
1487 /* Transmission errors.*/
1488 if ((status & IS_TxComplete) != 0) {
1489 if ((reinit = stge_tx_error(sc)) != 0)
1490 break;
1491 }
1492 }
1493
1494 force_init:
1495 if (reinit != 0) {
1496 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1497 stge_init_locked(sc);
1498 }
1499
1500 /* Re-enable interrupts. */
1501 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1502
1503 /* Try to get more packets going. */
1504 if (!if_sendq_empty(ifp))
1505 stge_start_locked(ifp);
1506
1507 done_locked:
1508 STGE_UNLOCK(sc);
1509 }
1510
1511 /*
1512 * stge_txeof:
1513 *
1514 * Helper; handle transmit interrupts.
1515 */
1516 static void
stge_txeof(struct stge_softc * sc)1517 stge_txeof(struct stge_softc *sc)
1518 {
1519 if_t ifp;
1520 struct stge_txdesc *txd;
1521 uint64_t control;
1522 int cons;
1523
1524 STGE_LOCK_ASSERT(sc);
1525
1526 ifp = sc->sc_ifp;
1527
1528 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1529 if (txd == NULL)
1530 return;
1531 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1532 sc->sc_cdata.stge_tx_ring_map, BUS_DMASYNC_POSTREAD);
1533
1534 /*
1535 * Go through our Tx list and free mbufs for those
1536 * frames which have been transmitted.
1537 */
1538 for (cons = sc->sc_cdata.stge_tx_cons;;
1539 cons = (cons + 1) % STGE_TX_RING_CNT) {
1540 if (sc->sc_cdata.stge_tx_cnt <= 0)
1541 break;
1542 control = le64toh(sc->sc_rdata.stge_tx_ring[cons].tfd_control);
1543 if ((control & TFD_TFDDone) == 0)
1544 break;
1545 sc->sc_cdata.stge_tx_cnt--;
1546 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1547
1548 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap,
1549 BUS_DMASYNC_POSTWRITE);
1550 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag, txd->tx_dmamap);
1551
1552 /* Output counter is updated with statistics register */
1553 m_freem(txd->tx_m);
1554 txd->tx_m = NULL;
1555 STAILQ_REMOVE_HEAD(&sc->sc_cdata.stge_txbusyq, tx_q);
1556 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
1557 txd = STAILQ_FIRST(&sc->sc_cdata.stge_txbusyq);
1558 }
1559 sc->sc_cdata.stge_tx_cons = cons;
1560 if (sc->sc_cdata.stge_tx_cnt == 0)
1561 sc->sc_watchdog_timer = 0;
1562
1563 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
1564 sc->sc_cdata.stge_tx_ring_map,
1565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1566 }
1567
1568 static __inline void
stge_discard_rxbuf(struct stge_softc * sc,int idx)1569 stge_discard_rxbuf(struct stge_softc *sc, int idx)
1570 {
1571 struct stge_rfd *rfd;
1572
1573 rfd = &sc->sc_rdata.stge_rx_ring[idx];
1574 rfd->rfd_status = 0;
1575 }
1576
1577 #ifndef __NO_STRICT_ALIGNMENT
1578 /*
1579 * It seems that TC9021's DMA engine has alignment restrictions in
1580 * DMA scatter operations. The first DMA segment has no address
1581 * alignment restrictins but the rest should be aligned on 4(?) bytes
1582 * boundary. Otherwise it would corrupt random memory. Since we don't
1583 * know which one is used for the first segment in advance we simply
1584 * don't align at all.
1585 * To avoid copying over an entire frame to align, we allocate a new
1586 * mbuf and copy ethernet header to the new mbuf. The new mbuf is
1587 * prepended into the existing mbuf chain.
1588 */
1589 static __inline struct mbuf *
stge_fixup_rx(struct stge_softc * sc,struct mbuf * m)1590 stge_fixup_rx(struct stge_softc *sc, struct mbuf *m)
1591 {
1592 struct mbuf *n;
1593
1594 n = NULL;
1595 if (m->m_len <= (MCLBYTES - ETHER_HDR_LEN)) {
1596 bcopy(m->m_data, m->m_data + ETHER_HDR_LEN, m->m_len);
1597 m->m_data += ETHER_HDR_LEN;
1598 n = m;
1599 } else {
1600 MGETHDR(n, M_NOWAIT, MT_DATA);
1601 if (n != NULL) {
1602 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
1603 m->m_data += ETHER_HDR_LEN;
1604 m->m_len -= ETHER_HDR_LEN;
1605 n->m_len = ETHER_HDR_LEN;
1606 M_MOVE_PKTHDR(n, m);
1607 n->m_next = m;
1608 } else
1609 m_freem(m);
1610 }
1611
1612 return (n);
1613 }
1614 #endif
1615
1616 /*
1617 * stge_rxeof:
1618 *
1619 * Helper; handle receive interrupts.
1620 */
1621 static int
stge_rxeof(struct stge_softc * sc)1622 stge_rxeof(struct stge_softc *sc)
1623 {
1624 if_t ifp;
1625 struct stge_rxdesc *rxd;
1626 struct mbuf *mp, *m;
1627 uint64_t status64;
1628 uint32_t status;
1629 int cons, prog, rx_npkts;
1630
1631 STGE_LOCK_ASSERT(sc);
1632
1633 rx_npkts = 0;
1634 ifp = sc->sc_ifp;
1635
1636 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1637 sc->sc_cdata.stge_rx_ring_map, BUS_DMASYNC_POSTREAD);
1638
1639 prog = 0;
1640 for (cons = sc->sc_cdata.stge_rx_cons; prog < STGE_RX_RING_CNT;
1641 prog++, cons = (cons + 1) % STGE_RX_RING_CNT) {
1642 status64 = le64toh(sc->sc_rdata.stge_rx_ring[cons].rfd_status);
1643 status = RFD_RxStatus(status64);
1644 if ((status & RFD_RFDDone) == 0)
1645 break;
1646 #ifdef DEVICE_POLLING
1647 if (if_getcapenable(ifp) & IFCAP_POLLING) {
1648 if (sc->sc_cdata.stge_rxcycles <= 0)
1649 break;
1650 sc->sc_cdata.stge_rxcycles--;
1651 }
1652 #endif
1653 prog++;
1654 rxd = &sc->sc_cdata.stge_rxdesc[cons];
1655 mp = rxd->rx_m;
1656
1657 /*
1658 * If the packet had an error, drop it. Note we count
1659 * the error later in the periodic stats update.
1660 */
1661 if ((status & RFD_FrameEnd) != 0 && (status &
1662 (RFD_RxFIFOOverrun | RFD_RxRuntFrame |
1663 RFD_RxAlignmentError | RFD_RxFCSError |
1664 RFD_RxLengthError)) != 0) {
1665 stge_discard_rxbuf(sc, cons);
1666 if (sc->sc_cdata.stge_rxhead != NULL) {
1667 m_freem(sc->sc_cdata.stge_rxhead);
1668 STGE_RXCHAIN_RESET(sc);
1669 }
1670 continue;
1671 }
1672 /*
1673 * Add a new receive buffer to the ring.
1674 */
1675 if (stge_newbuf(sc, cons) != 0) {
1676 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1677 stge_discard_rxbuf(sc, cons);
1678 if (sc->sc_cdata.stge_rxhead != NULL) {
1679 m_freem(sc->sc_cdata.stge_rxhead);
1680 STGE_RXCHAIN_RESET(sc);
1681 }
1682 continue;
1683 }
1684
1685 if ((status & RFD_FrameEnd) != 0)
1686 mp->m_len = RFD_RxDMAFrameLen(status) -
1687 sc->sc_cdata.stge_rxlen;
1688 sc->sc_cdata.stge_rxlen += mp->m_len;
1689
1690 /* Chain mbufs. */
1691 if (sc->sc_cdata.stge_rxhead == NULL) {
1692 sc->sc_cdata.stge_rxhead = mp;
1693 sc->sc_cdata.stge_rxtail = mp;
1694 } else {
1695 mp->m_flags &= ~M_PKTHDR;
1696 sc->sc_cdata.stge_rxtail->m_next = mp;
1697 sc->sc_cdata.stge_rxtail = mp;
1698 }
1699
1700 if ((status & RFD_FrameEnd) != 0) {
1701 m = sc->sc_cdata.stge_rxhead;
1702 m->m_pkthdr.rcvif = ifp;
1703 m->m_pkthdr.len = sc->sc_cdata.stge_rxlen;
1704
1705 if (m->m_pkthdr.len > sc->sc_if_framesize) {
1706 m_freem(m);
1707 STGE_RXCHAIN_RESET(sc);
1708 continue;
1709 }
1710 /*
1711 * Set the incoming checksum information for
1712 * the packet.
1713 */
1714 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
1715 if ((status & RFD_IPDetected) != 0) {
1716 m->m_pkthdr.csum_flags |=
1717 CSUM_IP_CHECKED;
1718 if ((status & RFD_IPError) == 0)
1719 m->m_pkthdr.csum_flags |=
1720 CSUM_IP_VALID;
1721 }
1722 if (((status & RFD_TCPDetected) != 0 &&
1723 (status & RFD_TCPError) == 0) ||
1724 ((status & RFD_UDPDetected) != 0 &&
1725 (status & RFD_UDPError) == 0)) {
1726 m->m_pkthdr.csum_flags |=
1727 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1728 m->m_pkthdr.csum_data = 0xffff;
1729 }
1730 }
1731
1732 #ifndef __NO_STRICT_ALIGNMENT
1733 if (sc->sc_if_framesize > (MCLBYTES - ETHER_ALIGN)) {
1734 if ((m = stge_fixup_rx(sc, m)) == NULL) {
1735 STGE_RXCHAIN_RESET(sc);
1736 continue;
1737 }
1738 }
1739 #endif
1740 /* Check for VLAN tagged packets. */
1741 if ((status & RFD_VLANDetected) != 0 &&
1742 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
1743 m->m_pkthdr.ether_vtag = RFD_TCI(status64);
1744 m->m_flags |= M_VLANTAG;
1745 }
1746
1747 STGE_UNLOCK(sc);
1748 /* Pass it on. */
1749 if_input(ifp, m);
1750 STGE_LOCK(sc);
1751 rx_npkts++;
1752
1753 STGE_RXCHAIN_RESET(sc);
1754 }
1755 }
1756
1757 if (prog > 0) {
1758 /* Update the consumer index. */
1759 sc->sc_cdata.stge_rx_cons = cons;
1760 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
1761 sc->sc_cdata.stge_rx_ring_map,
1762 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1763 }
1764 return (rx_npkts);
1765 }
1766
1767 #ifdef DEVICE_POLLING
1768 static int
stge_poll(if_t ifp,enum poll_cmd cmd,int count)1769 stge_poll(if_t ifp, enum poll_cmd cmd, int count)
1770 {
1771 struct stge_softc *sc;
1772 uint16_t status;
1773 int rx_npkts;
1774
1775 rx_npkts = 0;
1776 sc = if_getsoftc(ifp);
1777 STGE_LOCK(sc);
1778 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
1779 STGE_UNLOCK(sc);
1780 return (rx_npkts);
1781 }
1782
1783 sc->sc_cdata.stge_rxcycles = count;
1784 rx_npkts = stge_rxeof(sc);
1785 stge_txeof(sc);
1786
1787 if (cmd == POLL_AND_CHECK_STATUS) {
1788 status = CSR_READ_2(sc, STGE_IntStatus);
1789 status &= sc->sc_IntEnable;
1790 if (status != 0) {
1791 if ((status & IS_HostError) != 0) {
1792 device_printf(sc->sc_dev,
1793 "Host interface error, resetting...\n");
1794 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1795 stge_init_locked(sc);
1796 }
1797 if ((status & IS_TxComplete) != 0) {
1798 if (stge_tx_error(sc) != 0) {
1799 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1800 stge_init_locked(sc);
1801 }
1802 }
1803 }
1804 }
1805
1806 if (!if_sendq_empty(ifp))
1807 stge_start_locked(ifp);
1808
1809 STGE_UNLOCK(sc);
1810 return (rx_npkts);
1811 }
1812 #endif /* DEVICE_POLLING */
1813
1814 /*
1815 * stge_tick:
1816 *
1817 * One second timer, used to tick the MII.
1818 */
1819 static void
stge_tick(void * arg)1820 stge_tick(void *arg)
1821 {
1822 struct stge_softc *sc;
1823 struct mii_data *mii;
1824
1825 sc = (struct stge_softc *)arg;
1826
1827 STGE_LOCK_ASSERT(sc);
1828
1829 mii = device_get_softc(sc->sc_miibus);
1830 mii_tick(mii);
1831
1832 /* Update statistics counters. */
1833 stge_stats_update(sc);
1834
1835 /*
1836 * Relcaim any pending Tx descriptors to release mbufs in a
1837 * timely manner as we don't generate Tx completion interrupts
1838 * for every frame. This limits the delay to a maximum of one
1839 * second.
1840 */
1841 if (sc->sc_cdata.stge_tx_cnt != 0)
1842 stge_txeof(sc);
1843
1844 stge_watchdog(sc);
1845
1846 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
1847 }
1848
1849 /*
1850 * stge_stats_update:
1851 *
1852 * Read the TC9021 statistics counters.
1853 */
1854 static void
stge_stats_update(struct stge_softc * sc)1855 stge_stats_update(struct stge_softc *sc)
1856 {
1857 if_t ifp;
1858
1859 STGE_LOCK_ASSERT(sc);
1860
1861 ifp = sc->sc_ifp;
1862
1863 CSR_READ_4(sc,STGE_OctetRcvOk);
1864
1865 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk));
1866
1867 if_inc_counter(ifp, IFCOUNTER_IERRORS, CSR_READ_2(sc, STGE_FramesLostRxErrors));
1868
1869 CSR_READ_4(sc, STGE_OctetXmtdOk);
1870
1871 if_inc_counter(ifp, IFCOUNTER_OPACKETS, CSR_READ_4(sc, STGE_FramesXmtdOk));
1872
1873 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1874 CSR_READ_4(sc, STGE_LateCollisions) +
1875 CSR_READ_4(sc, STGE_MultiColFrames) +
1876 CSR_READ_4(sc, STGE_SingleColFrames));
1877
1878 if_inc_counter(ifp, IFCOUNTER_OERRORS,
1879 CSR_READ_2(sc, STGE_FramesAbortXSColls) +
1880 CSR_READ_2(sc, STGE_FramesWEXDeferal));
1881 }
1882
1883 /*
1884 * stge_reset:
1885 *
1886 * Perform a soft reset on the TC9021.
1887 */
1888 static void
stge_reset(struct stge_softc * sc,uint32_t how)1889 stge_reset(struct stge_softc *sc, uint32_t how)
1890 {
1891 uint32_t ac;
1892 uint8_t v;
1893 int i, dv;
1894
1895 STGE_LOCK_ASSERT(sc);
1896
1897 dv = 5000;
1898 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1899 switch (how) {
1900 case STGE_RESET_TX:
1901 ac |= AC_TxReset | AC_FIFO;
1902 dv = 100;
1903 break;
1904 case STGE_RESET_RX:
1905 ac |= AC_RxReset | AC_FIFO;
1906 dv = 100;
1907 break;
1908 case STGE_RESET_FULL:
1909 default:
1910 /*
1911 * Only assert RstOut if we're fiber. We need GMII clocks
1912 * to be present in order for the reset to complete on fiber
1913 * cards.
1914 */
1915 ac |= AC_GlobalReset | AC_RxReset | AC_TxReset |
1916 AC_DMA | AC_FIFO | AC_Network | AC_Host | AC_AutoInit |
1917 (sc->sc_usefiber ? AC_RstOut : 0);
1918 break;
1919 }
1920
1921 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1922
1923 /* Account for reset problem at 10Mbps. */
1924 DELAY(dv);
1925
1926 for (i = 0; i < STGE_TIMEOUT; i++) {
1927 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0)
1928 break;
1929 DELAY(dv);
1930 }
1931
1932 if (i == STGE_TIMEOUT)
1933 device_printf(sc->sc_dev, "reset failed to complete\n");
1934
1935 /* Set LED, from Linux IPG driver. */
1936 ac = CSR_READ_4(sc, STGE_AsicCtrl);
1937 ac &= ~(AC_LEDMode | AC_LEDSpeed | AC_LEDModeBit1);
1938 if ((sc->sc_led & 0x01) != 0)
1939 ac |= AC_LEDMode;
1940 if ((sc->sc_led & 0x03) != 0)
1941 ac |= AC_LEDModeBit1;
1942 if ((sc->sc_led & 0x08) != 0)
1943 ac |= AC_LEDSpeed;
1944 CSR_WRITE_4(sc, STGE_AsicCtrl, ac);
1945
1946 /* Set PHY, from Linux IPG driver */
1947 v = CSR_READ_1(sc, STGE_PhySet);
1948 v &= ~(PS_MemLenb9b | PS_MemLen | PS_NonCompdet);
1949 v |= ((sc->sc_led & 0x70) >> 4);
1950 CSR_WRITE_1(sc, STGE_PhySet, v);
1951 }
1952
1953 /*
1954 * stge_init: [ ifnet interface function ]
1955 *
1956 * Initialize the interface.
1957 */
1958 static void
stge_init(void * xsc)1959 stge_init(void *xsc)
1960 {
1961 struct stge_softc *sc;
1962
1963 sc = (struct stge_softc *)xsc;
1964 STGE_LOCK(sc);
1965 stge_init_locked(sc);
1966 STGE_UNLOCK(sc);
1967 }
1968
1969 static void
stge_init_locked(struct stge_softc * sc)1970 stge_init_locked(struct stge_softc *sc)
1971 {
1972 if_t ifp;
1973 struct mii_data *mii;
1974 uint16_t eaddr[3];
1975 uint32_t v;
1976 int error;
1977
1978 STGE_LOCK_ASSERT(sc);
1979
1980 ifp = sc->sc_ifp;
1981 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0)
1982 return;
1983 mii = device_get_softc(sc->sc_miibus);
1984
1985 /*
1986 * Cancel any pending I/O.
1987 */
1988 stge_stop(sc);
1989
1990 /*
1991 * Reset the chip to a known state.
1992 */
1993 stge_reset(sc, STGE_RESET_FULL);
1994
1995 /* Init descriptors. */
1996 error = stge_init_rx_ring(sc);
1997 if (error != 0) {
1998 device_printf(sc->sc_dev,
1999 "initialization failed: no memory for rx buffers\n");
2000 stge_stop(sc);
2001 goto out;
2002 }
2003 stge_init_tx_ring(sc);
2004
2005 /* Set the station address. */
2006 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN);
2007 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2008 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2009 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2010
2011 /*
2012 * Set the statistics masks. Disable all the RMON stats,
2013 * and disable selected stats in the non-RMON stats registers.
2014 */
2015 CSR_WRITE_4(sc, STGE_RMONStatisticsMask, 0xffffffff);
2016 CSR_WRITE_4(sc, STGE_StatisticsMask,
2017 (1U << 1) | (1U << 2) | (1U << 3) | (1U << 4) | (1U << 5) |
2018 (1U << 6) | (1U << 7) | (1U << 8) | (1U << 9) | (1U << 10) |
2019 (1U << 13) | (1U << 14) | (1U << 15) | (1U << 19) | (1U << 20) |
2020 (1U << 21));
2021
2022 /* Set up the receive filter. */
2023 stge_set_filter(sc);
2024 /* Program multicast filter. */
2025 stge_set_multi(sc);
2026
2027 /*
2028 * Give the transmit and receive ring to the chip.
2029 */
2030 CSR_WRITE_4(sc, STGE_TFDListPtrHi,
2031 STGE_ADDR_HI(STGE_TX_RING_ADDR(sc, 0)));
2032 CSR_WRITE_4(sc, STGE_TFDListPtrLo,
2033 STGE_ADDR_LO(STGE_TX_RING_ADDR(sc, 0)));
2034
2035 CSR_WRITE_4(sc, STGE_RFDListPtrHi,
2036 STGE_ADDR_HI(STGE_RX_RING_ADDR(sc, 0)));
2037 CSR_WRITE_4(sc, STGE_RFDListPtrLo,
2038 STGE_ADDR_LO(STGE_RX_RING_ADDR(sc, 0)));
2039
2040 /*
2041 * Initialize the Tx auto-poll period. It's OK to make this number
2042 * large (255 is the max, but we use 127) -- we explicitly kick the
2043 * transmit engine when there's actually a packet.
2044 */
2045 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2046
2047 /* ..and the Rx auto-poll period. */
2048 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2049
2050 /* Initialize the Tx start threshold. */
2051 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2052
2053 /* Rx DMA thresholds, from Linux */
2054 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30);
2055 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30);
2056
2057 /* Rx early threhold, from Linux */
2058 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2059
2060 /* Tx DMA thresholds, from Linux */
2061 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30);
2062 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04);
2063
2064 /*
2065 * Initialize the Rx DMA interrupt control register. We
2066 * request an interrupt after every incoming packet, but
2067 * defer it for sc_rxint_dmawait us. When the number of
2068 * interrupts pending reaches STGE_RXINT_NFRAME, we stop
2069 * deferring the interrupt, and signal it immediately.
2070 */
2071 CSR_WRITE_4(sc, STGE_RxDMAIntCtrl,
2072 RDIC_RxFrameCount(sc->sc_rxint_nframe) |
2073 RDIC_RxDMAWaitTime(STGE_RXINT_USECS2TICK(sc->sc_rxint_dmawait)));
2074
2075 /*
2076 * Initialize the interrupt mask.
2077 */
2078 sc->sc_IntEnable = IS_HostError | IS_TxComplete |
2079 IS_TxDMAComplete | IS_RxDMAComplete | IS_RFDListEnd;
2080 #ifdef DEVICE_POLLING
2081 /* Disable interrupts if we are polling. */
2082 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0)
2083 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2084 else
2085 #endif
2086 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2087
2088 /*
2089 * Configure the DMA engine.
2090 * XXX Should auto-tune TxBurstLimit.
2091 */
2092 CSR_WRITE_4(sc, STGE_DMACtrl, sc->sc_DMACtrl | DMAC_TxBurstLimit(3));
2093
2094 /*
2095 * Send a PAUSE frame when we reach 29,696 bytes in the Rx
2096 * FIFO, and send an un-PAUSE frame when we reach 3056 bytes
2097 * in the Rx FIFO.
2098 */
2099 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2100 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2101
2102 /*
2103 * Set the maximum frame size.
2104 */
2105 sc->sc_if_framesize = if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN;
2106 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2107
2108 /*
2109 * Initialize MacCtrl -- do it before setting the media,
2110 * as setting the media will actually program the register.
2111 *
2112 * Note: We have to poke the IFS value before poking
2113 * anything else.
2114 */
2115 /* Tx/Rx MAC should be disabled before programming IFS.*/
2116 CSR_WRITE_4(sc, STGE_MACCtrl, MC_IFSSelect(MC_IFS96bit));
2117
2118 stge_vlan_setup(sc);
2119
2120 if (sc->sc_rev >= 6) { /* >= B.2 */
2121 /* Multi-frag frame bug work-around. */
2122 CSR_WRITE_2(sc, STGE_DebugCtrl,
2123 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0200);
2124
2125 /* Tx Poll Now bug work-around. */
2126 CSR_WRITE_2(sc, STGE_DebugCtrl,
2127 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0010);
2128 /* Tx Poll Now bug work-around. */
2129 CSR_WRITE_2(sc, STGE_DebugCtrl,
2130 CSR_READ_2(sc, STGE_DebugCtrl) | 0x0020);
2131 }
2132
2133 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2134 v |= MC_StatisticsEnable | MC_TxEnable | MC_RxEnable;
2135 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2136 /*
2137 * It seems that transmitting frames without checking the state of
2138 * Rx/Tx MAC wedge the hardware.
2139 */
2140 stge_start_tx(sc);
2141 stge_start_rx(sc);
2142
2143 sc->sc_link = 0;
2144 /*
2145 * Set the current media.
2146 */
2147 mii_mediachg(mii);
2148
2149 /*
2150 * Start the one second MII clock.
2151 */
2152 callout_reset(&sc->sc_tick_ch, hz, stge_tick, sc);
2153
2154 /*
2155 * ...all done!
2156 */
2157 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
2158 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
2159
2160 out:
2161 if (error != 0)
2162 device_printf(sc->sc_dev, "interface not running\n");
2163 }
2164
2165 static void
stge_vlan_setup(struct stge_softc * sc)2166 stge_vlan_setup(struct stge_softc *sc)
2167 {
2168 if_t ifp;
2169 uint32_t v;
2170
2171 ifp = sc->sc_ifp;
2172 /*
2173 * The NIC always copy a VLAN tag regardless of STGE_MACCtrl
2174 * MC_AutoVLANuntagging bit.
2175 * MC_AutoVLANtagging bit selects which VLAN source to use
2176 * between STGE_VLANTag and TFC. However TFC TFD_VLANTagInsert
2177 * bit has priority over MC_AutoVLANtagging bit. So we always
2178 * use TFC instead of STGE_VLANTag register.
2179 */
2180 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2181 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0)
2182 v |= MC_AutoVLANuntagging;
2183 else
2184 v &= ~MC_AutoVLANuntagging;
2185 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2186 }
2187
2188 /*
2189 * Stop transmission on the interface.
2190 */
2191 static void
stge_stop(struct stge_softc * sc)2192 stge_stop(struct stge_softc *sc)
2193 {
2194 if_t ifp;
2195 struct stge_txdesc *txd;
2196 struct stge_rxdesc *rxd;
2197 uint32_t v;
2198 int i;
2199
2200 STGE_LOCK_ASSERT(sc);
2201 /*
2202 * Stop the one second clock.
2203 */
2204 callout_stop(&sc->sc_tick_ch);
2205 sc->sc_watchdog_timer = 0;
2206
2207 /*
2208 * Disable interrupts.
2209 */
2210 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2211
2212 /*
2213 * Stop receiver, transmitter, and stats update.
2214 */
2215 stge_stop_rx(sc);
2216 stge_stop_tx(sc);
2217 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2218 v |= MC_StatisticsDisable;
2219 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2220
2221 /*
2222 * Stop the transmit and receive DMA.
2223 */
2224 stge_dma_wait(sc);
2225 CSR_WRITE_4(sc, STGE_TFDListPtrHi, 0);
2226 CSR_WRITE_4(sc, STGE_TFDListPtrLo, 0);
2227 CSR_WRITE_4(sc, STGE_RFDListPtrHi, 0);
2228 CSR_WRITE_4(sc, STGE_RFDListPtrLo, 0);
2229
2230 /*
2231 * Free RX and TX mbufs still in the queues.
2232 */
2233 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2234 rxd = &sc->sc_cdata.stge_rxdesc[i];
2235 if (rxd->rx_m != NULL) {
2236 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag,
2237 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2238 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag,
2239 rxd->rx_dmamap);
2240 m_freem(rxd->rx_m);
2241 rxd->rx_m = NULL;
2242 }
2243 }
2244 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2245 txd = &sc->sc_cdata.stge_txdesc[i];
2246 if (txd->tx_m != NULL) {
2247 bus_dmamap_sync(sc->sc_cdata.stge_tx_tag,
2248 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2249 bus_dmamap_unload(sc->sc_cdata.stge_tx_tag,
2250 txd->tx_dmamap);
2251 m_freem(txd->tx_m);
2252 txd->tx_m = NULL;
2253 }
2254 }
2255
2256 /*
2257 * Mark the interface down and cancel the watchdog timer.
2258 */
2259 ifp = sc->sc_ifp;
2260 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
2261 sc->sc_link = 0;
2262 }
2263
2264 static void
stge_start_tx(struct stge_softc * sc)2265 stge_start_tx(struct stge_softc *sc)
2266 {
2267 uint32_t v;
2268 int i;
2269
2270 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2271 if ((v & MC_TxEnabled) != 0)
2272 return;
2273 v |= MC_TxEnable;
2274 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2275 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127);
2276 for (i = STGE_TIMEOUT; i > 0; i--) {
2277 DELAY(10);
2278 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2279 if ((v & MC_TxEnabled) != 0)
2280 break;
2281 }
2282 if (i == 0)
2283 device_printf(sc->sc_dev, "Starting Tx MAC timed out\n");
2284 }
2285
2286 static void
stge_start_rx(struct stge_softc * sc)2287 stge_start_rx(struct stge_softc *sc)
2288 {
2289 uint32_t v;
2290 int i;
2291
2292 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2293 if ((v & MC_RxEnabled) != 0)
2294 return;
2295 v |= MC_RxEnable;
2296 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2297 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1);
2298 for (i = STGE_TIMEOUT; i > 0; i--) {
2299 DELAY(10);
2300 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2301 if ((v & MC_RxEnabled) != 0)
2302 break;
2303 }
2304 if (i == 0)
2305 device_printf(sc->sc_dev, "Starting Rx MAC timed out\n");
2306 }
2307
2308 static void
stge_stop_tx(struct stge_softc * sc)2309 stge_stop_tx(struct stge_softc *sc)
2310 {
2311 uint32_t v;
2312 int i;
2313
2314 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2315 if ((v & MC_TxEnabled) == 0)
2316 return;
2317 v |= MC_TxDisable;
2318 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2319 for (i = STGE_TIMEOUT; i > 0; i--) {
2320 DELAY(10);
2321 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2322 if ((v & MC_TxEnabled) == 0)
2323 break;
2324 }
2325 if (i == 0)
2326 device_printf(sc->sc_dev, "Stopping Tx MAC timed out\n");
2327 }
2328
2329 static void
stge_stop_rx(struct stge_softc * sc)2330 stge_stop_rx(struct stge_softc *sc)
2331 {
2332 uint32_t v;
2333 int i;
2334
2335 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2336 if ((v & MC_RxEnabled) == 0)
2337 return;
2338 v |= MC_RxDisable;
2339 CSR_WRITE_4(sc, STGE_MACCtrl, v);
2340 for (i = STGE_TIMEOUT; i > 0; i--) {
2341 DELAY(10);
2342 v = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK;
2343 if ((v & MC_RxEnabled) == 0)
2344 break;
2345 }
2346 if (i == 0)
2347 device_printf(sc->sc_dev, "Stopping Rx MAC timed out\n");
2348 }
2349
2350 static void
stge_init_tx_ring(struct stge_softc * sc)2351 stge_init_tx_ring(struct stge_softc *sc)
2352 {
2353 struct stge_ring_data *rd;
2354 struct stge_txdesc *txd;
2355 bus_addr_t addr;
2356 int i;
2357
2358 STAILQ_INIT(&sc->sc_cdata.stge_txfreeq);
2359 STAILQ_INIT(&sc->sc_cdata.stge_txbusyq);
2360
2361 sc->sc_cdata.stge_tx_prod = 0;
2362 sc->sc_cdata.stge_tx_cons = 0;
2363 sc->sc_cdata.stge_tx_cnt = 0;
2364
2365 rd = &sc->sc_rdata;
2366 bzero(rd->stge_tx_ring, STGE_TX_RING_SZ);
2367 for (i = 0; i < STGE_TX_RING_CNT; i++) {
2368 if (i == (STGE_TX_RING_CNT - 1))
2369 addr = STGE_TX_RING_ADDR(sc, 0);
2370 else
2371 addr = STGE_TX_RING_ADDR(sc, i + 1);
2372 rd->stge_tx_ring[i].tfd_next = htole64(addr);
2373 rd->stge_tx_ring[i].tfd_control = htole64(TFD_TFDDone);
2374 txd = &sc->sc_cdata.stge_txdesc[i];
2375 STAILQ_INSERT_TAIL(&sc->sc_cdata.stge_txfreeq, txd, tx_q);
2376 }
2377
2378 bus_dmamap_sync(sc->sc_cdata.stge_tx_ring_tag,
2379 sc->sc_cdata.stge_tx_ring_map,
2380 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2381
2382 }
2383
2384 static int
stge_init_rx_ring(struct stge_softc * sc)2385 stge_init_rx_ring(struct stge_softc *sc)
2386 {
2387 struct stge_ring_data *rd;
2388 bus_addr_t addr;
2389 int i;
2390
2391 sc->sc_cdata.stge_rx_cons = 0;
2392 STGE_RXCHAIN_RESET(sc);
2393
2394 rd = &sc->sc_rdata;
2395 bzero(rd->stge_rx_ring, STGE_RX_RING_SZ);
2396 for (i = 0; i < STGE_RX_RING_CNT; i++) {
2397 if (stge_newbuf(sc, i) != 0)
2398 return (ENOBUFS);
2399 if (i == (STGE_RX_RING_CNT - 1))
2400 addr = STGE_RX_RING_ADDR(sc, 0);
2401 else
2402 addr = STGE_RX_RING_ADDR(sc, i + 1);
2403 rd->stge_rx_ring[i].rfd_next = htole64(addr);
2404 rd->stge_rx_ring[i].rfd_status = 0;
2405 }
2406
2407 bus_dmamap_sync(sc->sc_cdata.stge_rx_ring_tag,
2408 sc->sc_cdata.stge_rx_ring_map,
2409 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2410
2411 return (0);
2412 }
2413
2414 /*
2415 * stge_newbuf:
2416 *
2417 * Add a receive buffer to the indicated descriptor.
2418 */
2419 static int
stge_newbuf(struct stge_softc * sc,int idx)2420 stge_newbuf(struct stge_softc *sc, int idx)
2421 {
2422 struct stge_rxdesc *rxd;
2423 struct stge_rfd *rfd;
2424 struct mbuf *m;
2425 bus_dma_segment_t segs[1];
2426 bus_dmamap_t map;
2427 int nsegs;
2428
2429 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2430 if (m == NULL)
2431 return (ENOBUFS);
2432 m->m_len = m->m_pkthdr.len = MCLBYTES;
2433 /*
2434 * The hardware requires 4bytes aligned DMA address when JUMBO
2435 * frame is used.
2436 */
2437 if (sc->sc_if_framesize <= (MCLBYTES - ETHER_ALIGN))
2438 m_adj(m, ETHER_ALIGN);
2439
2440 if (bus_dmamap_load_mbuf_sg(sc->sc_cdata.stge_rx_tag,
2441 sc->sc_cdata.stge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
2442 m_freem(m);
2443 return (ENOBUFS);
2444 }
2445 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
2446
2447 rxd = &sc->sc_cdata.stge_rxdesc[idx];
2448 if (rxd->rx_m != NULL) {
2449 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2450 BUS_DMASYNC_POSTREAD);
2451 bus_dmamap_unload(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap);
2452 }
2453 map = rxd->rx_dmamap;
2454 rxd->rx_dmamap = sc->sc_cdata.stge_rx_sparemap;
2455 sc->sc_cdata.stge_rx_sparemap = map;
2456 bus_dmamap_sync(sc->sc_cdata.stge_rx_tag, rxd->rx_dmamap,
2457 BUS_DMASYNC_PREREAD);
2458 rxd->rx_m = m;
2459
2460 rfd = &sc->sc_rdata.stge_rx_ring[idx];
2461 rfd->rfd_frag.frag_word0 =
2462 htole64(FRAG_ADDR(segs[0].ds_addr) | FRAG_LEN(segs[0].ds_len));
2463 rfd->rfd_status = 0;
2464
2465 return (0);
2466 }
2467
2468 /*
2469 * stge_set_filter:
2470 *
2471 * Set up the receive filter.
2472 */
2473 static void
stge_set_filter(struct stge_softc * sc)2474 stge_set_filter(struct stge_softc *sc)
2475 {
2476 if_t ifp;
2477 uint16_t mode;
2478
2479 STGE_LOCK_ASSERT(sc);
2480
2481 ifp = sc->sc_ifp;
2482
2483 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2484 mode |= RM_ReceiveUnicast;
2485 if ((if_getflags(ifp) & IFF_BROADCAST) != 0)
2486 mode |= RM_ReceiveBroadcast;
2487 else
2488 mode &= ~RM_ReceiveBroadcast;
2489 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
2490 mode |= RM_ReceiveAllFrames;
2491 else
2492 mode &= ~RM_ReceiveAllFrames;
2493
2494 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2495 }
2496
2497 static u_int
stge_hash_maddr(void * arg,struct sockaddr_dl * sdl,u_int cnt)2498 stge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2499 {
2500 uint32_t crc, *mchash = arg;
2501
2502 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
2503 /* Just want the 6 least significant bits. */
2504 crc &= 0x3f;
2505 /* Set the corresponding bit in the hash table. */
2506 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2507
2508 return (1);
2509 }
2510
2511 static void
stge_set_multi(struct stge_softc * sc)2512 stge_set_multi(struct stge_softc *sc)
2513 {
2514 if_t ifp;
2515 uint32_t mchash[2];
2516 uint16_t mode;
2517 int count;
2518
2519 STGE_LOCK_ASSERT(sc);
2520
2521 ifp = sc->sc_ifp;
2522
2523 mode = CSR_READ_2(sc, STGE_ReceiveMode);
2524 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2525 if ((if_getflags(ifp) & IFF_PROMISC) != 0)
2526 mode |= RM_ReceiveAllFrames;
2527 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0)
2528 mode |= RM_ReceiveMulticast;
2529 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2530 return;
2531 }
2532
2533 /* clear existing filters. */
2534 CSR_WRITE_4(sc, STGE_HashTable0, 0);
2535 CSR_WRITE_4(sc, STGE_HashTable1, 0);
2536
2537 /*
2538 * Set up the multicast address filter by passing all multicast
2539 * addresses through a CRC generator, and then using the low-order
2540 * 6 bits as an index into the 64 bit multicast hash table. The
2541 * high order bits select the register, while the rest of the bits
2542 * select the bit within the register.
2543 */
2544 bzero(mchash, sizeof(mchash));
2545 count = if_foreach_llmaddr(ifp, stge_hash_maddr, mchash);
2546
2547 mode &= ~(RM_ReceiveMulticast | RM_ReceiveAllFrames);
2548 if (count > 0)
2549 mode |= RM_ReceiveMulticastHash;
2550 else
2551 mode &= ~RM_ReceiveMulticastHash;
2552
2553 CSR_WRITE_4(sc, STGE_HashTable0, mchash[0]);
2554 CSR_WRITE_4(sc, STGE_HashTable1, mchash[1]);
2555 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2556 }
2557
2558 static int
sysctl_int_range(SYSCTL_HANDLER_ARGS,int low,int high)2559 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2560 {
2561 int error, value;
2562
2563 if (!arg1)
2564 return (EINVAL);
2565 value = *(int *)arg1;
2566 error = sysctl_handle_int(oidp, &value, 0, req);
2567 if (error || !req->newptr)
2568 return (error);
2569 if (value < low || value > high)
2570 return (EINVAL);
2571 *(int *)arg1 = value;
2572
2573 return (0);
2574 }
2575
2576 static int
sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)2577 sysctl_hw_stge_rxint_nframe(SYSCTL_HANDLER_ARGS)
2578 {
2579 return (sysctl_int_range(oidp, arg1, arg2, req,
2580 STGE_RXINT_NFRAME_MIN, STGE_RXINT_NFRAME_MAX));
2581 }
2582
2583 static int
sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)2584 sysctl_hw_stge_rxint_dmawait(SYSCTL_HANDLER_ARGS)
2585 {
2586 return (sysctl_int_range(oidp, arg1, arg2, req,
2587 STGE_RXINT_DMAWAIT_MIN, STGE_RXINT_DMAWAIT_MAX));
2588 }
2589