1 /* $OpenBSD: if_urtwn.c,v 1.16 2011/02/10 17:26:40 jakemsr Exp $ */
2
3 /*-
4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2014 Kevin Lo <kevlo@FreeBSD.org>
6 * Copyright (c) 2015-2016 Andriy Voskoboinyk <avos@FreeBSD.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 #include <sys/cdefs.h>
22 #include "opt_wlan.h"
23
24 #include <sys/param.h>
25 #include <sys/lock.h>
26 #include <sys/mutex.h>
27 #include <sys/mbuf.h>
28 #include <sys/kernel.h>
29 #include <sys/socket.h>
30 #include <sys/systm.h>
31 #include <sys/malloc.h>
32 #include <sys/queue.h>
33 #include <sys/taskqueue.h>
34 #include <sys/bus.h>
35 #include <sys/endian.h>
36 #include <sys/linker.h>
37
38 #include <net/if.h>
39 #include <net/ethernet.h>
40 #include <net/if_media.h>
41
42 #include <net80211/ieee80211_var.h>
43 #include <net80211/ieee80211_radiotap.h>
44
45 #include <dev/rtwn/if_rtwnreg.h>
46 #include <dev/rtwn/if_rtwnvar.h>
47
48 #include <dev/rtwn/rtl8192c/r92c.h>
49 #include <dev/rtwn/rtl8192c/r92c_var.h>
50
51 #include <dev/rtwn/rtl8188e/usb/r88eu.h>
52 #include <dev/rtwn/rtl8188e/usb/r88eu_reg.h>
53
54 void
r88eu_init_bb(struct rtwn_softc * sc)55 r88eu_init_bb(struct rtwn_softc *sc)
56 {
57
58 /* Enable BB and RF. */
59 rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
60 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
61 R92C_SYS_FUNC_EN_DIO_RF);
62
63 rtwn_write_1(sc, R92C_RF_CTRL,
64 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
65 rtwn_write_1(sc, R92C_SYS_FUNC_EN,
66 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
67 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
68
69 r88e_init_bb_common(sc);
70 }
71
72 int
r88eu_power_on(struct rtwn_softc * sc)73 r88eu_power_on(struct rtwn_softc *sc)
74 {
75 #define RTWN_CHK(res) do { \
76 if (res != 0) \
77 return (EIO); \
78 } while(0)
79 int ntries;
80
81 /* Wait for power ready bit. */
82 for (ntries = 0; ntries < 5000; ntries++) {
83 if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
84 break;
85 rtwn_delay(sc, 10);
86 }
87 if (ntries == 5000) {
88 device_printf(sc->sc_dev,
89 "timeout waiting for chip power up\n");
90 return (ETIMEDOUT);
91 }
92
93 /* Reset BB. */
94 RTWN_CHK(rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
95 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0));
96
97 RTWN_CHK(rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80));
98
99 /* Disable HWPDN. */
100 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
101 R92C_APS_FSMCO_APDM_HPDN, 0, 1));
102
103 /* Disable WL suspend. */
104 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
105 R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1));
106
107 RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
108 0, R92C_APS_FSMCO_APFM_ONMAC, 1));
109 for (ntries = 0; ntries < 5000; ntries++) {
110 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
111 R92C_APS_FSMCO_APFM_ONMAC))
112 break;
113 rtwn_delay(sc, 10);
114 }
115 if (ntries == 5000)
116 return (ETIMEDOUT);
117
118 /* Enable LDO normal mode. */
119 RTWN_CHK(rtwn_setbits_1(sc, R92C_LPLDO_CTRL,
120 R92C_LPLDO_CTRL_SLEEP, 0));
121
122 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
123 RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
124 RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
125 R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
126 R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
127 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
128 ((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
129 R92C_CR_CALTMR_EN));
130
131 return (0);
132 #undef RTWN_CHK
133 }
134
135 void
r88eu_power_off(struct rtwn_softc * sc)136 r88eu_power_off(struct rtwn_softc *sc)
137 {
138 uint8_t reg;
139 int error, ntries;
140
141 /* Disable any kind of TX reports. */
142 error = rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
143 R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
144 if (error == ENXIO) /* hardware gone */
145 return;
146
147 /* Stop Rx. */
148 rtwn_write_1(sc, R92C_CR, 0);
149
150 /* Move card to Low Power State. */
151 /* Block all Tx queues. */
152 rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
153
154 for (ntries = 0; ntries < 10; ntries++) {
155 /* Should be zero if no packet is transmitting. */
156 if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
157 break;
158
159 rtwn_delay(sc, 5000);
160 }
161 if (ntries == 10) {
162 device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
163 __func__);
164 return;
165 }
166
167 /* CCK and OFDM are disabled, and clock are gated. */
168 rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
169
170 rtwn_delay(sc, 1);
171
172 /* Reset MAC TRX */
173 rtwn_write_1(sc, R92C_CR,
174 R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
175 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
176 R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
177
178 /* check if removed later */
179 rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
180
181 /* Respond TxOK to scheduler */
182 rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
183
184 /* If firmware in ram code, do reset. */
185 #ifndef RTWN_WITHOUT_UCODE
186 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
187 r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
188 #endif
189
190 /* Reset MCU ready status. */
191 rtwn_write_1(sc, R92C_MCUFWDL, 0);
192
193 /* Disable 32k. */
194 rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
195
196 /* Move card to Disabled state. */
197 /* Turn off RF. */
198 rtwn_write_1(sc, R92C_RF_CTRL, 0);
199
200 /* LDO Sleep mode. */
201 rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
202
203 /* Turn off MAC by HW state machine */
204 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
205 R92C_APS_FSMCO_APFM_OFF, 1);
206
207 for (ntries = 0; ntries < 10; ntries++) {
208 /* Wait until it will be disabled. */
209 if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
210 R92C_APS_FSMCO_APFM_OFF) == 0)
211 break;
212
213 rtwn_delay(sc, 5000);
214 }
215 if (ntries == 10) {
216 device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
217 __func__);
218 return;
219 }
220
221 /* schmit trigger */
222 rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
223
224 /* Enable WL suspend. */
225 rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
226 R92C_APS_FSMCO_AFSM_PCIE, R92C_APS_FSMCO_AFSM_HSUS, 1);
227
228 /* Enable bandgap mbias in suspend. */
229 rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
230
231 /* Clear SIC_EN register. */
232 rtwn_setbits_1(sc, R92C_GPIO_MUXCFG + 1, 0x10, 0);
233
234 /* Set USB suspend enable local register */
235 rtwn_setbits_1(sc, R92C_USB_SUSPEND, 0, 0x10);
236
237 /* Reset MCU IO Wrapper. */
238 reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
239 rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
240 rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
241
242 /* marked as 'For Power Consumption' code. */
243 rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
244 rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
245
246 rtwn_write_1(sc, R92C_GPIO_IO_SEL,
247 rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
248 rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
249
250 /* Set LNA, TRSW, EX_PA Pin to output mode. */
251 rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
252 }
253
254 void
r88eu_init_intr(struct rtwn_softc * sc)255 r88eu_init_intr(struct rtwn_softc *sc)
256 {
257 /* TODO: adjust */
258 rtwn_write_4(sc, R88E_HISR, 0xffffffff);
259 rtwn_write_4(sc, R88E_HIMR, R88E_HIMR_CPWM | R88E_HIMR_CPWM2 |
260 R88E_HIMR_TBDER | R88E_HIMR_PSTIMEOUT);
261 rtwn_write_4(sc, R88E_HIMRE, R88E_HIMRE_RXFOVW |
262 R88E_HIMRE_TXFOVW | R88E_HIMRE_RXERR | R88E_HIMRE_TXERR);
263 rtwn_setbits_1(sc, R92C_USB_SPECIAL_OPTION, 0,
264 R92C_USB_SPECIAL_OPTION_INT_BULK_SEL);
265 }
266
267 void
r88eu_init_rx_agg(struct rtwn_softc * sc)268 r88eu_init_rx_agg(struct rtwn_softc *sc)
269 {
270 /* XXX merge? */
271 rtwn_setbits_1(sc, R92C_TRXDMA_CTRL, 0,
272 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
273 /* XXX dehardcode */
274 rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
275 rtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH + 1, 4);
276 }
277
278 void
r88eu_post_init(struct rtwn_softc * sc)279 r88eu_post_init(struct rtwn_softc *sc)
280 {
281
282 /* Enable per-packet TX report (RPT1) */
283 rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
284
285 #ifndef RTWN_WITHOUT_UCODE
286 /* Enable timer report (RPT2) if requested */
287 if (sc->macid_rpt2_max_num > 0) {
288 rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0,
289 R88E_TX_RPT2_ENA);
290
291 /* Configure how many TX RPT2 entries to populate */
292 rtwn_write_1(sc, R88E_TX_RPT_MACID_MAX,
293 sc->macid_rpt2_max_num);
294 /* Enable periodic TX report; 32uS units */
295 rtwn_write_2(sc, R88E_TX_RPT_TIME, 0xcdf0);
296 }
297 #endif
298 /* Disable Tx if MACID is not associated. */
299 rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
300 rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
301 r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
302
303 /* Perform LO and IQ calibrations. */
304 r88e_iq_calib(sc);
305 /* Perform LC calibration. */
306 r92c_lc_calib(sc);
307
308 rtwn_write_1(sc, R92C_USB_HRPWM, 0);
309
310 if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
311 /* No support (yet?) for f/w rate adaptation. */
312 sc->sc_ratectl = RTWN_RATECTL_NET80211;
313 } else
314 sc->sc_ratectl = sc->sc_ratectl_sysctl;
315 }
316