1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2006 Marcel Moolenaar
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 /*
31 * PCI "universal" communications card driver configuration data (used to
32 * match/attach the cards).
33 */
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/kernel.h>
38 #include <sys/bus.h>
39 #include <sys/sysctl.h>
40
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44
45 #include <dev/ic/ns16550.h>
46
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49
50 #include <dev/puc/puc_bus.h>
51 #include <dev/puc/puc_cfg.h>
52 #include <dev/puc/puc_bfe.h>
53
54 static puc_config_f puc_config_advantech;
55 static puc_config_f puc_config_amc;
56 static puc_config_f puc_config_diva;
57 static puc_config_f puc_config_exar;
58 static puc_config_f puc_config_exar_pcie;
59 static puc_config_f puc_config_icbook;
60 static puc_config_f puc_config_moxa;
61 static puc_config_f puc_config_oxford_pci954;
62 static puc_config_f puc_config_oxford_pcie;
63 static puc_config_f puc_config_quatech;
64 static puc_config_f puc_config_syba;
65 static puc_config_f puc_config_siig;
66 static puc_config_f puc_config_sunix;
67 static puc_config_f puc_config_systembase;
68 static puc_config_f puc_config_timedia;
69 static puc_config_f puc_config_titan;
70
71 const struct puc_cfg puc_pci_devices[] = {
72 { 0x0009, 0x7168, 0xffff, 0,
73 "Sunix SUN1889",
74 DEFAULT_RCLK * 8,
75 PUC_PORT_2S, 0x10, 0, 8,
76 },
77
78 { 0x103c, 0x1048, 0x103c, 0x1049,
79 "HP Diva Serial [GSP] Multiport UART - Tosca Console",
80 DEFAULT_RCLK,
81 PUC_PORT_3S, 0x10, 0, -1,
82 .config_function = puc_config_diva
83 },
84
85 { 0x103c, 0x1048, 0x103c, 0x104a,
86 "HP Diva Serial [GSP] Multiport UART - Tosca Secondary",
87 DEFAULT_RCLK,
88 PUC_PORT_2S, 0x10, 0, -1,
89 .config_function = puc_config_diva
90 },
91
92 { 0x103c, 0x1048, 0x103c, 0x104b,
93 "HP Diva Serial [GSP] Multiport UART - Maestro SP2",
94 DEFAULT_RCLK,
95 PUC_PORT_4S, 0x10, 0, -1,
96 .config_function = puc_config_diva
97 },
98
99 { 0x103c, 0x1048, 0x103c, 0x1223,
100 "HP Diva Serial [GSP] Multiport UART - Superdome Console",
101 DEFAULT_RCLK,
102 PUC_PORT_3S, 0x10, 0, -1,
103 .config_function = puc_config_diva
104 },
105
106 { 0x103c, 0x1048, 0x103c, 0x1226,
107 "HP Diva Serial [GSP] Multiport UART - Keystone SP2",
108 DEFAULT_RCLK,
109 PUC_PORT_3S, 0x10, 0, -1,
110 .config_function = puc_config_diva
111 },
112
113 { 0x103c, 0x1048, 0x103c, 0x1282,
114 "HP Diva Serial [GSP] Multiport UART - Everest SP2",
115 DEFAULT_RCLK,
116 PUC_PORT_3S, 0x10, 0, -1,
117 .config_function = puc_config_diva
118 },
119
120 { 0x10b5, 0x1076, 0x10b5, 0x1076,
121 "VScom PCI-800",
122 DEFAULT_RCLK * 8,
123 PUC_PORT_8S, 0x18, 0, 8,
124 },
125
126 { 0x10b5, 0x1077, 0x10b5, 0x1077,
127 "VScom PCI-400",
128 DEFAULT_RCLK * 8,
129 PUC_PORT_4S, 0x18, 0, 8,
130 },
131
132 { 0x10b5, 0x1103, 0x10b5, 0x1103,
133 "VScom PCI-200",
134 DEFAULT_RCLK * 8,
135 PUC_PORT_2S, 0x18, 4, 0,
136 },
137
138 /*
139 * Boca Research Turbo Serial 658 (8 serial port) card.
140 * Appears to be the same as Chase Research PLC PCI-FAST8
141 * and Perle PCI-FAST8 Multi-Port serial cards.
142 */
143 { 0x10b5, 0x9050, 0x12e0, 0x0021,
144 "Boca Research Turbo Serial 658",
145 DEFAULT_RCLK * 4,
146 PUC_PORT_8S, 0x18, 0, 8,
147 },
148
149 { 0x10b5, 0x9050, 0x12e0, 0x0031,
150 "Boca Research Turbo Serial 654",
151 DEFAULT_RCLK * 4,
152 PUC_PORT_4S, 0x18, 0, 8,
153 },
154
155 /*
156 * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with
157 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
158 * into the subsystem fields, and claims that it's a
159 * network/misc (0x02/0x80) device.
160 */
161 { 0x10b5, 0x9050, 0xd84d, 0x6808,
162 "Dolphin Peripherals 4035",
163 DEFAULT_RCLK,
164 PUC_PORT_2S, 0x18, 4, 0,
165 },
166
167 /*
168 * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with
169 * a seemingly-lame EEPROM setup that puts the Dolphin IDs
170 * into the subsystem fields, and claims that it's a
171 * network/misc (0x02/0x80) device.
172 */
173 { 0x10b5, 0x9050, 0xd84d, 0x6810,
174 "Dolphin Peripherals 4014",
175 0,
176 PUC_PORT_2P, 0x20, 4, 0,
177 },
178
179 { 0x10e8, 0x818e, 0xffff, 0,
180 "Applied Micro Circuits 8 Port UART",
181 DEFAULT_RCLK,
182 PUC_PORT_8S, 0x14, -1, -1,
183 .config_function = puc_config_amc
184 },
185
186 /*
187 * The following members of the Digi International Neo series are
188 * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV.
189 * Accordingly, the PCIe versions of these cards incorporate a PLX
190 * PCIe-PCI-bridge.
191 */
192
193 { 0x114f, 0x00b0, 0xffff, 0,
194 "Digi Neo PCI 4 Port",
195 DEFAULT_RCLK * 8,
196 PUC_PORT_4S, 0x10, 0, -1,
197 .config_function = puc_config_exar
198 },
199
200 { 0x114f, 0x00b1, 0xffff, 0,
201 "Digi Neo PCI 8 Port",
202 DEFAULT_RCLK * 8,
203 PUC_PORT_8S, 0x10, 0, -1,
204 .config_function = puc_config_exar
205 },
206
207 { 0x114f, 0x00f0, 0xffff, 0,
208 "Digi Neo PCIe 8 Port",
209 DEFAULT_RCLK * 8,
210 PUC_PORT_8S, 0x10, 0, -1,
211 .config_function = puc_config_exar
212 },
213
214 { 0x114f, 0x00f1, 0xffff, 0,
215 "Digi Neo PCIe 4 Port",
216 DEFAULT_RCLK * 8,
217 PUC_PORT_4S, 0x10, 0, -1,
218 .config_function = puc_config_exar
219 },
220
221 { 0x114f, 0x00f2, 0xffff, 0,
222 "Digi Neo PCIe 4 Port RJ45",
223 DEFAULT_RCLK * 8,
224 PUC_PORT_4S, 0x10, 0, -1,
225 .config_function = puc_config_exar
226 },
227
228 { 0x114f, 0x00f3, 0xffff, 0,
229 "Digi Neo PCIe 8 Port RJ45",
230 DEFAULT_RCLK * 8,
231 PUC_PORT_8S, 0x10, 0, -1,
232 .config_function = puc_config_exar
233 },
234
235 { 0x11fe, 0x8010, 0xffff, 0,
236 "Comtrol RocketPort 550/8 RJ11 part A",
237 DEFAULT_RCLK * 4,
238 PUC_PORT_4S, 0x10, 0, 8,
239 },
240
241 { 0x11fe, 0x8011, 0xffff, 0,
242 "Comtrol RocketPort 550/8 RJ11 part B",
243 DEFAULT_RCLK * 4,
244 PUC_PORT_4S, 0x10, 0, 8,
245 },
246
247 { 0x11fe, 0x8012, 0xffff, 0,
248 "Comtrol RocketPort 550/8 Octa part A",
249 DEFAULT_RCLK * 4,
250 PUC_PORT_4S, 0x10, 0, 8,
251 },
252
253 { 0x11fe, 0x8013, 0xffff, 0,
254 "Comtrol RocketPort 550/8 Octa part B",
255 DEFAULT_RCLK * 4,
256 PUC_PORT_4S, 0x10, 0, 8,
257 },
258
259 { 0x11fe, 0x8014, 0xffff, 0,
260 "Comtrol RocketPort 550/4 RJ45",
261 DEFAULT_RCLK * 4,
262 PUC_PORT_4S, 0x10, 0, 8,
263 },
264
265 { 0x11fe, 0x8015, 0xffff, 0,
266 "Comtrol RocketPort 550/Quad",
267 DEFAULT_RCLK * 4,
268 PUC_PORT_4S, 0x10, 0, 8,
269 },
270
271 { 0x11fe, 0x8016, 0xffff, 0,
272 "Comtrol RocketPort 550/16 part A",
273 DEFAULT_RCLK * 4,
274 PUC_PORT_4S, 0x10, 0, 8,
275 },
276
277 { 0x11fe, 0x8017, 0xffff, 0,
278 "Comtrol RocketPort 550/16 part B",
279 DEFAULT_RCLK * 4,
280 PUC_PORT_12S, 0x10, 0, 8,
281 },
282
283 { 0x11fe, 0x8018, 0xffff, 0,
284 "Comtrol RocketPort 550/8 part A",
285 DEFAULT_RCLK * 4,
286 PUC_PORT_4S, 0x10, 0, 8,
287 },
288
289 { 0x11fe, 0x8019, 0xffff, 0,
290 "Comtrol RocketPort 550/8 part B",
291 DEFAULT_RCLK * 4,
292 PUC_PORT_4S, 0x10, 0, 8,
293 },
294
295 /*
296 * IBM SurePOS 300 Series (481033H) serial ports
297 * Details can be found on the IBM RSS websites
298 */
299
300 { 0x1014, 0x0297, 0xffff, 0,
301 "IBM SurePOS 300 Series (481033H) serial ports",
302 DEFAULT_RCLK,
303 PUC_PORT_4S, 0x10, 4, 0
304 },
305
306 /*
307 * SIIG Boards.
308 *
309 * SIIG provides documentation for their boards at:
310 * <URL:http://www.siig.com/downloads.asp>
311 */
312
313 { 0x131f, 0x1010, 0xffff, 0,
314 "SIIG Cyber I/O PCI 16C550 (10x family)",
315 DEFAULT_RCLK,
316 PUC_PORT_1S1P, 0x18, 4, 0,
317 },
318
319 { 0x131f, 0x1011, 0xffff, 0,
320 "SIIG Cyber I/O PCI 16C650 (10x family)",
321 DEFAULT_RCLK,
322 PUC_PORT_1S1P, 0x18, 4, 0,
323 },
324
325 { 0x131f, 0x1012, 0xffff, 0,
326 "SIIG Cyber I/O PCI 16C850 (10x family)",
327 DEFAULT_RCLK,
328 PUC_PORT_1S1P, 0x18, 4, 0,
329 },
330
331 { 0x131f, 0x1021, 0xffff, 0,
332 "SIIG Cyber Parallel Dual PCI (10x family)",
333 0,
334 PUC_PORT_2P, 0x18, 8, 0,
335 },
336
337 { 0x131f, 0x1030, 0xffff, 0,
338 "SIIG Cyber Serial Dual PCI 16C550 (10x family)",
339 DEFAULT_RCLK,
340 PUC_PORT_2S, 0x18, 4, 0,
341 },
342
343 { 0x131f, 0x1031, 0xffff, 0,
344 "SIIG Cyber Serial Dual PCI 16C650 (10x family)",
345 DEFAULT_RCLK,
346 PUC_PORT_2S, 0x18, 4, 0,
347 },
348
349 { 0x131f, 0x1032, 0xffff, 0,
350 "SIIG Cyber Serial Dual PCI 16C850 (10x family)",
351 DEFAULT_RCLK,
352 PUC_PORT_2S, 0x18, 4, 0,
353 },
354
355 { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */
356 "SIIG Cyber 2S1P PCI 16C550 (10x family)",
357 DEFAULT_RCLK,
358 PUC_PORT_2S1P, 0x18, 4, 0,
359 },
360
361 { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */
362 "SIIG Cyber 2S1P PCI 16C650 (10x family)",
363 DEFAULT_RCLK,
364 PUC_PORT_2S1P, 0x18, 4, 0,
365 },
366
367 { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */
368 "SIIG Cyber 2S1P PCI 16C850 (10x family)",
369 DEFAULT_RCLK,
370 PUC_PORT_2S1P, 0x18, 4, 0,
371 },
372
373 { 0x131f, 0x1050, 0xffff, 0,
374 "SIIG Cyber 4S PCI 16C550 (10x family)",
375 DEFAULT_RCLK,
376 PUC_PORT_4S, 0x18, 4, 0,
377 },
378
379 { 0x131f, 0x1051, 0xffff, 0,
380 "SIIG Cyber 4S PCI 16C650 (10x family)",
381 DEFAULT_RCLK,
382 PUC_PORT_4S, 0x18, 4, 0,
383 },
384
385 { 0x131f, 0x1052, 0xffff, 0,
386 "SIIG Cyber 4S PCI 16C850 (10x family)",
387 DEFAULT_RCLK,
388 PUC_PORT_4S, 0x18, 4, 0,
389 },
390
391 { 0x131f, 0x2010, 0xffff, 0,
392 "SIIG Cyber I/O PCI 16C550 (20x family)",
393 DEFAULT_RCLK,
394 PUC_PORT_1S1P, 0x10, 4, 0,
395 },
396
397 { 0x131f, 0x2011, 0xffff, 0,
398 "SIIG Cyber I/O PCI 16C650 (20x family)",
399 DEFAULT_RCLK,
400 PUC_PORT_1S1P, 0x10, 4, 0,
401 },
402
403 { 0x131f, 0x2012, 0xffff, 0,
404 "SIIG Cyber I/O PCI 16C850 (20x family)",
405 DEFAULT_RCLK,
406 PUC_PORT_1S1P, 0x10, 4, 0,
407 },
408
409 { 0x131f, 0x2021, 0xffff, 0,
410 "SIIG Cyber Parallel Dual PCI (20x family)",
411 0,
412 PUC_PORT_2P, 0x10, 8, 0,
413 },
414
415 { 0x131f, 0x2030, 0xffff, 0,
416 "SIIG Cyber Serial Dual PCI 16C550 (20x family)",
417 DEFAULT_RCLK,
418 PUC_PORT_2S, 0x10, 4, 0,
419 },
420
421 { 0x131f, 0x2031, 0xffff, 0,
422 "SIIG Cyber Serial Dual PCI 16C650 (20x family)",
423 DEFAULT_RCLK,
424 PUC_PORT_2S, 0x10, 4, 0,
425 },
426
427 { 0x131f, 0x2032, 0xffff, 0,
428 "SIIG Cyber Serial Dual PCI 16C850 (20x family)",
429 DEFAULT_RCLK,
430 PUC_PORT_2S, 0x10, 4, 0,
431 },
432
433 { 0x131f, 0x2040, 0xffff, 0,
434 "SIIG Cyber 2P1S PCI 16C550 (20x family)",
435 DEFAULT_RCLK,
436 PUC_PORT_1S2P, 0x10, -1, 0,
437 .config_function = puc_config_siig
438 },
439
440 { 0x131f, 0x2041, 0xffff, 0,
441 "SIIG Cyber 2P1S PCI 16C650 (20x family)",
442 DEFAULT_RCLK,
443 PUC_PORT_1S2P, 0x10, -1, 0,
444 .config_function = puc_config_siig
445 },
446
447 { 0x131f, 0x2042, 0xffff, 0,
448 "SIIG Cyber 2P1S PCI 16C850 (20x family)",
449 DEFAULT_RCLK,
450 PUC_PORT_1S2P, 0x10, -1, 0,
451 .config_function = puc_config_siig
452 },
453
454 { 0x131f, 0x2050, 0xffff, 0,
455 "SIIG Cyber 4S PCI 16C550 (20x family)",
456 DEFAULT_RCLK,
457 PUC_PORT_4S, 0x10, 4, 0,
458 },
459
460 { 0x131f, 0x2051, 0xffff, 0,
461 "SIIG Cyber 4S PCI 16C650 (20x family)",
462 DEFAULT_RCLK,
463 PUC_PORT_4S, 0x10, 4, 0,
464 },
465
466 { 0x131f, 0x2052, 0xffff, 0,
467 "SIIG Cyber 4S PCI 16C850 (20x family)",
468 DEFAULT_RCLK,
469 PUC_PORT_4S, 0x10, 4, 0,
470 },
471
472 { 0x131f, 0x2060, 0xffff, 0,
473 "SIIG Cyber 2S1P PCI 16C550 (20x family)",
474 DEFAULT_RCLK,
475 PUC_PORT_2S1P, 0x10, 4, 0,
476 },
477
478 { 0x131f, 0x2061, 0xffff, 0,
479 "SIIG Cyber 2S1P PCI 16C650 (20x family)",
480 DEFAULT_RCLK,
481 PUC_PORT_2S1P, 0x10, 4, 0,
482 },
483
484 { 0x131f, 0x2062, 0xffff, 0,
485 "SIIG Cyber 2S1P PCI 16C850 (20x family)",
486 DEFAULT_RCLK,
487 PUC_PORT_2S1P, 0x10, 4, 0,
488 },
489
490 { 0x131f, 0x2081, 0xffff, 0,
491 "SIIG PS8000 8S PCI 16C650 (20x family)",
492 DEFAULT_RCLK,
493 PUC_PORT_8S, 0x10, -1, -1,
494 .config_function = puc_config_siig
495 },
496
497 { 0x135a, 0x0841, 0xffff, 0,
498 "Brainboxes UC-268",
499 DEFAULT_RCLK,
500 PUC_PORT_4S, 0x18, 0, 8,
501 },
502
503 { 0x135a, 0x0861, 0xffff, 0,
504 "Brainboxes UC-257",
505 DEFAULT_RCLK,
506 PUC_PORT_2S, 0x18, 0, 8,
507 },
508
509 { 0x135a, 0x0862, 0xffff, 0,
510 "Brainboxes UC-257",
511 DEFAULT_RCLK,
512 PUC_PORT_2S, 0x18, 0, 8,
513 },
514
515 { 0x135a, 0x0863, 0xffff, 0,
516 "Brainboxes UC-257",
517 DEFAULT_RCLK,
518 PUC_PORT_2S, 0x18, 0, 8,
519 },
520
521 { 0x135a, 0x0881, 0xffff, 0,
522 "Brainboxes UC-279",
523 DEFAULT_RCLK,
524 PUC_PORT_8S, 0x18, 0, 8,
525 },
526
527 { 0x135a, 0x08a1, 0xffff, 0,
528 "Brainboxes UC-313",
529 DEFAULT_RCLK,
530 PUC_PORT_2S, 0x18, 0, 8,
531 },
532
533 { 0x135a, 0x08a2, 0xffff, 0,
534 "Brainboxes UC-313",
535 DEFAULT_RCLK,
536 PUC_PORT_2S, 0x18, 0, 8,
537 },
538
539 { 0x135a, 0x08a3, 0xffff, 0,
540 "Brainboxes UC-313",
541 DEFAULT_RCLK,
542 PUC_PORT_2S, 0x18, 0, 8,
543 },
544
545 { 0x135a, 0x08c1, 0xffff, 0,
546 "Brainboxes UC-310",
547 DEFAULT_RCLK,
548 PUC_PORT_2S, 0x18, 0, 8,
549 },
550
551 { 0x135a, 0x08e1, 0xffff, 0,
552 "Brainboxes UC-302",
553 DEFAULT_RCLK,
554 PUC_PORT_2S, 0x18, 0, 8,
555 },
556
557 { 0x135a, 0x08e2, 0xffff, 0,
558 "Brainboxes UC-302",
559 DEFAULT_RCLK,
560 PUC_PORT_2S, 0x18, 0, 8,
561 },
562
563 { 0x135a, 0x08e3, 0xffff, 0,
564 "Brainboxes UC-302",
565 DEFAULT_RCLK,
566 PUC_PORT_2S, 0x18, 0, 8,
567 },
568
569 { 0x135a, 0x0901, 0xffff, 0,
570 "Brainboxes UC-431",
571 DEFAULT_RCLK,
572 PUC_PORT_3S, 0x18, 0, 8,
573 },
574
575 { 0x135a, 0x0921, 0xffff, 0,
576 "Brainboxes UC-420",
577 DEFAULT_RCLK,
578 PUC_PORT_4S, 0x18, 0, 8,
579 },
580
581 { 0x135a, 0x0981, 0xffff, 0,
582 "Brainboxes UC-475",
583 DEFAULT_RCLK,
584 PUC_PORT_2S, 0x18, 0, 8,
585 },
586
587 { 0x135a, 0x0982, 0xffff, 0,
588 "Brainboxes UC-475",
589 DEFAULT_RCLK,
590 PUC_PORT_2S, 0x18, 0, 8,
591 },
592
593 { 0x135a, 0x09a1, 0xffff, 0,
594 "Brainboxes UC-607",
595 DEFAULT_RCLK,
596 PUC_PORT_2S, 0x18, 0, 8,
597 },
598
599 { 0x135a, 0x09a2, 0xffff, 0,
600 "Brainboxes UC-607",
601 DEFAULT_RCLK,
602 PUC_PORT_2S, 0x18, 0, 8,
603 },
604
605 { 0x135a, 0x09a3, 0xffff, 0,
606 "Brainboxes UC-607",
607 DEFAULT_RCLK,
608 PUC_PORT_2S, 0x18, 0, 8,
609 },
610
611 { 0x135a, 0x0a81, 0xffff, 0,
612 "Brainboxes UC-357",
613 DEFAULT_RCLK,
614 PUC_PORT_2S, 0x18, 0, 8,
615 },
616
617 { 0x135a, 0x0a82, 0xffff, 0,
618 "Brainboxes UC-357",
619 DEFAULT_RCLK,
620 PUC_PORT_2S, 0x18, 0, 8,
621 },
622
623 { 0x135a, 0x0a83, 0xffff, 0,
624 "Brainboxes UC-357",
625 DEFAULT_RCLK,
626 PUC_PORT_2S, 0x18, 0, 8,
627 },
628
629 { 0x135a, 0x0ac1, 0xffff, 0,
630 "Brainboxes UP-189",
631 DEFAULT_RCLK,
632 PUC_PORT_2S, 0x18, 0, 8,
633 },
634
635 { 0x135a, 0x0ac2, 0xffff, 0,
636 "Brainboxes UP-189",
637 DEFAULT_RCLK,
638 PUC_PORT_2S, 0x18, 0, 8,
639 },
640
641 { 0x135a, 0x0ac3, 0xffff, 0,
642 "Brainboxes UP-189",
643 DEFAULT_RCLK,
644 PUC_PORT_2S, 0x18, 0, 8,
645 },
646
647 { 0x135a, 0x0b01, 0xffff, 0,
648 "Brainboxes UC-346",
649 DEFAULT_RCLK,
650 PUC_PORT_4S, 0x18, 0, 8,
651 },
652
653 { 0x135a, 0x0b02, 0xffff, 0,
654 "Brainboxes UC-346",
655 DEFAULT_RCLK,
656 PUC_PORT_4S, 0x18, 0, 8,
657 },
658
659 { 0x135a, 0x0b21, 0xffff, 0,
660 "Brainboxes UP-200",
661 DEFAULT_RCLK,
662 PUC_PORT_2S, 0x18, 0, 8,
663 },
664
665 { 0x135a, 0x0b22, 0xffff, 0,
666 "Brainboxes UP-200",
667 DEFAULT_RCLK,
668 PUC_PORT_2S, 0x18, 0, 8,
669 },
670
671 { 0x135a, 0x0b23, 0xffff, 0,
672 "Brainboxes UP-200",
673 DEFAULT_RCLK,
674 PUC_PORT_2S, 0x18, 0, 8,
675 },
676
677 { 0x135a, 0x0ba1, 0xffff, 0,
678 "Brainboxes UC-101",
679 DEFAULT_RCLK,
680 PUC_PORT_2S, 0x18, 0, 8,
681 },
682
683 { 0x135a, 0x0bc1, 0xffff, 0,
684 "Brainboxes UC-203",
685 DEFAULT_RCLK,
686 PUC_PORT_2S, 0x18, 0, 8,
687 },
688
689 { 0x135a, 0x0bc2, 0xffff, 0,
690 "Brainboxes UC-203",
691 DEFAULT_RCLK,
692 PUC_PORT_2S, 0x18, 0, 8,
693 },
694
695 { 0x135a, 0x0c01, 0xffff, 0,
696 "Brainboxes UP-869",
697 DEFAULT_RCLK,
698 PUC_PORT_2S, 0x18, 0, 8,
699 },
700
701 { 0x135a, 0x0c02, 0xffff, 0,
702 "Brainboxes UP-869",
703 DEFAULT_RCLK,
704 PUC_PORT_2S, 0x18, 0, 8,
705 },
706
707 { 0x135a, 0x0c03, 0xffff, 0,
708 "Brainboxes UP-869",
709 DEFAULT_RCLK,
710 PUC_PORT_2S, 0x18, 0, 8,
711 },
712
713 { 0x135a, 0x0c21, 0xffff, 0,
714 "Brainboxes UP-880",
715 DEFAULT_RCLK,
716 PUC_PORT_2S, 0x18, 0, 8,
717 },
718
719 { 0x135a, 0x0c22, 0xffff, 0,
720 "Brainboxes UP-880",
721 DEFAULT_RCLK,
722 PUC_PORT_2S, 0x18, 0, 8,
723 },
724
725 { 0x135a, 0x0c23, 0xffff, 0,
726 "Brainboxes UP-880",
727 DEFAULT_RCLK,
728 PUC_PORT_2S, 0x18, 0, 8,
729 },
730
731 { 0x135a, 0x0c41, 0xffff, 0,
732 "Brainboxes UC-368",
733 DEFAULT_RCLK,
734 PUC_PORT_4S, 0x18, 0, 8,
735 },
736
737 { 0x135a, 0x0ca1, 0xffff, 0,
738 "Brainboxes UC-253",
739 DEFAULT_RCLK,
740 PUC_PORT_2S, 0x18, 0, 8,
741 },
742
743 { 0x135a, 0x0d21, 0xffff, 0,
744 "Brainboxes UC-260",
745 DEFAULT_RCLK,
746 PUC_PORT_4S, 0x18, 0, 8,
747 },
748
749 { 0x135a, 0x0d41, 0xffff, 0,
750 "Brainboxes UC-836",
751 DEFAULT_RCLK,
752 PUC_PORT_4S, 0x18, 0, 8,
753 },
754
755 { 0x135a, 0x0d80, 0xffff, 0,
756 "Intashield IS-200",
757 DEFAULT_RCLK,
758 PUC_PORT_2S, 0x18, 0, 8,
759 },
760
761 { 0x135a, 0x0dc0, 0xffff, 0,
762 "Intashield IS-400",
763 DEFAULT_RCLK,
764 PUC_PORT_4S, 0x18, 0, 8,
765 },
766
767 { 0x135a, 0x0e41, 0xffff, 0,
768 "Brainboxes PX-279",
769 DEFAULT_RCLK,
770 PUC_PORT_8S, 0x18, 0, 8,
771 },
772
773 { 0x135a, 0x0e61, 0xffff, 0,
774 "Brainboxes UC-414",
775 DEFAULT_RCLK,
776 PUC_PORT_4S, 0x18, 0, 8,
777 },
778
779 { 0x135a, 0x400a, 0xffff, 0,
780 "Brainboxes PX-260",
781 DEFAULT_RCLK * 0x22,
782 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
783 .config_function = puc_config_oxford_pcie
784 },
785
786 { 0x135a, 0x400b, 0xffff, 0,
787 "Brainboxes PX-320",
788 DEFAULT_RCLK * 0x22,
789 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
790 .config_function = puc_config_oxford_pcie
791 },
792
793 { 0x135a, 0x400c, 0xffff, 0,
794 "Brainboxes PX-313",
795 DEFAULT_RCLK * 0x22,
796 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
797 .config_function = puc_config_oxford_pcie
798 },
799
800 { 0x135a, 0x400e, 0xffff, 0,
801 "Brainboxes PX-310",
802 DEFAULT_RCLK * 0x22,
803 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
804 .config_function = puc_config_oxford_pcie
805 },
806
807 { 0x135a, 0x400f, 0xffff, 0,
808 "Brainboxes PX-346",
809 DEFAULT_RCLK * 0x22,
810 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
811 .config_function = puc_config_oxford_pcie
812 },
813
814 { 0x135a, 0x4010, 0xffff, 0,
815 "Brainboxes PX-368",
816 DEFAULT_RCLK * 0x22,
817 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
818 .config_function = puc_config_oxford_pcie
819 },
820
821 { 0x135a, 0x4011, 0xffff, 0,
822 "Brainboxes PX-420",
823 DEFAULT_RCLK * 0x22,
824 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
825 .config_function = puc_config_oxford_pcie
826 },
827
828 { 0x135a, 0x4012, 0xffff, 0,
829 "Brainboxes PX-431",
830 DEFAULT_RCLK * 0x22,
831 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
832 .config_function = puc_config_oxford_pcie
833 },
834
835 { 0x135a, 0x4013, 0xffff, 0,
836 "Brainboxes PX-820",
837 DEFAULT_RCLK * 0x22,
838 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
839 .config_function = puc_config_oxford_pcie
840 },
841
842 { 0x135a, 0x4014, 0xffff, 0,
843 "Brainboxes PX-831",
844 DEFAULT_RCLK * 0x22,
845 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
846 .config_function = puc_config_oxford_pcie
847 },
848
849 { 0x135a, 0x4015, 0xffff, 0,
850 "Brainboxes PX-257",
851 DEFAULT_RCLK * 0x22,
852 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
853 .config_function = puc_config_oxford_pcie
854 },
855
856 { 0x135a, 0x4016, 0xffff, 0,
857 "Brainboxes PX-246",
858 DEFAULT_RCLK * 0x22,
859 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
860 .config_function = puc_config_oxford_pcie
861 },
862
863 { 0x135a, 0x4017, 0xffff, 0,
864 "Brainboxes PX-846",
865 DEFAULT_RCLK * 0x22,
866 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
867 .config_function = puc_config_oxford_pcie
868 },
869
870 { 0x135a, 0x4018, 0xffff, 0,
871 "Brainboxes PX-857",
872 DEFAULT_RCLK * 0x22,
873 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
874 .config_function = puc_config_oxford_pcie
875 },
876
877 { 0x135a, 0x4019, 0xffff, 0,
878 "Brainboxes PX-101",
879 DEFAULT_RCLK * 0x22,
880 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
881 .config_function = puc_config_oxford_pcie
882 },
883
884 { 0x135a, 0x401d, 0xffff, 0,
885 "Brainboxes PX-475",
886 DEFAULT_RCLK * 0x22,
887 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
888 .config_function = puc_config_oxford_pcie
889 },
890
891 { 0x135a, 0x401e, 0xffff, 0,
892 "Brainboxes PX-803",
893 DEFAULT_RCLK * 0x22,
894 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
895 .config_function = puc_config_oxford_pcie
896 },
897
898 { 0x135a, 0x4027, 0xffff, 0,
899 "Intashield IX-100",
900 DEFAULT_RCLK * 0x22,
901 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
902 .config_function = puc_config_oxford_pcie
903 },
904
905 { 0x135a, 0x4028, 0xffff, 0,
906 "Intashield IX-200",
907 DEFAULT_RCLK * 0x22,
908 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
909 .config_function = puc_config_oxford_pcie
910 },
911
912 { 0x135a, 0x4029, 0xffff, 0,
913 "Intashield IX-400",
914 DEFAULT_RCLK * 0x22,
915 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
916 .config_function = puc_config_oxford_pcie
917 },
918
919 { 0x135c, 0x0010, 0xffff, 0,
920 "Quatech QSC-100",
921 -3, /* max 8x clock rate */
922 PUC_PORT_4S, 0x14, 0, 8,
923 .config_function = puc_config_quatech
924 },
925
926 { 0x135c, 0x0020, 0xffff, 0,
927 "Quatech DSC-100",
928 -1, /* max 2x clock rate */
929 PUC_PORT_2S, 0x14, 0, 8,
930 .config_function = puc_config_quatech
931 },
932
933 { 0x135c, 0x0030, 0xffff, 0,
934 "Quatech DSC-200/300",
935 -1, /* max 2x clock rate */
936 PUC_PORT_2S, 0x14, 0, 8,
937 .config_function = puc_config_quatech
938 },
939
940 { 0x135c, 0x0040, 0xffff, 0,
941 "Quatech QSC-200/300",
942 -3, /* max 8x clock rate */
943 PUC_PORT_4S, 0x14, 0, 8,
944 .config_function = puc_config_quatech
945 },
946
947 { 0x135c, 0x0050, 0xffff, 0,
948 "Quatech ESC-100D",
949 -3, /* max 8x clock rate */
950 PUC_PORT_8S, 0x14, 0, 8,
951 .config_function = puc_config_quatech
952 },
953
954 { 0x135c, 0x0060, 0xffff, 0,
955 "Quatech ESC-100M",
956 -3, /* max 8x clock rate */
957 PUC_PORT_8S, 0x14, 0, 8,
958 .config_function = puc_config_quatech
959 },
960
961 { 0x135c, 0x0170, 0xffff, 0,
962 "Quatech QSCLP-100",
963 -1, /* max 2x clock rate */
964 PUC_PORT_4S, 0x18, 0, 8,
965 .config_function = puc_config_quatech
966 },
967
968 { 0x135c, 0x0180, 0xffff, 0,
969 "Quatech DSCLP-100",
970 -1, /* max 3x clock rate */
971 PUC_PORT_2S, 0x18, 0, 8,
972 .config_function = puc_config_quatech
973 },
974
975 { 0x135c, 0x01b0, 0xffff, 0,
976 "Quatech DSCLP-200/300",
977 -1, /* max 2x clock rate */
978 PUC_PORT_2S, 0x18, 0, 8,
979 .config_function = puc_config_quatech
980 },
981
982 { 0x135c, 0x01e0, 0xffff, 0,
983 "Quatech ESCLP-100",
984 -3, /* max 8x clock rate */
985 PUC_PORT_8S, 0x10, 0, 8,
986 .config_function = puc_config_quatech
987 },
988
989 { 0x1393, 0x1024, 0xffff, 0,
990 "Moxa Technologies, Smartio CP-102E/PCIe",
991 DEFAULT_RCLK * 8,
992 PUC_PORT_2S, 0x14, 0, -1,
993 .config_function = puc_config_moxa
994 },
995
996 { 0x1393, 0x1025, 0xffff, 0,
997 "Moxa Technologies, Smartio CP-102EL/PCIe",
998 DEFAULT_RCLK * 8,
999 PUC_PORT_2S, 0x14, 0, -1,
1000 .config_function = puc_config_moxa
1001 },
1002
1003 { 0x1393, 0x1040, 0xffff, 0,
1004 "Moxa Technologies, Smartio C104H/PCI",
1005 DEFAULT_RCLK * 8,
1006 PUC_PORT_4S, 0x18, 0, 8,
1007 },
1008
1009 { 0x1393, 0x1041, 0xffff, 0,
1010 "Moxa Technologies, Smartio CP-104UL/PCI",
1011 DEFAULT_RCLK * 8,
1012 PUC_PORT_4S, 0x18, 0, 8,
1013 },
1014
1015 { 0x1393, 0x1042, 0xffff, 0,
1016 "Moxa Technologies, Smartio CP-104JU/PCI",
1017 DEFAULT_RCLK * 8,
1018 PUC_PORT_4S, 0x18, 0, 8,
1019 },
1020
1021 { 0x1393, 0x1043, 0xffff, 0,
1022 "Moxa Technologies, Smartio CP-104EL/PCIe",
1023 DEFAULT_RCLK * 8,
1024 PUC_PORT_4S, 0x18, 0, 8,
1025 },
1026
1027 { 0x1393, 0x1045, 0xffff, 0,
1028 "Moxa Technologies, Smartio CP-104EL-A/PCIe",
1029 DEFAULT_RCLK * 8,
1030 PUC_PORT_4S, 0x14, 0, -1,
1031 .config_function = puc_config_moxa
1032 },
1033
1034 { 0x1393, 0x1120, 0xffff, 0,
1035 "Moxa Technologies, CP-112UL",
1036 DEFAULT_RCLK * 8,
1037 PUC_PORT_2S, 0x18, 0, 8,
1038 },
1039
1040 { 0x1393, 0x1141, 0xffff, 0,
1041 "Moxa Technologies, Industio CP-114",
1042 DEFAULT_RCLK * 8,
1043 PUC_PORT_4S, 0x18, 0, 8,
1044 },
1045
1046 { 0x1393, 0x1144, 0xffff, 0,
1047 "Moxa Technologies, Smartio CP-114EL/PCIe",
1048 DEFAULT_RCLK * 8,
1049 PUC_PORT_4S, 0x14, 0, -1,
1050 .config_function = puc_config_moxa
1051 },
1052
1053 { 0x1393, 0x1182, 0xffff, 0,
1054 "Moxa Technologies, Smartio CP-118EL-A/PCIe",
1055 DEFAULT_RCLK * 8,
1056 PUC_PORT_8S, 0x14, 0, -1,
1057 .config_function = puc_config_moxa
1058 },
1059
1060 { 0x1393, 0x1680, 0xffff, 0,
1061 "Moxa Technologies, C168H/PCI",
1062 DEFAULT_RCLK * 8,
1063 PUC_PORT_8S, 0x18, 0, 8,
1064 },
1065
1066 { 0x1393, 0x1681, 0xffff, 0,
1067 "Moxa Technologies, C168U/PCI",
1068 DEFAULT_RCLK * 8,
1069 PUC_PORT_8S, 0x18, 0, 8,
1070 },
1071
1072 { 0x1393, 0x1682, 0xffff, 0,
1073 "Moxa Technologies, CP-168EL/PCIe",
1074 DEFAULT_RCLK * 8,
1075 PUC_PORT_8S, 0x18, 0, 8,
1076 },
1077
1078 { 0x1393, 0x1683, 0xffff, 0,
1079 "Moxa Technologies, Smartio CP-168EL-A/PCIe",
1080 DEFAULT_RCLK * 8,
1081 PUC_PORT_8S, 0x14, 0, -1,
1082 .config_function = puc_config_moxa
1083 },
1084
1085 { 0x13a8, 0x0152, 0xffff, 0,
1086 "Exar XR17C/D152",
1087 DEFAULT_RCLK * 8,
1088 PUC_PORT_2S, 0x10, 0, -1,
1089 .config_function = puc_config_exar
1090 },
1091
1092 { 0x13a8, 0x0154, 0xffff, 0,
1093 "Exar XR17C154",
1094 DEFAULT_RCLK * 8,
1095 PUC_PORT_4S, 0x10, 0, -1,
1096 .config_function = puc_config_exar
1097 },
1098
1099 { 0x13a8, 0x0158, 0xffff, 0,
1100 "Exar XR17C158",
1101 DEFAULT_RCLK * 8,
1102 PUC_PORT_8S, 0x10, 0, -1,
1103 .config_function = puc_config_exar
1104 },
1105
1106 { 0x13a8, 0x0258, 0xffff, 0,
1107 "Exar XR17V258IV",
1108 DEFAULT_RCLK * 8,
1109 PUC_PORT_8S, 0x10, 0, -1,
1110 .config_function = puc_config_exar
1111 },
1112
1113 { 0x13a8, 0x0352, 0xffff, 0,
1114 "Exar XR17V352",
1115 125000000,
1116 PUC_PORT_2S, 0x10, 0, -1,
1117 .config_function = puc_config_exar_pcie
1118 },
1119
1120 { 0x13a8, 0x0354, 0xffff, 0,
1121 "Exar XR17V354",
1122 125000000,
1123 PUC_PORT_4S, 0x10, 0, -1,
1124 .config_function = puc_config_exar_pcie
1125 },
1126
1127 /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */
1128 { 0x13a8, 0x0358, 0xffff, 0,
1129 "Exar XR17V358",
1130 125000000,
1131 PUC_PORT_8S, 0x10, 0, -1,
1132 .config_function = puc_config_exar_pcie
1133 },
1134
1135 /*
1136 * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford
1137 * Semiconductor OXuPCI954. Note these boards have a hardware bug in
1138 * that they drive the RS-422/485 transmitters after power-on until a
1139 * driver initializes the UARTs.
1140 */
1141 { 0x13fe, 0x1600, 0x1602, 0x0002,
1142 "Advantech PCI-1602 Rev. A",
1143 DEFAULT_RCLK * 8,
1144 PUC_PORT_2S, 0x10, 0, 8,
1145 .config_function = puc_config_advantech
1146 },
1147
1148 /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */
1149 { 0x13fe, 0xa102, 0x13fe, 0xa102,
1150 "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)",
1151 DEFAULT_RCLK * 8,
1152 PUC_PORT_2S, 0x10, 4, 0,
1153 .config_function = puc_config_advantech
1154 },
1155
1156 { 0x1407, 0x0100, 0xffff, 0,
1157 "Lava Computers Dual Serial",
1158 DEFAULT_RCLK,
1159 PUC_PORT_2S, 0x10, 4, 0,
1160 },
1161
1162 { 0x1407, 0x0101, 0xffff, 0,
1163 "Lava Computers Quatro A",
1164 DEFAULT_RCLK,
1165 PUC_PORT_2S, 0x10, 4, 0,
1166 },
1167
1168 { 0x1407, 0x0102, 0xffff, 0,
1169 "Lava Computers Quatro B",
1170 DEFAULT_RCLK,
1171 PUC_PORT_2S, 0x10, 4, 0,
1172 },
1173
1174 { 0x1407, 0x0120, 0xffff, 0,
1175 "Lava Computers Quattro-PCI A",
1176 DEFAULT_RCLK,
1177 PUC_PORT_2S, 0x10, 4, 0,
1178 },
1179
1180 { 0x1407, 0x0121, 0xffff, 0,
1181 "Lava Computers Quattro-PCI B",
1182 DEFAULT_RCLK,
1183 PUC_PORT_2S, 0x10, 4, 0,
1184 },
1185
1186 { 0x1407, 0x0180, 0xffff, 0,
1187 "Lava Computers Octo A",
1188 DEFAULT_RCLK,
1189 PUC_PORT_4S, 0x10, 4, 0,
1190 },
1191
1192 { 0x1407, 0x0181, 0xffff, 0,
1193 "Lava Computers Octo B",
1194 DEFAULT_RCLK,
1195 PUC_PORT_4S, 0x10, 4, 0,
1196 },
1197
1198 { 0x1409, 0x7268, 0xffff, 0,
1199 "Sunix SUN1888",
1200 0,
1201 PUC_PORT_2P, 0x10, 0, 8,
1202 },
1203
1204 { 0x1409, 0x7168, 0xffff, 0,
1205 NULL,
1206 DEFAULT_RCLK * 8,
1207 PUC_PORT_NONSTANDARD, 0x10, -1, -1,
1208 .config_function = puc_config_timedia
1209 },
1210
1211 /*
1212 * Boards with an Oxford Semiconductor chip.
1213 *
1214 * Oxford Semiconductor provides documentation for their chip at:
1215 * <URL:http://www.plxtech.com/products/uart/>
1216 *
1217 * As sold by Kouwell <URL:http://www.kouwell.com/>.
1218 * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports.
1219 */
1220 {
1221 0x1415, 0x9501, 0x10fc, 0xc070,
1222 "I-O DATA RSA-PCI2/R",
1223 DEFAULT_RCLK * 8,
1224 PUC_PORT_2S, 0x10, 0, 8,
1225 },
1226
1227 { 0x1415, 0x9501, 0x131f, 0x2050,
1228 "SIIG Cyber 4 PCI 16550",
1229 DEFAULT_RCLK * 10,
1230 PUC_PORT_4S, 0x10, 0, 8,
1231 },
1232
1233 { 0x1415, 0x9501, 0x131f, 0x2051,
1234 "SIIG Cyber 4S PCI 16C650 (20x family)",
1235 DEFAULT_RCLK * 10,
1236 PUC_PORT_4S, 0x10, 0, 8,
1237 },
1238
1239 { 0x1415, 0x9501, 0x131f, 0x2052,
1240 "SIIG Quartet Serial 850",
1241 DEFAULT_RCLK * 10,
1242 PUC_PORT_4S, 0x10, 0, 8,
1243 },
1244
1245 { 0x1415, 0x9501, 0x14db, 0x2150,
1246 "Kuroutoshikou SERIAL4P-LPPCI2",
1247 DEFAULT_RCLK * 10,
1248 PUC_PORT_4S, 0x10, 0, 8,
1249 },
1250
1251 { 0x1415, 0x9501, 0xffff, 0,
1252 "Oxford Semiconductor OX16PCI954 UARTs",
1253 0,
1254 PUC_PORT_4S, 0x10, 0, 8,
1255 .config_function = puc_config_oxford_pci954
1256 },
1257
1258 { 0x1415, 0x950a, 0x131f, 0x2030,
1259 "SIIG Cyber 2S PCIe",
1260 DEFAULT_RCLK * 10,
1261 PUC_PORT_2S, 0x10, 0, 8,
1262 },
1263
1264 { 0x1415, 0x950a, 0x131f, 0x2032,
1265 "SIIG Cyber Serial Dual PCI 16C850",
1266 DEFAULT_RCLK * 10,
1267 PUC_PORT_4S, 0x10, 0, 8,
1268 },
1269
1270 { 0x1415, 0x950a, 0x131f, 0x2061,
1271 "SIIG Cyber 2SP1 PCIe",
1272 DEFAULT_RCLK * 10,
1273 PUC_PORT_2S, 0x10, 0, 8,
1274 },
1275
1276 { 0x1415, 0x950a, 0xffff, 0,
1277 "Oxford Semiconductor OX16PCI954 UARTs",
1278 DEFAULT_RCLK,
1279 PUC_PORT_4S, 0x10, 0, 8,
1280 },
1281
1282 { 0x1415, 0x9511, 0xffff, 0,
1283 "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)",
1284 DEFAULT_RCLK,
1285 PUC_PORT_4S, 0x10, 0, 8,
1286 },
1287
1288 { 0x1415, 0x9521, 0xffff, 0,
1289 "Oxford Semiconductor OX16PCI952 UARTs",
1290 DEFAULT_RCLK,
1291 PUC_PORT_2S, 0x10, 4, 0,
1292 },
1293
1294 { 0x1415, 0x9538, 0xffff, 0,
1295 "Oxford Semiconductor OX16PCI958 UARTs",
1296 DEFAULT_RCLK,
1297 PUC_PORT_8S, 0x18, 0, 8,
1298 },
1299
1300 /*
1301 * Perle boards use Oxford Semiconductor chips, but they store the
1302 * Oxford Semiconductor device ID as a subvendor device ID and use
1303 * their own device IDs.
1304 */
1305
1306 { 0x155f, 0x0331, 0xffff, 0,
1307 "Perle Ultraport4 Express",
1308 DEFAULT_RCLK * 8,
1309 PUC_PORT_4S, 0x10, 0, 8,
1310 },
1311
1312 { 0x155f, 0xB012, 0xffff, 0,
1313 "Perle Speed2 LE",
1314 DEFAULT_RCLK * 8,
1315 PUC_PORT_2S, 0x10, 0, 8,
1316 },
1317
1318 { 0x155f, 0xB022, 0xffff, 0,
1319 "Perle Speed2 LE",
1320 DEFAULT_RCLK * 8,
1321 PUC_PORT_2S, 0x10, 0, 8,
1322 },
1323
1324 { 0x155f, 0xB004, 0xffff, 0,
1325 "Perle Speed4 LE",
1326 DEFAULT_RCLK * 8,
1327 PUC_PORT_4S, 0x10, 0, 8,
1328 },
1329
1330 { 0x155f, 0xB008, 0xffff, 0,
1331 "Perle Speed8 LE",
1332 DEFAULT_RCLK * 8,
1333 PUC_PORT_8S, 0x10, 0, 8,
1334 },
1335
1336 /*
1337 * Oxford Semiconductor PCI Express Expresso family
1338 *
1339 * Found in many 'native' PCI Express serial boards such as:
1340 *
1341 * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port)
1342 * <URL:http://www.emegatech.com.tw/pdrs232pcie.html>
1343 *
1344 * Lindy 51189 (4 port)
1345 * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189>
1346 *
1347 * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port)
1348 * <URL:http://www.startech.com>
1349 */
1350
1351 { 0x1415, 0xc11b, 0xffff, 0,
1352 "Oxford Semiconductor OXPCIe952 1S1P",
1353 DEFAULT_RCLK * 0x22,
1354 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1355 .config_function = puc_config_oxford_pcie
1356 },
1357
1358 { 0x1415, 0xc138, 0xffff, 0,
1359 "Oxford Semiconductor OXPCIe952 UARTs",
1360 DEFAULT_RCLK * 0x22,
1361 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1362 .config_function = puc_config_oxford_pcie
1363 },
1364
1365 { 0x1415, 0xc158, 0xffff, 0,
1366 "Oxford Semiconductor OXPCIe952 UARTs",
1367 DEFAULT_RCLK * 0x22,
1368 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1369 .config_function = puc_config_oxford_pcie
1370 },
1371
1372 { 0x1415, 0xc15d, 0xffff, 0,
1373 "Oxford Semiconductor OXPCIe952 UARTs (function 1)",
1374 DEFAULT_RCLK * 0x22,
1375 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1376 .config_function = puc_config_oxford_pcie
1377 },
1378
1379 { 0x1415, 0xc208, 0xffff, 0,
1380 "Oxford Semiconductor OXPCIe954 UARTs",
1381 DEFAULT_RCLK * 0x22,
1382 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1383 .config_function = puc_config_oxford_pcie
1384 },
1385
1386 { 0x1415, 0xc20d, 0xffff, 0,
1387 "Oxford Semiconductor OXPCIe954 UARTs (function 1)",
1388 DEFAULT_RCLK * 0x22,
1389 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1390 .config_function = puc_config_oxford_pcie
1391 },
1392
1393 { 0x1415, 0xc308, 0xffff, 0,
1394 "Oxford Semiconductor OXPCIe958 UARTs",
1395 DEFAULT_RCLK * 0x22,
1396 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1397 .config_function = puc_config_oxford_pcie
1398 },
1399
1400 { 0x1415, 0xc30d, 0xffff, 0,
1401 "Oxford Semiconductor OXPCIe958 UARTs (function 1)",
1402 DEFAULT_RCLK * 0x22,
1403 PUC_PORT_NONSTANDARD, 0x10, 0, -1,
1404 .config_function = puc_config_oxford_pcie
1405 },
1406
1407 { 0x14d2, 0x8010, 0xffff, 0,
1408 "VScom PCI-100L",
1409 DEFAULT_RCLK * 8,
1410 PUC_PORT_1S, 0x14, 0, 0,
1411 },
1412
1413 { 0x14d2, 0x8020, 0xffff, 0,
1414 "VScom PCI-200L",
1415 DEFAULT_RCLK * 8,
1416 PUC_PORT_2S, 0x14, 4, 0,
1417 },
1418
1419 { 0x14d2, 0x8028, 0xffff, 0,
1420 "VScom 200Li",
1421 DEFAULT_RCLK,
1422 PUC_PORT_2S, 0x20, 0, 8,
1423 },
1424
1425 /*
1426 * VScom (Titan?) PCI-800L. More modern variant of the
1427 * PCI-800. Uses 6 discrete 16550 UARTs, plus another
1428 * two of them obviously implemented as macro cells in
1429 * the ASIC. This causes the weird port access pattern
1430 * below, where two of the IO port ranges each access
1431 * one of the ASIC UARTs, and a block of IO addresses
1432 * access the external UARTs.
1433 */
1434 { 0x14d2, 0x8080, 0xffff, 0,
1435 "Titan VScom PCI-800L",
1436 DEFAULT_RCLK * 8,
1437 PUC_PORT_8S, 0x14, -1, -1,
1438 .config_function = puc_config_titan
1439 },
1440
1441 /*
1442 * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers
1443 * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has
1444 * device ID 3 and PCI device 1 device ID 4.
1445 */
1446 { 0x14d2, 0xa003, 0xffff, 0,
1447 "Titan PCI-800H",
1448 DEFAULT_RCLK * 8,
1449 PUC_PORT_4S, 0x10, 0, 8,
1450 },
1451
1452 { 0x14d2, 0xa004, 0xffff, 0,
1453 "Titan PCI-800H",
1454 DEFAULT_RCLK * 8,
1455 PUC_PORT_4S, 0x10, 0, 8,
1456 },
1457
1458 { 0x14d2, 0xa005, 0xffff, 0,
1459 "Titan PCI-200H",
1460 DEFAULT_RCLK * 8,
1461 PUC_PORT_2S, 0x10, 0, 8,
1462 },
1463
1464 { 0x14d2, 0xe020, 0xffff, 0,
1465 "Titan VScom PCI-200HV2",
1466 DEFAULT_RCLK * 8,
1467 PUC_PORT_2S, 0x10, 4, 0,
1468 },
1469
1470 { 0x14d2, 0xa007, 0xffff, 0,
1471 "Titan VScom PCIex-800H",
1472 DEFAULT_RCLK * 8,
1473 PUC_PORT_4S, 0x10, 0, 8,
1474 },
1475
1476 { 0x14d2, 0xa008, 0xffff, 0,
1477 "Titan VScom PCIex-800H",
1478 DEFAULT_RCLK * 8,
1479 PUC_PORT_4S, 0x10, 0, 8,
1480 },
1481
1482 { 0x14db, 0x2130, 0xffff, 0,
1483 "Avlab Technology, PCI IO 2S",
1484 DEFAULT_RCLK,
1485 PUC_PORT_2S, 0x10, 4, 0,
1486 },
1487
1488 { 0x14db, 0x2150, 0xffff, 0,
1489 "Avlab Low Profile PCI 4 Serial",
1490 DEFAULT_RCLK,
1491 PUC_PORT_4S, 0x10, 4, 0,
1492 },
1493
1494 { 0x14db, 0x2152, 0xffff, 0,
1495 "Avlab Low Profile PCI 4 Serial",
1496 DEFAULT_RCLK,
1497 PUC_PORT_4S, 0x10, 4, 0,
1498 },
1499
1500 { 0x1592, 0x0781, 0xffff, 0,
1501 "Syba Tech Ltd. PCI-4S2P-550-ECP",
1502 DEFAULT_RCLK,
1503 PUC_PORT_4S1P, 0x10, 0, -1,
1504 .config_function = puc_config_syba
1505 },
1506
1507 { 0x1fd4, 0x1999, 0x1fd4, 0x0002,
1508 "Sunix SER5xxxx 2-port serial",
1509 DEFAULT_RCLK * 8,
1510 PUC_PORT_2S, 0x10, 0, 8,
1511 },
1512
1513 { 0x1fd4, 0x1999, 0x1fd4, 0x0004,
1514 "Sunix SER5xxxx 4-port serial",
1515 DEFAULT_RCLK * 8,
1516 PUC_PORT_4S, 0x10, 0, 8,
1517 },
1518
1519 { 0x1fd4, 0x1999, 0x1fd4, 0x0008,
1520 "Sunix SER5xxxx 8-port serial",
1521 DEFAULT_RCLK * 8,
1522 PUC_PORT_8S, -1, -1, -1,
1523 .config_function = puc_config_sunix
1524 },
1525
1526 { 0x1fd4, 0x1999, 0x1fd4, 0x0101,
1527 "Sunix MIO5xxxx 1-port serial and 1284 Printer port",
1528 DEFAULT_RCLK * 8,
1529 PUC_PORT_1S1P, -1, -1, -1,
1530 .config_function = puc_config_sunix
1531 },
1532
1533 { 0x1fd4, 0x1999, 0x1fd4, 0x0102,
1534 "Sunix MIO5xxxx 2-port serial and 1284 Printer port",
1535 DEFAULT_RCLK * 8,
1536 PUC_PORT_2S1P, -1, -1, -1,
1537 .config_function = puc_config_sunix
1538 },
1539
1540 { 0x1fd4, 0x1999, 0x1fd4, 0x0104,
1541 "Sunix MIO5xxxx 4-port serial and 1284 Printer port",
1542 DEFAULT_RCLK * 8,
1543 PUC_PORT_4S1P, -1, -1, -1,
1544 .config_function = puc_config_sunix
1545 },
1546
1547 { 0x5372, 0x6872, 0xffff, 0,
1548 "Feasso PCI FPP-02 2S1P",
1549 DEFAULT_RCLK,
1550 PUC_PORT_2S1P, 0x10, 4, 0,
1551 },
1552
1553 { 0x5372, 0x6873, 0xffff, 0,
1554 "Sun 1040 PCI Quad Serial",
1555 DEFAULT_RCLK,
1556 PUC_PORT_4S, 0x10, 4, 0,
1557 },
1558
1559 { 0x6666, 0x0001, 0xffff, 0,
1560 "Decision Computer Inc, PCCOM 4-port serial",
1561 DEFAULT_RCLK,
1562 PUC_PORT_4S, 0x1c, 0, 8,
1563 },
1564
1565 { 0x6666, 0x0002, 0xffff, 0,
1566 "Decision Computer Inc, PCCOM 8-port serial",
1567 DEFAULT_RCLK,
1568 PUC_PORT_8S, 0x1c, 0, 8,
1569 },
1570
1571 { 0x6666, 0x0004, 0xffff, 0,
1572 "PCCOM dual port RS232/422/485",
1573 DEFAULT_RCLK,
1574 PUC_PORT_2S, 0x1c, 0, 8,
1575 },
1576
1577 { 0x9710, 0x9815, 0xffff, 0,
1578 "NetMos NM9815 Dual 1284 Printer port",
1579 0,
1580 PUC_PORT_2P, 0x10, 8, 0,
1581 },
1582
1583 /*
1584 * This is more specific than the generic NM9835 entry, and is placed
1585 * here to _prevent_ puc(4) from claiming this single port card.
1586 *
1587 * uart(4) will claim this device.
1588 */
1589 { 0x9710, 0x9835, 0x1000, 1,
1590 "NetMos NM9835 based 1-port serial",
1591 DEFAULT_RCLK,
1592 PUC_PORT_1S, 0x10, 4, 0,
1593 },
1594
1595 { 0x9710, 0x9835, 0x1000, 2,
1596 "NetMos NM9835 based 2-port serial",
1597 DEFAULT_RCLK,
1598 PUC_PORT_2S, 0x10, 4, 0,
1599 },
1600
1601 { 0x9710, 0x9835, 0xffff, 0,
1602 "NetMos NM9835 Dual UART and 1284 Printer port",
1603 DEFAULT_RCLK,
1604 PUC_PORT_2S1P, 0x10, 4, 0,
1605 },
1606
1607 { 0x9710, 0x9845, 0x1000, 0x0006,
1608 "NetMos NM9845 6 Port UART",
1609 DEFAULT_RCLK,
1610 PUC_PORT_6S, 0x10, 4, 0,
1611 },
1612
1613 { 0x9710, 0x9845, 0xffff, 0,
1614 "NetMos NM9845 Quad UART and 1284 Printer port",
1615 DEFAULT_RCLK,
1616 PUC_PORT_4S1P, 0x10, 4, 0,
1617 },
1618
1619 { 0x9710, 0x9865, 0xa000, 0x3002,
1620 "NetMos NM9865 Dual UART",
1621 DEFAULT_RCLK,
1622 PUC_PORT_2S, 0x10, 4, 0,
1623 },
1624
1625 { 0x9710, 0x9865, 0xa000, 0x3003,
1626 "NetMos NM9865 Triple UART",
1627 DEFAULT_RCLK,
1628 PUC_PORT_3S, 0x10, 4, 0,
1629 },
1630
1631 { 0x9710, 0x9865, 0xa000, 0x3004,
1632 "NetMos NM9865 Quad UART",
1633 DEFAULT_RCLK,
1634 PUC_PORT_4S, 0x10, 4, 0,
1635 },
1636
1637 { 0x9710, 0x9865, 0xa000, 0x3011,
1638 "NetMos NM9865 Single UART and 1284 Printer port",
1639 DEFAULT_RCLK,
1640 PUC_PORT_1S1P, 0x10, 4, 0,
1641 },
1642
1643 { 0x9710, 0x9865, 0xa000, 0x3012,
1644 "NetMos NM9865 Dual UART and 1284 Printer port",
1645 DEFAULT_RCLK,
1646 PUC_PORT_2S1P, 0x10, 4, 0,
1647 },
1648
1649 { 0x9710, 0x9865, 0xa000, 0x3020,
1650 "NetMos NM9865 Dual 1284 Printer port",
1651 DEFAULT_RCLK,
1652 PUC_PORT_2P, 0x10, 4, 0,
1653 },
1654
1655 { 0xb00c, 0x021c, 0xffff, 0,
1656 "IC Book Labs Gunboat x4 Lite",
1657 DEFAULT_RCLK,
1658 PUC_PORT_4S, 0x10, 0, 8,
1659 .config_function = puc_config_icbook
1660 },
1661
1662 { 0xb00c, 0x031c, 0xffff, 0,
1663 "IC Book Labs Gunboat x4 Pro",
1664 DEFAULT_RCLK,
1665 PUC_PORT_4S, 0x10, 0, 8,
1666 .config_function = puc_config_icbook
1667 },
1668
1669 { 0xb00c, 0x041c, 0xffff, 0,
1670 "IC Book Labs Ironclad x8 Lite",
1671 DEFAULT_RCLK,
1672 PUC_PORT_8S, 0x10, 0, 8,
1673 .config_function = puc_config_icbook
1674 },
1675
1676 { 0xb00c, 0x051c, 0xffff, 0,
1677 "IC Book Labs Ironclad x8 Pro",
1678 DEFAULT_RCLK,
1679 PUC_PORT_8S, 0x10, 0, 8,
1680 .config_function = puc_config_icbook
1681 },
1682
1683 { 0xb00c, 0x081c, 0xffff, 0,
1684 "IC Book Labs Dreadnought x16 Pro",
1685 DEFAULT_RCLK * 8,
1686 PUC_PORT_16S, 0x10, 0, 8,
1687 .config_function = puc_config_icbook
1688 },
1689
1690 { 0xb00c, 0x091c, 0xffff, 0,
1691 "IC Book Labs Dreadnought x16 Lite",
1692 DEFAULT_RCLK,
1693 PUC_PORT_16S, 0x10, 0, 8,
1694 .config_function = puc_config_icbook
1695 },
1696
1697 { 0xb00c, 0x0a1c, 0xffff, 0,
1698 "IC Book Labs Gunboat x2 Low Profile",
1699 DEFAULT_RCLK,
1700 PUC_PORT_2S, 0x10, 0, 8,
1701 },
1702
1703 { 0xb00c, 0x0b1c, 0xffff, 0,
1704 "IC Book Labs Gunboat x4 Low Profile",
1705 DEFAULT_RCLK,
1706 PUC_PORT_4S, 0x10, 0, 8,
1707 .config_function = puc_config_icbook
1708 },
1709
1710 /*
1711 * Systembase cards using SB16C1050 UARTs:
1712 */
1713 { 0x14a1, 0x0008, 0x14a1, 0x0008,
1714 "Systembase SB16C1058",
1715 DEFAULT_RCLK * 8,
1716 PUC_PORT_8S, 0x10, 0, 8,
1717 .config_function = puc_config_systembase,
1718 },
1719 { 0x14a1, 0x0004, 0x14a1, 0x0004,
1720 "Systembase SB16C1054",
1721 DEFAULT_RCLK * 8,
1722 PUC_PORT_4S, 0x10, 0, 8,
1723 .config_function = puc_config_systembase,
1724 },
1725
1726 { 0xffff, 0, 0xffff, 0, NULL, 0 }
1727 };
1728
1729 static int
puc_config_advantech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res __unused)1730 puc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1731 intptr_t *res __unused)
1732 {
1733 const struct puc_cfg *cfg;
1734 struct resource *cres;
1735 struct puc_bar *bar;
1736 device_t cdev, dev;
1737 bus_size_t off;
1738 int base, crtype, fixed, high, i, oxpcie;
1739 uint8_t acr, func, mask;
1740
1741 if (cmd != PUC_CFG_SETUP)
1742 return (ENXIO);
1743
1744 base = fixed = oxpcie = 0;
1745 crtype = SYS_RES_IOPORT;
1746 acr = mask = 0x0;
1747 func = high = 1;
1748 off = 0x60;
1749
1750 cfg = sc->sc_cfg;
1751 switch (cfg->subvendor) {
1752 case 0x13fe:
1753 switch (cfg->device) {
1754 case 0xa102:
1755 high = 0;
1756 break;
1757 default:
1758 break;
1759 }
1760 default:
1761 break;
1762 }
1763 if (fixed == 1)
1764 goto setup;
1765
1766 dev = sc->sc_dev;
1767 cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev),
1768 pci_get_slot(dev), func);
1769 if (cdev == NULL) {
1770 device_printf(dev, "could not find config function\n");
1771 return (ENXIO);
1772 }
1773
1774 i = PCIR_BAR(0);
1775 cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE);
1776 if (cres == NULL) {
1777 device_printf(dev, "could not allocate config resource\n");
1778 return (ENXIO);
1779 }
1780
1781 if (oxpcie == 0) {
1782 mask = bus_read_1(cres, off);
1783 if (pci_get_function(dev) == 1)
1784 base = 4;
1785 }
1786
1787 setup:
1788 for (i = 0; i < sc->sc_nports; ++i) {
1789 device_printf(dev, "port %d: ", i);
1790 bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid);
1791 if (bar == NULL) {
1792 printf("could not get BAR\n");
1793 continue;
1794 }
1795
1796 if (fixed == 0) {
1797 if ((mask & (1 << (base + i))) == 0) {
1798 acr = 0;
1799 printf("RS-232\n");
1800 } else {
1801 acr = (high == 1 ? 0x18 : 0x10);
1802 printf("RS-422/RS-485, active-%s auto-DTR\n",
1803 high == 1 ? "high" : "low");
1804 }
1805 }
1806
1807 bus_write_1(bar->b_res, REG_SPR, REG_ACR);
1808 bus_write_1(bar->b_res, REG_ICR, acr);
1809 }
1810
1811 bus_release_resource(cdev, crtype, rman_get_rid(cres), cres);
1812 return (0);
1813 }
1814
1815 static int
puc_config_amc(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1816 puc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port,
1817 intptr_t *res)
1818 {
1819
1820 switch (cmd) {
1821 case PUC_CFG_GET_OFS:
1822 *res = 8 * (port & 1);
1823 return (0);
1824 case PUC_CFG_GET_RID:
1825 *res = 0x14 + (port >> 1) * 4;
1826 return (0);
1827 default:
1828 break;
1829 }
1830 return (ENXIO);
1831 }
1832
1833 static int
puc_config_diva(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1834 puc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1835 intptr_t *res)
1836 {
1837 const struct puc_cfg *cfg = sc->sc_cfg;
1838
1839 if (cmd == PUC_CFG_GET_OFS) {
1840 if (cfg->subdevice == 0x1282) /* Everest SP */
1841 port <<= 1;
1842 else if (cfg->subdevice == 0x104b) /* Maestro SP2 */
1843 port = (port == 3) ? 4 : port;
1844 *res = port * 8 + ((port > 2) ? 0x18 : 0);
1845 return (0);
1846 }
1847 return (ENXIO);
1848 }
1849
1850 static int
puc_config_exar(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1851 puc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1852 int port, intptr_t *res)
1853 {
1854
1855 if (cmd == PUC_CFG_GET_OFS) {
1856 *res = port * 0x200;
1857 return (0);
1858 }
1859 return (ENXIO);
1860 }
1861
1862 static int
puc_config_exar_pcie(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)1863 puc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1864 int port, intptr_t *res)
1865 {
1866
1867 if (cmd == PUC_CFG_GET_OFS) {
1868 *res = port * 0x400;
1869 return (0);
1870 }
1871 return (ENXIO);
1872 }
1873
1874 static int
puc_config_icbook(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1875 puc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
1876 int port __unused, intptr_t *res)
1877 {
1878
1879 if (cmd == PUC_CFG_GET_ILR) {
1880 *res = PUC_ILR_DIGI;
1881 return (0);
1882 }
1883 return (ENXIO);
1884 }
1885
1886 static int
puc_config_moxa(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1887 puc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1888 intptr_t *res)
1889 {
1890 const struct puc_cfg *cfg = sc->sc_cfg;
1891
1892 if (cmd == PUC_CFG_GET_OFS) {
1893 if (port == 3 && (cfg->device == 0x1045 ||
1894 cfg->device == 0x1144))
1895 port = 7;
1896 *res = port * 0x200;
1897
1898 return 0;
1899 }
1900 return (ENXIO);
1901 }
1902
1903 static int
puc_config_quatech(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)1904 puc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd,
1905 int port __unused, intptr_t *res)
1906 {
1907 const struct puc_cfg *cfg = sc->sc_cfg;
1908 struct puc_bar *bar;
1909 uint8_t v0, v1;
1910
1911 switch (cmd) {
1912 case PUC_CFG_SETUP:
1913 /*
1914 * Check if the scratchpad register is enabled or if the
1915 * interrupt status and options registers are active.
1916 */
1917 bar = puc_get_bar(sc, cfg->rid);
1918 if (bar == NULL)
1919 return (ENXIO);
1920 bus_write_1(bar->b_res, REG_LCR, LCR_DLAB);
1921 bus_write_1(bar->b_res, REG_SPR, 0);
1922 v0 = bus_read_1(bar->b_res, REG_SPR);
1923 bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock);
1924 v1 = bus_read_1(bar->b_res, REG_SPR);
1925 bus_write_1(bar->b_res, REG_LCR, 0);
1926 sc->sc_cfg_data = (v0 << 8) | v1;
1927 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1928 /*
1929 * The SPR register echoed the two values written
1930 * by us. This means that the SPAD jumper is set.
1931 */
1932 device_printf(sc->sc_dev, "warning: extra features "
1933 "not usable -- SPAD compatibility enabled\n");
1934 return (0);
1935 }
1936 if (v0 != 0) {
1937 /*
1938 * The first value doesn't match. This can only mean
1939 * that the SPAD jumper is not set and that a non-
1940 * standard fixed clock multiplier jumper is set.
1941 */
1942 if (bootverbose)
1943 device_printf(sc->sc_dev, "fixed clock rate "
1944 "multiplier of %d\n", 1 << v0);
1945 if (v0 < -cfg->clock)
1946 device_printf(sc->sc_dev, "warning: "
1947 "suboptimal fixed clock rate multiplier "
1948 "setting\n");
1949 return (0);
1950 }
1951 /*
1952 * The first value matched, but the second didn't. We know
1953 * that the SPAD jumper is not set. We also know that the
1954 * clock rate multiplier is software controlled *and* that
1955 * we just programmed it to the maximum allowed.
1956 */
1957 if (bootverbose)
1958 device_printf(sc->sc_dev, "clock rate multiplier of "
1959 "%d selected\n", 1 << -cfg->clock);
1960 return (0);
1961 case PUC_CFG_GET_CLOCK:
1962 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1963 v1 = sc->sc_cfg_data & 0xff;
1964 if (v0 == 0 && v1 == 0x80 + -cfg->clock) {
1965 /*
1966 * XXX With the SPAD jumper applied, there's no
1967 * easy way of knowing if there's also a clock
1968 * rate multiplier jumper installed. Let's hope
1969 * not ...
1970 */
1971 *res = DEFAULT_RCLK;
1972 } else if (v0 == 0) {
1973 /*
1974 * No clock rate multiplier jumper installed,
1975 * so we programmed the board with the maximum
1976 * multiplier allowed as given to us in the
1977 * clock field of the config record (negated).
1978 */
1979 *res = DEFAULT_RCLK << -cfg->clock;
1980 } else
1981 *res = DEFAULT_RCLK << v0;
1982 return (0);
1983 case PUC_CFG_GET_ILR:
1984 v0 = (sc->sc_cfg_data >> 8) & 0xff;
1985 v1 = sc->sc_cfg_data & 0xff;
1986 *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ?
1987 PUC_ILR_NONE : PUC_ILR_QUATECH;
1988 return (0);
1989 default:
1990 break;
1991 }
1992 return (ENXIO);
1993 }
1994
1995 static int
puc_config_syba(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)1996 puc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
1997 intptr_t *res)
1998 {
1999 static int base[] = { 0x251, 0x3f0, 0 };
2000 const struct puc_cfg *cfg = sc->sc_cfg;
2001 struct puc_bar *bar;
2002 int efir, idx, ofs;
2003 uint8_t v;
2004
2005 switch (cmd) {
2006 case PUC_CFG_SETUP:
2007 bar = puc_get_bar(sc, cfg->rid);
2008 if (bar == NULL)
2009 return (ENXIO);
2010
2011 /* configure both W83877TFs */
2012 bus_write_1(bar->b_res, 0x250, 0x89);
2013 bus_write_1(bar->b_res, 0x3f0, 0x87);
2014 bus_write_1(bar->b_res, 0x3f0, 0x87);
2015 idx = 0;
2016 while (base[idx] != 0) {
2017 efir = base[idx];
2018 bus_write_1(bar->b_res, efir, 0x09);
2019 v = bus_read_1(bar->b_res, efir + 1);
2020 if ((v & 0x0f) != 0x0c)
2021 return (ENXIO);
2022 bus_write_1(bar->b_res, efir, 0x16);
2023 v = bus_read_1(bar->b_res, efir + 1);
2024 bus_write_1(bar->b_res, efir, 0x16);
2025 bus_write_1(bar->b_res, efir + 1, v | 0x04);
2026 bus_write_1(bar->b_res, efir, 0x16);
2027 bus_write_1(bar->b_res, efir + 1, v & ~0x04);
2028 ofs = base[idx] & 0x300;
2029 bus_write_1(bar->b_res, efir, 0x23);
2030 bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2);
2031 bus_write_1(bar->b_res, efir, 0x24);
2032 bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2);
2033 bus_write_1(bar->b_res, efir, 0x25);
2034 bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2);
2035 bus_write_1(bar->b_res, efir, 0x17);
2036 bus_write_1(bar->b_res, efir + 1, 0x03);
2037 bus_write_1(bar->b_res, efir, 0x28);
2038 bus_write_1(bar->b_res, efir + 1, 0x43);
2039 idx++;
2040 }
2041 bus_write_1(bar->b_res, 0x250, 0xaa);
2042 bus_write_1(bar->b_res, 0x3f0, 0xaa);
2043 return (0);
2044 case PUC_CFG_GET_OFS:
2045 switch (port) {
2046 case 0:
2047 *res = 0x2f8;
2048 return (0);
2049 case 1:
2050 *res = 0x2e8;
2051 return (0);
2052 case 2:
2053 *res = 0x3f8;
2054 return (0);
2055 case 3:
2056 *res = 0x3e8;
2057 return (0);
2058 case 4:
2059 *res = 0x278;
2060 return (0);
2061 }
2062 break;
2063 default:
2064 break;
2065 }
2066 return (ENXIO);
2067 }
2068
2069 static int
puc_config_siig(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2070 puc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2071 intptr_t *res)
2072 {
2073 const struct puc_cfg *cfg = sc->sc_cfg;
2074
2075 switch (cmd) {
2076 case PUC_CFG_GET_OFS:
2077 if (cfg->ports == PUC_PORT_8S) {
2078 *res = (port > 4) ? 8 * (port - 4) : 0;
2079 return (0);
2080 }
2081 break;
2082 case PUC_CFG_GET_RID:
2083 if (cfg->ports == PUC_PORT_8S) {
2084 *res = 0x10 + ((port > 4) ? 0x10 : 4 * port);
2085 return (0);
2086 }
2087 if (cfg->ports == PUC_PORT_2S1P) {
2088 switch (port) {
2089 case 0: *res = 0x10; return (0);
2090 case 1: *res = 0x14; return (0);
2091 case 2: *res = 0x1c; return (0);
2092 }
2093 }
2094 break;
2095 default:
2096 break;
2097 }
2098 return (ENXIO);
2099 }
2100
2101 static int
puc_config_timedia(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2102 puc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2103 intptr_t *res)
2104 {
2105 static const uint16_t dual[] = {
2106 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
2107 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
2108 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
2109 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
2110 0xD079, 0
2111 };
2112 static const uint16_t quad[] = {
2113 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
2114 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
2115 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
2116 0xB157, 0
2117 };
2118 static const uint16_t octa[] = {
2119 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
2120 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
2121 };
2122 static const struct {
2123 int ports;
2124 const uint16_t *ids;
2125 } subdevs[] = {
2126 { 2, dual },
2127 { 4, quad },
2128 { 8, octa },
2129 { 0, NULL }
2130 };
2131 static char desc[64];
2132 int dev, id;
2133 uint16_t subdev;
2134
2135 switch (cmd) {
2136 case PUC_CFG_GET_CLOCK:
2137 if (port < 2)
2138 *res = DEFAULT_RCLK * 8;
2139 else
2140 *res = DEFAULT_RCLK;
2141 return (0);
2142 case PUC_CFG_GET_DESC:
2143 snprintf(desc, sizeof(desc),
2144 "Timedia technology %d Port Serial", (int)sc->sc_cfg_data);
2145 *res = (intptr_t)desc;
2146 return (0);
2147 case PUC_CFG_GET_NPORTS:
2148 subdev = pci_get_subdevice(sc->sc_dev);
2149 dev = 0;
2150 while (subdevs[dev].ports != 0) {
2151 id = 0;
2152 while (subdevs[dev].ids[id] != 0) {
2153 if (subdev == subdevs[dev].ids[id]) {
2154 sc->sc_cfg_data = subdevs[dev].ports;
2155 *res = sc->sc_cfg_data;
2156 return (0);
2157 }
2158 id++;
2159 }
2160 dev++;
2161 }
2162 return (ENXIO);
2163 case PUC_CFG_GET_OFS:
2164 *res = (port == 1 || port == 3) ? 8 : 0;
2165 return (0);
2166 case PUC_CFG_GET_RID:
2167 *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4;
2168 return (0);
2169 case PUC_CFG_GET_TYPE:
2170 *res = PUC_TYPE_SERIAL;
2171 return (0);
2172 default:
2173 break;
2174 }
2175 return (ENXIO);
2176 }
2177
2178 static int
puc_config_oxford_pci954(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port __unused,intptr_t * res)2179 puc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd,
2180 int port __unused, intptr_t *res)
2181 {
2182
2183 switch (cmd) {
2184 case PUC_CFG_GET_CLOCK:
2185 /*
2186 * OXu16PCI954 use a 14.7456 MHz clock by default while
2187 * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one.
2188 */
2189 if (pci_get_revid(sc->sc_dev) == 1)
2190 *res = DEFAULT_RCLK * 8;
2191 else
2192 *res = DEFAULT_RCLK;
2193 return (0);
2194 default:
2195 break;
2196 }
2197 return (ENXIO);
2198 }
2199
2200 static int
puc_config_oxford_pcie(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2201 puc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2202 intptr_t *res)
2203 {
2204 const struct puc_cfg *cfg = sc->sc_cfg;
2205 int idx;
2206 struct puc_bar *bar;
2207 uint8_t value;
2208
2209 switch (cmd) {
2210 case PUC_CFG_SETUP:
2211 device_printf(sc->sc_dev, "%d UARTs detected\n",
2212 sc->sc_nports);
2213
2214 /* Set UARTs to enhanced mode */
2215 bar = puc_get_bar(sc, cfg->rid);
2216 if (bar == NULL)
2217 return (ENXIO);
2218 for (idx = 0; idx < sc->sc_nports; idx++) {
2219 value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) +
2220 0x92);
2221 bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92,
2222 value | 0x10);
2223 }
2224 return (0);
2225 case PUC_CFG_GET_LEN:
2226 *res = 0x200;
2227 return (0);
2228 case PUC_CFG_GET_NPORTS:
2229 /*
2230 * Check if we are being called from puc_bfe_attach()
2231 * or puc_bfe_probe(). If puc_bfe_probe(), we cannot
2232 * puc_get_bar(), so we return a value of 16. This has
2233 * cosmetic side-effects at worst; in PUC_CFG_GET_DESC,
2234 * sc->sc_cfg_data will not contain the true number of
2235 * ports in PUC_CFG_GET_DESC, but we are not implementing
2236 * that call for this device family anyway.
2237 *
2238 * The check is for initialization of sc->sc_bar[idx],
2239 * which is only done in puc_bfe_attach().
2240 */
2241 idx = 0;
2242 do {
2243 if (sc->sc_bar[idx++].b_rid != -1) {
2244 sc->sc_cfg_data = 16;
2245 *res = sc->sc_cfg_data;
2246 return (0);
2247 }
2248 } while (idx < PUC_PCI_BARS);
2249
2250 bar = puc_get_bar(sc, cfg->rid);
2251 if (bar == NULL)
2252 return (ENXIO);
2253
2254 value = bus_read_1(bar->b_res, 0x04);
2255 if (value == 0)
2256 return (ENXIO);
2257
2258 sc->sc_cfg_data = value;
2259 *res = sc->sc_cfg_data;
2260 return (0);
2261 case PUC_CFG_GET_OFS:
2262 *res = 0x1000 + (port << 9);
2263 return (0);
2264 case PUC_CFG_GET_TYPE:
2265 *res = PUC_TYPE_SERIAL;
2266 return (0);
2267 default:
2268 break;
2269 }
2270 return (ENXIO);
2271 }
2272
2273 static int
puc_config_sunix(struct puc_softc * sc,enum puc_cfg_cmd cmd,int port,intptr_t * res)2274 puc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port,
2275 intptr_t *res)
2276 {
2277 int error;
2278
2279 switch (cmd) {
2280 case PUC_CFG_GET_OFS:
2281 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
2282 if (error != 0)
2283 return (error);
2284 *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0;
2285 return (0);
2286 case PUC_CFG_GET_RID:
2287 error = puc_config(sc, PUC_CFG_GET_TYPE, port, res);
2288 if (error != 0)
2289 return (error);
2290 *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14;
2291 return (0);
2292 default:
2293 break;
2294 }
2295 return (ENXIO);
2296 }
2297
2298 static int
puc_config_titan(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)2299 puc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd,
2300 int port, intptr_t *res)
2301 {
2302
2303 switch (cmd) {
2304 case PUC_CFG_GET_OFS:
2305 *res = (port < 3) ? 0 : (port - 2) << 3;
2306 return (0);
2307 case PUC_CFG_GET_RID:
2308 *res = 0x14 + ((port >= 2) ? 0x0c : port << 2);
2309 return (0);
2310 default:
2311 break;
2312 }
2313 return (ENXIO);
2314 }
2315
2316 static int
puc_config_systembase(struct puc_softc * sc __unused,enum puc_cfg_cmd cmd,int port,intptr_t * res)2317 puc_config_systembase(struct puc_softc *sc __unused,
2318 enum puc_cfg_cmd cmd, int port, intptr_t *res)
2319 {
2320 struct puc_bar *bar;
2321
2322 switch (cmd) {
2323 case PUC_CFG_SETUP:
2324 bar = puc_get_bar(sc, 0x14);
2325 if (bar == NULL)
2326 return (ENXIO);
2327
2328 /*
2329 * The Systembase SB16C1058 (and probably other devices
2330 * based on the SB16C1050 UART core) require poking a
2331 * register in the *other* RID to turn on interrupts.
2332 */
2333 bus_write_1(bar->b_res, /* OPT_IMRREG0 */ 0xc, 0xff);
2334 return (0);
2335 default:
2336 break;
2337 }
2338 return (ENXIO);
2339 }
2340