1 /*
2 * Copyright (c) 2022 Jared McNeill <jmcneill@invisible.ca>
3 * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
4 * Copyright (c) 2024 Jari Sihvola <jsihv@gmx.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /*
30 * Motorcomm YT8511C/YT8511H/YT8531
31 * Integrated 10/100/1000 Gigabit Ethernet phy
32 */
33
34 #include "opt_platform.h"
35
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/errno.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43
44 #include <net/if.h>
45 #include <net/if_media.h>
46
47 #include <dev/mii/mii.h>
48 #include <dev/mii/miivar.h>
49 #ifdef FDT
50 #include <dev/mii/mii_fdt.h>
51 #endif
52
53 #include "miidevs.h"
54 #include "miibus_if.h"
55
56 #define MCOMMPHY_YT8511_OUI 0x000000
57 #define MCOMMPHY_YT8511_MODEL 0x10
58 #define MCOMMPHY_YT8511_REV 0x0a
59
60 #define MCOMMPHY_YT8531_MODEL 0x11
61
62 #define EXT_REG_ADDR 0x1e
63 #define EXT_REG_DATA 0x1f
64
65 /* Extended registers */
66 #define PHY_CLOCK_GATING_REG 0x0c
67 #define RX_CLK_DELAY_EN 0x0001
68 #define CLK_25M_SEL 0x0006
69 #define CLK_25M_SEL_125M 3
70 #define TX_CLK_DELAY_SEL 0x00f0
71 #define PHY_SLEEP_CONTROL1_REG 0x27
72 #define PLLON_IN_SLP 0x4000
73
74 /* Registers and values for YT8531 */
75 #define YT8531_CHIP_CONFIG 0xa001
76 #define RXC_DLY_EN (1 << 8)
77
78 #define YT8531_PAD_DRSTR_CFG 0xa010
79 #define PAD_RXC_MASK 0x7
80 #define PAD_RXC_SHIFT 13
81 #define JH7110_RGMII_RXC_STRENGTH 6
82
83 #define YT8531_RGMII_CONFIG1 0xa003
84 #define RX_DELAY_SEL_SHIFT 10
85 #define RX_DELAY_SEL_MASK 0xf
86 #define RXC_DLY_THRESH 2250
87 #define RXC_DLY_ADDON 1900
88 #define TX_DELAY_SEL_FE_MASK 0xf
89 #define TX_DELAY_SEL_FE_SHIFT 4
90 #define TX_DELAY_SEL_MASK 0xf
91 #define TX_DELAY_SEL_SHIFT 0
92 #define TX_CLK_SEL (1 << 14)
93 #define INTERNAL_DLY_DIV 150
94
95 #define YT8531_SYNCE_CFG 0xa012
96 #define EN_SYNC_E (1 << 6)
97
98 #define LOWEST_SET_BIT(mask) ((((mask) - 1) & (mask)) ^ (mask))
99 #define SHIFTIN(x, mask) ((x) * LOWEST_SET_BIT(mask))
100
101 static const struct mii_phydesc mcommphys[] = {
102 MII_PHY_DESC(MOTORCOMM, YT8511),
103 MII_PHY_DESC(MOTORCOMM2, YT8531),
104 MII_PHY_END
105 };
106
107 struct mcommphy_softc {
108 mii_softc_t mii_sc;
109 device_t dev;
110 u_int rx_delay_ps;
111 u_int tx_delay_ps;
112 bool tx_10_inv;
113 bool tx_100_inv;
114 bool tx_1000_inv;
115 };
116
117 static void mcommphy_yt8531_speed_adjustment(struct mii_softc *sc);
118
119 static int
mcommphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)120 mcommphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
121 {
122 switch (cmd) {
123 case MII_POLLSTAT:
124 break;
125
126 case MII_MEDIACHG:
127 mii_phy_setmedia(sc);
128 break;
129
130 case MII_TICK:
131 if (mii_phy_tick(sc) == EJUSTRETURN)
132 return (0);
133 break;
134 }
135
136 /* Update the media status. */
137 PHY_STATUS(sc);
138
139 /*
140 * For the needs of JH7110 which has two Ethernet devices with
141 * different TX inverted configuration depending on speed used
142 */
143 if (sc->mii_mpd_model == MCOMMPHY_YT8531_MODEL &&
144 (sc->mii_media_active != mii->mii_media_active ||
145 sc->mii_media_status != mii->mii_media_status)) {
146 mcommphy_yt8531_speed_adjustment(sc);
147 }
148
149 /* Callback if something changed. */
150 mii_phy_update(sc, cmd);
151
152 return (0);
153 }
154
155 static const struct mii_phy_funcs mcommphy_funcs = {
156 mcommphy_service,
157 ukphy_status,
158 mii_phy_reset
159 };
160
161 static int
mcommphy_probe(device_t dev)162 mcommphy_probe(device_t dev)
163 {
164 struct mii_attach_args *ma = device_get_ivars(dev);
165
166 /*
167 * The YT8511C reports an OUI of 0. Best we can do here is to match
168 * exactly the contents of the PHY identification registers.
169 */
170 if (MII_OUI(ma->mii_id1, ma->mii_id2) == MCOMMPHY_YT8511_OUI &&
171 MII_MODEL(ma->mii_id2) == MCOMMPHY_YT8511_MODEL &&
172 MII_REV(ma->mii_id2) == MCOMMPHY_YT8511_REV) {
173 device_set_desc(dev, "Motorcomm YT8511 media interface");
174 return (BUS_PROBE_DEFAULT);
175 }
176
177 /* YT8531 follows a conventional procedure */
178 return (mii_phy_dev_probe(dev, mcommphys, BUS_PROBE_DEFAULT));
179 }
180
181 static void
mcommphy_yt8511_setup(struct mii_softc * sc)182 mcommphy_yt8511_setup(struct mii_softc *sc)
183 {
184 uint16_t oldaddr, data;
185
186 oldaddr = PHY_READ(sc, EXT_REG_ADDR);
187
188 PHY_WRITE(sc, EXT_REG_ADDR, PHY_CLOCK_GATING_REG);
189 data = PHY_READ(sc, EXT_REG_DATA);
190 data &= ~CLK_25M_SEL;
191 data |= SHIFTIN(CLK_25M_SEL_125M, CLK_25M_SEL);
192 if (sc->mii_flags & MIIF_RX_DELAY) {
193 data |= RX_CLK_DELAY_EN;
194 } else {
195 data &= ~RX_CLK_DELAY_EN;
196 }
197 data &= ~TX_CLK_DELAY_SEL;
198 if (sc->mii_flags & MIIF_TX_DELAY) {
199 data |= SHIFTIN(0xf, TX_CLK_DELAY_SEL);
200 } else {
201 data |= SHIFTIN(0x2, TX_CLK_DELAY_SEL);
202 }
203 PHY_WRITE(sc, EXT_REG_DATA, data);
204
205 PHY_WRITE(sc, EXT_REG_ADDR, PHY_SLEEP_CONTROL1_REG);
206 data = PHY_READ(sc, EXT_REG_DATA);
207 data |= PLLON_IN_SLP;
208 PHY_WRITE(sc, EXT_REG_DATA, data);
209
210 PHY_WRITE(sc, EXT_REG_ADDR, oldaddr);
211 }
212
213 static void
mcommphy_yt8531_speed_adjustment(struct mii_softc * sc)214 mcommphy_yt8531_speed_adjustment(struct mii_softc *sc)
215 {
216 struct mcommphy_softc *mcomm_sc = (struct mcommphy_softc *)sc;
217 struct mii_data *mii = sc->mii_pdata;
218 bool tx_clk_inv = false;
219 uint16_t reg, oldaddr;
220
221 switch (IFM_SUBTYPE(mii->mii_media_active)) {
222 case IFM_1000_T:
223 tx_clk_inv = mcomm_sc->tx_1000_inv;
224 break;
225 case IFM_100_T:
226 tx_clk_inv = mcomm_sc->tx_100_inv;
227 break;
228 case IFM_10_T:
229 tx_clk_inv = mcomm_sc->tx_10_inv;
230 break;
231 }
232
233 oldaddr = PHY_READ(sc, EXT_REG_ADDR);
234
235 PHY_WRITE(sc, EXT_REG_ADDR, YT8531_RGMII_CONFIG1);
236 reg = PHY_READ(sc, EXT_REG_DATA);
237 if (tx_clk_inv)
238 reg |= TX_CLK_SEL;
239 else
240 reg &= ~TX_CLK_SEL;
241 PHY_WRITE(sc, EXT_REG_DATA, reg);
242
243 PHY_WRITE(sc, EXT_REG_ADDR, oldaddr);
244 }
245
246 #ifdef FDT
247 static int
mcommphy_yt8531_setup_delay(struct mii_softc * sc)248 mcommphy_yt8531_setup_delay(struct mii_softc *sc)
249 {
250 struct mcommphy_softc *mcomm_sc = (struct mcommphy_softc *)sc;
251 uint16_t reg, oldaddr;
252 int rx_delay = 0, tx_delay = 0;
253 bool rxc_dly_en_off = false;
254
255 if (mcomm_sc->rx_delay_ps > RXC_DLY_THRESH) {
256 rx_delay = (mcomm_sc->rx_delay_ps - RXC_DLY_ADDON) /
257 INTERNAL_DLY_DIV;
258 } else if (mcomm_sc->rx_delay_ps > 0) {
259 rx_delay = mcomm_sc->rx_delay_ps / INTERNAL_DLY_DIV;
260 rxc_dly_en_off = true;
261 }
262
263 if (mcomm_sc->tx_delay_ps > 0) {
264 tx_delay = mcomm_sc->tx_delay_ps / INTERNAL_DLY_DIV;
265 }
266
267 oldaddr = PHY_READ(sc, EXT_REG_ADDR);
268
269 /* Modifying Chip Config register */
270 PHY_WRITE(sc, EXT_REG_ADDR, YT8531_CHIP_CONFIG);
271 reg = PHY_READ(sc, EXT_REG_DATA);
272 if (rxc_dly_en_off)
273 reg &= ~(RXC_DLY_EN);
274 PHY_WRITE(sc, EXT_REG_DATA, reg);
275
276 /* Modifying RGMII Config1 register */
277 PHY_WRITE(sc, EXT_REG_ADDR, YT8531_RGMII_CONFIG1);
278 reg = PHY_READ(sc, EXT_REG_DATA);
279 reg &= ~(RX_DELAY_SEL_MASK << RX_DELAY_SEL_SHIFT);
280 reg |= rx_delay << RX_DELAY_SEL_SHIFT;
281 reg &= ~(TX_DELAY_SEL_MASK << TX_DELAY_SEL_SHIFT);
282 reg |= tx_delay << TX_DELAY_SEL_SHIFT;
283 PHY_WRITE(sc, EXT_REG_DATA, reg);
284
285 PHY_WRITE(sc, EXT_REG_ADDR, oldaddr);
286
287 return (0);
288 }
289 #endif
290
291 static int
mcommphy_yt8531_setup(struct mii_softc * sc)292 mcommphy_yt8531_setup(struct mii_softc *sc)
293 {
294 uint16_t reg, oldaddr;
295
296 oldaddr = PHY_READ(sc, EXT_REG_ADDR);
297
298 /* Modifying Pad Drive Strength register */
299 PHY_WRITE(sc, EXT_REG_ADDR, YT8531_PAD_DRSTR_CFG);
300 reg = PHY_READ(sc, EXT_REG_DATA);
301 reg &= ~(PAD_RXC_MASK << PAD_RXC_SHIFT);
302 reg |= (JH7110_RGMII_RXC_STRENGTH << PAD_RXC_SHIFT);
303 PHY_WRITE(sc, EXT_REG_DATA, reg);
304
305 /* Modifying SyncE Config register */
306 PHY_WRITE(sc, EXT_REG_ADDR, YT8531_SYNCE_CFG);
307 reg = PHY_READ(sc, EXT_REG_DATA);
308 reg &= ~(EN_SYNC_E);
309 PHY_WRITE(sc, EXT_REG_DATA, reg);
310
311 PHY_WRITE(sc, EXT_REG_ADDR, oldaddr);
312
313 #ifdef FDT
314 if (mcommphy_yt8531_setup_delay(sc) != 0)
315 return (ENXIO);
316 #endif
317
318 return (0);
319 }
320
321 #ifdef FDT
322 static void
mcommphy_fdt_get_config(struct mcommphy_softc * sc)323 mcommphy_fdt_get_config(struct mcommphy_softc *sc)
324 {
325 mii_fdt_phy_config_t *cfg;
326 pcell_t val;
327
328 cfg = mii_fdt_get_config(sc->dev);
329
330 if (OF_hasprop(cfg->phynode, "motorcomm,tx-clk-10-inverted"))
331 sc->tx_10_inv = true;
332 if (OF_hasprop(cfg->phynode, "motorcomm,tx-clk-100-inverted"))
333 sc->tx_100_inv = true;
334 if (OF_hasprop(cfg->phynode, "motorcomm,tx-clk-1000-inverted"))
335 sc->tx_1000_inv = true;
336
337 /* Grab raw delay values (picoseconds); adjusted later. */
338 if (OF_getencprop(cfg->phynode, "rx-internal-delay-ps", &val,
339 sizeof(val)) > 0) {
340 sc->rx_delay_ps = val;
341 }
342 if (OF_getencprop(cfg->phynode, "tx-internal-delay-ps", &val,
343 sizeof(val)) > 0) {
344 sc->tx_delay_ps = val;
345 }
346
347 mii_fdt_free_config(cfg);
348 }
349 #endif
350
351 static int
mcommphy_attach(device_t dev)352 mcommphy_attach(device_t dev)
353 {
354 struct mcommphy_softc *mcomm_sc = device_get_softc(dev);
355 mii_softc_t *mii_sc = &mcomm_sc->mii_sc;
356 int ret = 0;
357
358 mcomm_sc->dev = dev;
359
360 #ifdef FDT
361 mcommphy_fdt_get_config(mcomm_sc);
362 #endif
363
364 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &mcommphy_funcs, 0);
365
366 PHY_RESET(mii_sc);
367
368 if (mii_sc->mii_mpd_model == MCOMMPHY_YT8511_MODEL)
369 mcommphy_yt8511_setup(mii_sc);
370 else if (mii_sc->mii_mpd_model == MCOMMPHY_YT8531_MODEL)
371 ret = mcommphy_yt8531_setup(mii_sc);
372 else {
373 device_printf(dev, "no PHY model detected\n");
374 return (ENXIO);
375 }
376 if (ret) {
377 device_printf(dev, "PHY setup failed, error: %d\n", ret);
378 return (ret);
379 }
380
381 mii_sc->mii_capabilities = PHY_READ(mii_sc, MII_BMSR) &
382 mii_sc->mii_capmask;
383 if (mii_sc->mii_capabilities & BMSR_EXTSTAT)
384 mii_sc->mii_extcapabilities = PHY_READ(mii_sc, MII_EXTSR);
385 device_printf(dev, " ");
386 mii_phy_add_media(mii_sc);
387 printf("\n");
388
389 MIIBUS_MEDIAINIT(mii_sc->mii_dev);
390
391 return (0);
392 }
393
394 static device_method_t mcommphy_methods[] = {
395 /* device interface */
396 DEVMETHOD(device_probe, mcommphy_probe),
397 DEVMETHOD(device_attach, mcommphy_attach),
398 DEVMETHOD(device_detach, mii_phy_detach),
399 DEVMETHOD(device_shutdown, bus_generic_shutdown),
400 DEVMETHOD_END
401 };
402
403 static driver_t mcommphy_driver = {
404 "mcommphy",
405 mcommphy_methods,
406 sizeof(struct mcommphy_softc)
407 };
408
409 DRIVER_MODULE(mcommphy, miibus, mcommphy_driver, 0, 0);
410