1 /*-
2 * Copyright (c) 2016 Hiroki Mori
3 * Copyright (c) 2013 Luiz Otavio O Souza.
4 * Copyright (c) 2011-2012 Stefan Bethke.
5 * Copyright (c) 2012 Adrian Chadd.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * This is Micrel KSZ8995MA driver code. KSZ8995MA use SPI bus on control.
32 * This code development on @SRCHACK's ksz8995ma board and FON2100 with
33 * gpiospi.
34 * etherswitchcfg command port option support addtag, ingress, striptag,
35 * dropuntagged.
36 */
37
38 #include <sys/param.h>
39 #include <sys/bus.h>
40 #include <sys/errno.h>
41 #include <sys/kernel.h>
42 #include <sys/lock.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/mutex.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
50
51 #include <net/if.h>
52 #include <net/if_var.h>
53 #include <net/ethernet.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56
57 #include <machine/bus.h>
58 #include <dev/mii/mii.h>
59 #include <dev/mii/miivar.h>
60
61 #include <dev/etherswitch/etherswitch.h>
62
63 #include <dev/spibus/spi.h>
64
65 #include "spibus_if.h"
66 #include "miibus_if.h"
67 #include "etherswitch_if.h"
68
69 #define KSZ8995MA_SPI_READ 0x03
70 #define KSZ8995MA_SPI_WRITE 0x02
71
72 #define KSZ8995MA_CID0 0x00
73 #define KSZ8995MA_CID1 0x01
74
75 #define KSZ8995MA_GC0 0x02
76 #define KSZ8995MA_GC1 0x03
77 #define KSZ8995MA_GC2 0x04
78 #define KSZ8995MA_GC3 0x05
79
80 #define KSZ8995MA_PORT_SIZE 0x10
81
82 #define KSZ8995MA_PC0_BASE 0x10
83 #define KSZ8995MA_PC1_BASE 0x11
84 #define KSZ8995MA_PC2_BASE 0x12
85 #define KSZ8995MA_PC3_BASE 0x13
86 #define KSZ8995MA_PC4_BASE 0x14
87 #define KSZ8995MA_PC5_BASE 0x15
88 #define KSZ8995MA_PC6_BASE 0x16
89 #define KSZ8995MA_PC7_BASE 0x17
90 #define KSZ8995MA_PC8_BASE 0x18
91 #define KSZ8995MA_PC9_BASE 0x19
92 #define KSZ8995MA_PC10_BASE 0x1a
93 #define KSZ8995MA_PC11_BASE 0x1b
94 #define KSZ8995MA_PC12_BASE 0x1c
95 #define KSZ8995MA_PC13_BASE 0x1d
96
97 #define KSZ8995MA_PS0_BASE 0x1e
98
99 #define KSZ8995MA_PC14_BASE 0x1f
100
101 #define KSZ8995MA_IAC0 0x6e
102 #define KSZ8995MA_IAC1 0x6f
103 #define KSZ8995MA_IDR8 0x70
104 #define KSZ8995MA_IDR7 0x71
105 #define KSZ8995MA_IDR6 0x72
106 #define KSZ8995MA_IDR5 0x73
107 #define KSZ8995MA_IDR4 0x74
108 #define KSZ8995MA_IDR3 0x75
109 #define KSZ8995MA_IDR2 0x76
110 #define KSZ8995MA_IDR1 0x77
111 #define KSZ8995MA_IDR0 0x78
112
113 #define KSZ8995MA_FAMILI_ID 0x95
114 #define KSZ8995MA_CHIP_ID 0x00
115 #define KSZ8995MA_CHIP_ID_MASK 0xf0
116 #define KSZ8995MA_START 0x01
117 #define KSZ8995MA_VLAN_ENABLE 0x80
118 #define KSZ8995MA_TAG_INS 0x04
119 #define KSZ8995MA_TAG_RM 0x02
120 #define KSZ8995MA_INGR_FILT 0x40
121 #define KSZ8995MA_DROP_NONPVID 0x20
122
123 #define KSZ8995MA_PDOWN 0x08
124 #define KSZ8995MA_STARTNEG 0x20
125
126 #define KSZ8995MA_MII_STAT 0x7808
127 #define KSZ8995MA_MII_PHYID_H 0x0022
128 #define KSZ8995MA_MII_PHYID_L 0x1450
129 #define KSZ8995MA_MII_AA 0x0401
130
131 #define KSZ8995MA_VLAN_TABLE_VALID 0x20
132 #define KSZ8995MA_VLAN_TABLE_READ 0x14
133 #define KSZ8995MA_VLAN_TABLE_WRITE 0x04
134
135 #define KSZ8995MA_MAX_PORT 5
136
137 MALLOC_DECLARE(M_KSZ8995MA);
138 MALLOC_DEFINE(M_KSZ8995MA, "ksz8995ma", "ksz8995ma data structures");
139
140 struct ksz8995ma_softc {
141 struct mtx sc_mtx; /* serialize access to softc */
142 device_t sc_dev;
143 int vlan_mode;
144 int media; /* cpu port media */
145 int cpuport; /* which PHY is connected to the CPU */
146 int phymask; /* PHYs we manage */
147 int numports; /* number of ports */
148 int ifpport[KSZ8995MA_MAX_PORT];
149 int *portphy;
150 char **ifname;
151 device_t **miibus;
152 if_t *ifp;
153 struct callout callout_tick;
154 etherswitch_info_t info;
155 };
156
157 #define KSZ8995MA_LOCK(_sc) \
158 mtx_lock(&(_sc)->sc_mtx)
159 #define KSZ8995MA_UNLOCK(_sc) \
160 mtx_unlock(&(_sc)->sc_mtx)
161 #define KSZ8995MA_LOCK_ASSERT(_sc, _what) \
162 mtx_assert(&(_sc)->sc_mtx, (_what))
163 #define KSZ8995MA_TRYLOCK(_sc) \
164 mtx_trylock(&(_sc)->sc_mtx)
165
166 #if defined(DEBUG)
167 #define DPRINTF(dev, args...) device_printf(dev, args)
168 #else
169 #define DPRINTF(dev, args...)
170 #endif
171
172 static inline int ksz8995ma_portforphy(struct ksz8995ma_softc *, int);
173 static void ksz8995ma_tick(void *);
174 static int ksz8995ma_ifmedia_upd(if_t);
175 static void ksz8995ma_ifmedia_sts(if_t, struct ifmediareq *);
176 static int ksz8995ma_readreg(device_t dev, int addr);
177 static int ksz8995ma_writereg(device_t dev, int addr, int value);
178 static void ksz8995ma_portvlanreset(device_t dev);
179
180 static int
ksz8995ma_probe(device_t dev)181 ksz8995ma_probe(device_t dev)
182 {
183 int id0, id1;
184 struct ksz8995ma_softc *sc;
185
186 sc = device_get_softc(dev);
187 bzero(sc, sizeof(*sc));
188
189 id0 = ksz8995ma_readreg(dev, KSZ8995MA_CID0);
190 id1 = ksz8995ma_readreg(dev, KSZ8995MA_CID1);
191 if (bootverbose)
192 device_printf(dev,"Chip Identifier Register %x %x\n", id0, id1);
193
194 /* check Product Code */
195 if (id0 != KSZ8995MA_FAMILI_ID || (id1 & KSZ8995MA_CHIP_ID_MASK) !=
196 KSZ8995MA_CHIP_ID) {
197 return (ENXIO);
198 }
199
200 device_set_desc(dev, "Micrel KSZ8995MA SPI switch driver");
201 return (BUS_PROBE_DEFAULT);
202 }
203
204 static int
ksz8995ma_attach_phys(struct ksz8995ma_softc * sc)205 ksz8995ma_attach_phys(struct ksz8995ma_softc *sc)
206 {
207 int phy, port, err;
208 char name[IFNAMSIZ];
209
210 port = 0;
211 err = 0;
212 /* PHYs need an interface, so we generate a dummy one */
213 snprintf(name, IFNAMSIZ, "%sport", device_get_nameunit(sc->sc_dev));
214 for (phy = 0; phy < sc->numports; phy++) {
215 if (phy == sc->cpuport)
216 continue;
217 if (((1 << phy) & sc->phymask) == 0)
218 continue;
219 sc->ifpport[phy] = port;
220 sc->portphy[port] = phy;
221 sc->ifp[port] = if_alloc(IFT_ETHER);
222 sc->ifp[port]->if_softc = sc;
223 sc->ifp[port]->if_flags |= IFF_UP | IFF_BROADCAST |
224 IFF_DRV_RUNNING | IFF_SIMPLEX;
225 if_initname(sc->ifp[port], name, port);
226 sc->miibus[port] = malloc(sizeof(device_t), M_KSZ8995MA,
227 M_WAITOK | M_ZERO);
228 err = mii_attach(sc->sc_dev, sc->miibus[port], sc->ifp[port],
229 ksz8995ma_ifmedia_upd, ksz8995ma_ifmedia_sts, \
230 BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
231 DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n",
232 device_get_nameunit(*sc->miibus[port]),
233 sc->ifp[port]->if_xname);
234 if (err != 0) {
235 device_printf(sc->sc_dev,
236 "attaching PHY %d failed\n",
237 phy);
238 goto failed;
239 }
240 ++port;
241 }
242 sc->info.es_nports = port;
243 if (sc->cpuport != -1) {
244 /* cpu port is MAC5 on ksz8995ma */
245 sc->ifpport[sc->cpuport] = port;
246 sc->portphy[port] = sc->cpuport;
247 ++sc->info.es_nports;
248 }
249
250 return (0);
251
252 failed:
253 for (phy = 0; phy < sc->numports; phy++) {
254 if (((1 << phy) & sc->phymask) == 0)
255 continue;
256 port = ksz8995ma_portforphy(sc, phy);
257 if (sc->miibus[port] != NULL)
258 device_delete_child(sc->sc_dev, (*sc->miibus[port]));
259 if (sc->ifp[port] != NULL)
260 if_free(sc->ifp[port]);
261 if (sc->ifname[port] != NULL)
262 free(sc->ifname[port], M_KSZ8995MA);
263 if (sc->miibus[port] != NULL)
264 free(sc->miibus[port], M_KSZ8995MA);
265 }
266 return (err);
267 }
268
269 static int
ksz8995ma_attach(device_t dev)270 ksz8995ma_attach(device_t dev)
271 {
272 struct ksz8995ma_softc *sc;
273 int err, reg;
274
275 err = 0;
276 sc = device_get_softc(dev);
277
278 sc->sc_dev = dev;
279 mtx_init(&sc->sc_mtx, "ksz8995ma", NULL, MTX_DEF);
280 strlcpy(sc->info.es_name, device_get_desc(dev),
281 sizeof(sc->info.es_name));
282
283 /* KSZ8995MA Defaults */
284 sc->numports = KSZ8995MA_MAX_PORT;
285 sc->phymask = (1 << (KSZ8995MA_MAX_PORT + 1)) - 1;
286 sc->cpuport = -1;
287 sc->media = 100;
288
289 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
290 "cpuport", &sc->cpuport);
291
292 sc->info.es_nvlangroups = 16;
293 sc->info.es_vlan_caps = ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOT1Q;
294
295 sc->ifp = malloc(sizeof(if_t) * sc->numports, M_KSZ8995MA,
296 M_WAITOK | M_ZERO);
297 sc->ifname = malloc(sizeof(char *) * sc->numports, M_KSZ8995MA,
298 M_WAITOK | M_ZERO);
299 sc->miibus = malloc(sizeof(device_t *) * sc->numports, M_KSZ8995MA,
300 M_WAITOK | M_ZERO);
301 sc->portphy = malloc(sizeof(int) * sc->numports, M_KSZ8995MA,
302 M_WAITOK | M_ZERO);
303
304 /*
305 * Attach the PHYs and complete the bus enumeration.
306 */
307 err = ksz8995ma_attach_phys(sc);
308 if (err != 0)
309 goto failed;
310
311 bus_identify_children(dev);
312 bus_enumerate_hinted_children(dev);
313 bus_attach_children(dev);
314
315 callout_init(&sc->callout_tick, 0);
316
317 ksz8995ma_tick(sc);
318
319 /* start switch */
320 sc->vlan_mode = 0;
321 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);
322 ksz8995ma_writereg(dev, KSZ8995MA_GC3,
323 reg & ~KSZ8995MA_VLAN_ENABLE);
324 ksz8995ma_portvlanreset(dev);
325 ksz8995ma_writereg(dev, KSZ8995MA_CID1, KSZ8995MA_START);
326
327 return (0);
328
329 failed:
330 free(sc->portphy, M_KSZ8995MA);
331 free(sc->miibus, M_KSZ8995MA);
332 free(sc->ifname, M_KSZ8995MA);
333 free(sc->ifp, M_KSZ8995MA);
334
335 return (err);
336 }
337
338 static int
ksz8995ma_detach(device_t dev)339 ksz8995ma_detach(device_t dev)
340 {
341 struct ksz8995ma_softc *sc;
342 int error, i, port;
343
344 error = bus_generic_detach(dev);
345 if (error != 0)
346 return (error);
347
348 sc = device_get_softc(dev);
349
350 callout_drain(&sc->callout_tick);
351
352 for (i = 0; i < KSZ8995MA_MAX_PORT; i++) {
353 if (((1 << i) & sc->phymask) == 0)
354 continue;
355 port = ksz8995ma_portforphy(sc, i);
356 if (sc->ifp[port] != NULL)
357 if_free(sc->ifp[port]);
358 free(sc->ifname[port], M_KSZ8995MA);
359 free(sc->miibus[port], M_KSZ8995MA);
360 }
361
362 free(sc->portphy, M_KSZ8995MA);
363 free(sc->miibus, M_KSZ8995MA);
364 free(sc->ifname, M_KSZ8995MA);
365 free(sc->ifp, M_KSZ8995MA);
366
367 mtx_destroy(&sc->sc_mtx);
368
369 return (0);
370 }
371
372 /*
373 * Convert PHY number to port number.
374 */
375 static inline int
ksz8995ma_portforphy(struct ksz8995ma_softc * sc,int phy)376 ksz8995ma_portforphy(struct ksz8995ma_softc *sc, int phy)
377 {
378
379 return (sc->ifpport[phy]);
380 }
381
382 static inline struct mii_data *
ksz8995ma_miiforport(struct ksz8995ma_softc * sc,int port)383 ksz8995ma_miiforport(struct ksz8995ma_softc *sc, int port)
384 {
385
386 if (port < 0 || port > sc->numports)
387 return (NULL);
388 if (port == sc->cpuport)
389 return (NULL);
390 return (device_get_softc(*sc->miibus[port]));
391 }
392
393 static inline if_t
ksz8995ma_ifpforport(struct ksz8995ma_softc * sc,int port)394 ksz8995ma_ifpforport(struct ksz8995ma_softc *sc, int port)
395 {
396
397 if (port < 0 || port > sc->numports)
398 return (NULL);
399 return (sc->ifp[port]);
400 }
401
402 /*
403 * Poll the status for all PHYs.
404 */
405 static void
ksz8995ma_miipollstat(struct ksz8995ma_softc * sc)406 ksz8995ma_miipollstat(struct ksz8995ma_softc *sc)
407 {
408 int i, port;
409 struct mii_data *mii;
410 struct mii_softc *miisc;
411
412 KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED);
413
414 for (i = 0; i < KSZ8995MA_MAX_PORT; i++) {
415 if (i == sc->cpuport)
416 continue;
417 if (((1 << i) & sc->phymask) == 0)
418 continue;
419 port = ksz8995ma_portforphy(sc, i);
420 if ((*sc->miibus[port]) == NULL)
421 continue;
422 mii = device_get_softc(*sc->miibus[port]);
423 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
424 if (IFM_INST(mii->mii_media.ifm_cur->ifm_media) !=
425 miisc->mii_inst)
426 continue;
427 ukphy_status(miisc);
428 mii_phy_update(miisc, MII_POLLSTAT);
429 }
430 }
431 }
432
433 static void
ksz8995ma_tick(void * arg)434 ksz8995ma_tick(void *arg)
435 {
436 struct ksz8995ma_softc *sc;
437
438 sc = arg;
439
440 ksz8995ma_miipollstat(sc);
441 callout_reset(&sc->callout_tick, hz, ksz8995ma_tick, sc);
442 }
443
444 static void
ksz8995ma_lock(device_t dev)445 ksz8995ma_lock(device_t dev)
446 {
447 struct ksz8995ma_softc *sc;
448
449 sc = device_get_softc(dev);
450
451 KSZ8995MA_LOCK_ASSERT(sc, MA_NOTOWNED);
452 KSZ8995MA_LOCK(sc);
453 }
454
455 static void
ksz8995ma_unlock(device_t dev)456 ksz8995ma_unlock(device_t dev)
457 {
458 struct ksz8995ma_softc *sc;
459
460 sc = device_get_softc(dev);
461
462 KSZ8995MA_LOCK_ASSERT(sc, MA_OWNED);
463 KSZ8995MA_UNLOCK(sc);
464 }
465
466 static etherswitch_info_t *
ksz8995ma_getinfo(device_t dev)467 ksz8995ma_getinfo(device_t dev)
468 {
469 struct ksz8995ma_softc *sc;
470
471 sc = device_get_softc(dev);
472
473 return (&sc->info);
474 }
475
476 static int
ksz8995ma_getport(device_t dev,etherswitch_port_t * p)477 ksz8995ma_getport(device_t dev, etherswitch_port_t *p)
478 {
479 struct ksz8995ma_softc *sc;
480 struct mii_data *mii;
481 struct ifmediareq *ifmr;
482 int phy, err;
483 int tag1, tag2, portreg;
484
485 sc = device_get_softc(dev);
486 ifmr = &p->es_ifmr;
487
488 if (p->es_port < 0 || p->es_port >= sc->numports)
489 return (ENXIO);
490
491 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
492 tag1 = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE +
493 KSZ8995MA_PORT_SIZE * p->es_port);
494 tag2 = ksz8995ma_readreg(dev, KSZ8995MA_PC4_BASE +
495 KSZ8995MA_PORT_SIZE * p->es_port);
496 p->es_pvid = (tag1 & 0x0f) << 8 | tag2;
497
498 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE +
499 KSZ8995MA_PORT_SIZE * p->es_port);
500 if (portreg & KSZ8995MA_TAG_INS)
501 p->es_flags |= ETHERSWITCH_PORT_ADDTAG;
502 if (portreg & KSZ8995MA_TAG_RM)
503 p->es_flags |= ETHERSWITCH_PORT_STRIPTAG;
504
505 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE +
506 KSZ8995MA_PORT_SIZE * p->es_port);
507 if (portreg & KSZ8995MA_DROP_NONPVID)
508 p->es_flags |= ETHERSWITCH_PORT_DROPUNTAGGED;
509 if (portreg & KSZ8995MA_INGR_FILT)
510 p->es_flags |= ETHERSWITCH_PORT_INGRESS;
511 }
512
513 phy = sc->portphy[p->es_port];
514 mii = ksz8995ma_miiforport(sc, p->es_port);
515 if (sc->cpuport != -1 && phy == sc->cpuport) {
516 /* fill in fixed values for CPU port */
517 p->es_flags |= ETHERSWITCH_PORT_CPU;
518 ifmr->ifm_count = 0;
519 if (sc->media == 100)
520 ifmr->ifm_current = ifmr->ifm_active =
521 IFM_ETHER | IFM_100_TX | IFM_FDX;
522 else
523 ifmr->ifm_current = ifmr->ifm_active =
524 IFM_ETHER | IFM_1000_T | IFM_FDX;
525 ifmr->ifm_mask = 0;
526 ifmr->ifm_status = IFM_ACTIVE | IFM_AVALID;
527 } else if (mii != NULL) {
528 err = ifmedia_ioctl(mii->mii_ifp, &p->es_ifr,
529 &mii->mii_media, SIOCGIFMEDIA);
530 if (err)
531 return (err);
532 } else {
533 return (ENXIO);
534 }
535
536 return (0);
537 }
538
539 static int
ksz8995ma_setport(device_t dev,etherswitch_port_t * p)540 ksz8995ma_setport(device_t dev, etherswitch_port_t *p)
541 {
542 struct ksz8995ma_softc *sc;
543 struct mii_data *mii;
544 struct ifmedia *ifm;
545 if_t ifp;
546 int phy, err;
547 int portreg;
548
549 sc = device_get_softc(dev);
550
551 if (p->es_port < 0 || p->es_port >= sc->numports)
552 return (ENXIO);
553
554 if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
555 ksz8995ma_writereg(dev, KSZ8995MA_PC4_BASE +
556 KSZ8995MA_PORT_SIZE * p->es_port, p->es_pvid & 0xff);
557 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC3_BASE +
558 KSZ8995MA_PORT_SIZE * p->es_port);
559 ksz8995ma_writereg(dev, KSZ8995MA_PC3_BASE +
560 KSZ8995MA_PORT_SIZE * p->es_port,
561 (portreg & 0xf0) | ((p->es_pvid >> 8) & 0x0f));
562
563 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC0_BASE +
564 KSZ8995MA_PORT_SIZE * p->es_port);
565 if (p->es_flags & ETHERSWITCH_PORT_ADDTAG)
566 portreg |= KSZ8995MA_TAG_INS;
567 else
568 portreg &= ~KSZ8995MA_TAG_INS;
569 if (p->es_flags & ETHERSWITCH_PORT_STRIPTAG)
570 portreg |= KSZ8995MA_TAG_RM;
571 else
572 portreg &= ~KSZ8995MA_TAG_RM;
573 ksz8995ma_writereg(dev, KSZ8995MA_PC0_BASE +
574 KSZ8995MA_PORT_SIZE * p->es_port, portreg);
575
576 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC2_BASE +
577 KSZ8995MA_PORT_SIZE * p->es_port);
578 if (p->es_flags & ETHERSWITCH_PORT_DROPUNTAGGED)
579 portreg |= KSZ8995MA_DROP_NONPVID;
580 else
581 portreg &= ~KSZ8995MA_DROP_NONPVID;
582 if (p->es_flags & ETHERSWITCH_PORT_INGRESS)
583 portreg |= KSZ8995MA_INGR_FILT;
584 else
585 portreg &= ~KSZ8995MA_INGR_FILT;
586 ksz8995ma_writereg(dev, KSZ8995MA_PC2_BASE +
587 KSZ8995MA_PORT_SIZE * p->es_port, portreg);
588 }
589
590 phy = sc->portphy[p->es_port];
591 mii = ksz8995ma_miiforport(sc, p->es_port);
592 if (phy != sc->cpuport) {
593 if (mii == NULL)
594 return (ENXIO);
595 ifp = ksz8995ma_ifpforport(sc, p->es_port);
596 ifm = &mii->mii_media;
597 err = ifmedia_ioctl(ifp, &p->es_ifr, ifm, SIOCSIFMEDIA);
598 }
599 return (0);
600 }
601
602 static int
ksz8995ma_getvgroup(device_t dev,etherswitch_vlangroup_t * vg)603 ksz8995ma_getvgroup(device_t dev, etherswitch_vlangroup_t *vg)
604 {
605 int data0, data1, data2;
606 int vlantab;
607 struct ksz8995ma_softc *sc;
608
609 sc = device_get_softc(dev);
610
611 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
612 if (vg->es_vlangroup < sc->numports) {
613 vg->es_vid = ETHERSWITCH_VID_VALID;
614 vg->es_vid |= vg->es_vlangroup;
615 data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE +
616 KSZ8995MA_PORT_SIZE * vg->es_vlangroup);
617 vg->es_member_ports = data0 & 0x1f;
618 vg->es_untagged_ports = vg->es_member_ports;
619 vg->es_fid = 0;
620 } else {
621 vg->es_vid = 0;
622 }
623 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
624 ksz8995ma_writereg(dev, KSZ8995MA_IAC0,
625 KSZ8995MA_VLAN_TABLE_READ);
626 ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup);
627 data2 = ksz8995ma_readreg(dev, KSZ8995MA_IDR2);
628 data1 = ksz8995ma_readreg(dev, KSZ8995MA_IDR1);
629 data0 = ksz8995ma_readreg(dev, KSZ8995MA_IDR0);
630 vlantab = data2 << 16 | data1 << 8 | data0;
631 if (data2 & KSZ8995MA_VLAN_TABLE_VALID) {
632 vg->es_vid = ETHERSWITCH_VID_VALID;
633 vg->es_vid |= vlantab & 0xfff;
634 vg->es_member_ports = (vlantab >> 16) & 0x1f;
635 vg->es_untagged_ports = vg->es_member_ports;
636 vg->es_fid = (vlantab >> 12) & 0x0f;
637 } else {
638 vg->es_fid = 0;
639 }
640 }
641
642 return (0);
643 }
644
645 static int
ksz8995ma_setvgroup(device_t dev,etherswitch_vlangroup_t * vg)646 ksz8995ma_setvgroup(device_t dev, etherswitch_vlangroup_t *vg)
647 {
648 struct ksz8995ma_softc *sc;
649 int data0;
650
651 sc = device_get_softc(dev);
652
653 if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
654 data0 = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE +
655 KSZ8995MA_PORT_SIZE * vg->es_vlangroup);
656 ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE +
657 KSZ8995MA_PORT_SIZE * vg->es_vlangroup,
658 (data0 & 0xe0) | (vg->es_member_ports & 0x1f));
659 } else if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
660 if (vg->es_member_ports != 0) {
661 ksz8995ma_writereg(dev, KSZ8995MA_IDR2,
662 KSZ8995MA_VLAN_TABLE_VALID |
663 (vg->es_member_ports & 0x1f));
664 ksz8995ma_writereg(dev, KSZ8995MA_IDR1,
665 vg->es_fid << 4 | vg->es_vid >> 8);
666 ksz8995ma_writereg(dev, KSZ8995MA_IDR0,
667 vg->es_vid & 0xff);
668 } else {
669 ksz8995ma_writereg(dev, KSZ8995MA_IDR2, 0);
670 ksz8995ma_writereg(dev, KSZ8995MA_IDR1, 0);
671 ksz8995ma_writereg(dev, KSZ8995MA_IDR0, 0);
672 }
673 ksz8995ma_writereg(dev, KSZ8995MA_IAC0,
674 KSZ8995MA_VLAN_TABLE_WRITE);
675 ksz8995ma_writereg(dev, KSZ8995MA_IAC1, vg->es_vlangroup);
676 }
677
678 return (0);
679 }
680
681 static int
ksz8995ma_getconf(device_t dev,etherswitch_conf_t * conf)682 ksz8995ma_getconf(device_t dev, etherswitch_conf_t *conf)
683 {
684 struct ksz8995ma_softc *sc;
685
686 sc = device_get_softc(dev);
687
688 /* Return the VLAN mode. */
689 conf->cmd = ETHERSWITCH_CONF_VLAN_MODE;
690 conf->vlan_mode = sc->vlan_mode;
691
692 return (0);
693 }
694
695 static void
ksz8995ma_portvlanreset(device_t dev)696 ksz8995ma_portvlanreset(device_t dev)
697 {
698 int i, data;
699 struct ksz8995ma_softc *sc;
700
701 sc = device_get_softc(dev);
702
703 for (i = 0; i < sc->numports; ++i) {
704 data = ksz8995ma_readreg(dev, KSZ8995MA_PC1_BASE +
705 KSZ8995MA_PORT_SIZE * i);
706 ksz8995ma_writereg(dev, KSZ8995MA_PC1_BASE +
707 KSZ8995MA_PORT_SIZE * i, (data & 0xe0) | 0x1f);
708 }
709 }
710
711 static int
ksz8995ma_setconf(device_t dev,etherswitch_conf_t * conf)712 ksz8995ma_setconf(device_t dev, etherswitch_conf_t *conf)
713 {
714 int reg;
715 struct ksz8995ma_softc *sc;
716
717 sc = device_get_softc(dev);
718
719 if ((conf->cmd & ETHERSWITCH_CONF_VLAN_MODE) == 0)
720 return (0);
721
722 if (conf->vlan_mode == ETHERSWITCH_VLAN_PORT) {
723 sc->vlan_mode = ETHERSWITCH_VLAN_PORT;
724 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);
725 ksz8995ma_writereg(dev, KSZ8995MA_GC3,
726 reg & ~KSZ8995MA_VLAN_ENABLE);
727 ksz8995ma_portvlanreset(dev);
728 } else if (conf->vlan_mode == ETHERSWITCH_VLAN_DOT1Q) {
729 sc->vlan_mode = ETHERSWITCH_VLAN_DOT1Q;
730 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);
731 ksz8995ma_writereg(dev, KSZ8995MA_GC3,
732 reg | KSZ8995MA_VLAN_ENABLE);
733 } else {
734 sc->vlan_mode = 0;
735 reg = ksz8995ma_readreg(dev, KSZ8995MA_GC3);
736 ksz8995ma_writereg(dev, KSZ8995MA_GC3,
737 reg & ~KSZ8995MA_VLAN_ENABLE);
738 ksz8995ma_portvlanreset(dev);
739 }
740 return (0);
741 }
742
743 static void
ksz8995ma_statchg(device_t dev)744 ksz8995ma_statchg(device_t dev)
745 {
746
747 DPRINTF(dev, "%s\n", __func__);
748 }
749
750 static int
ksz8995ma_ifmedia_upd(if_t ifp)751 ksz8995ma_ifmedia_upd(if_t ifp)
752 {
753 struct ksz8995ma_softc *sc;
754 struct mii_data *mii;
755
756 sc = if_getsoftc(ifp);
757 mii = ksz8995ma_miiforport(sc, if_getdunit(ifp));
758
759 DPRINTF(sc->sc_dev, "%s\n", __func__);
760 if (mii == NULL)
761 return (ENXIO);
762 mii_mediachg(mii);
763 return (0);
764 }
765
766 static void
ksz8995ma_ifmedia_sts(if_t ifp,struct ifmediareq * ifmr)767 ksz8995ma_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
768 {
769 struct ksz8995ma_softc *sc;
770 struct mii_data *mii;
771
772 sc = if_getsoftc(ifp);
773 mii = ksz8995ma_miiforport(sc, if_getdunit(ifp));
774
775 DPRINTF(sc->sc_dev, "%s\n", __func__);
776
777 if (mii == NULL)
778 return;
779 mii_pollstat(mii);
780 ifmr->ifm_active = mii->mii_media_active;
781 ifmr->ifm_status = mii->mii_media_status;
782 }
783
784 static int
ksz8995ma_readphy(device_t dev,int phy,int reg)785 ksz8995ma_readphy(device_t dev, int phy, int reg)
786 {
787 int portreg;
788
789 /*
790 * This is no mdio/mdc connection code.
791 * simulate MIIM Registers via the SPI interface
792 */
793 if (reg == MII_BMSR) {
794 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE +
795 KSZ8995MA_PORT_SIZE * phy);
796 return (KSZ8995MA_MII_STAT |
797 (portreg & 0x20 ? BMSR_LINK : 0x00) |
798 (portreg & 0x40 ? BMSR_ACOMP : 0x00));
799 } else if (reg == MII_PHYIDR1) {
800 return (KSZ8995MA_MII_PHYID_H);
801 } else if (reg == MII_PHYIDR2) {
802 return (KSZ8995MA_MII_PHYID_L);
803 } else if (reg == MII_ANAR) {
804 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE +
805 KSZ8995MA_PORT_SIZE * phy);
806 return (KSZ8995MA_MII_AA | (portreg & 0x0f) << 5);
807 } else if (reg == MII_ANLPAR) {
808 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PS0_BASE +
809 KSZ8995MA_PORT_SIZE * phy);
810 return (((portreg & 0x0f) << 5) | 0x01);
811 }
812
813 return (0);
814 }
815
816 static int
ksz8995ma_writephy(device_t dev,int phy,int reg,int data)817 ksz8995ma_writephy(device_t dev, int phy, int reg, int data)
818 {
819 int portreg;
820
821 /*
822 * This is no mdio/mdc connection code.
823 * simulate MIIM Registers via the SPI interface
824 */
825 if (reg == MII_BMCR) {
826 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC13_BASE +
827 KSZ8995MA_PORT_SIZE * phy);
828 if (data & BMCR_PDOWN)
829 portreg |= KSZ8995MA_PDOWN;
830 else
831 portreg &= ~KSZ8995MA_PDOWN;
832 if (data & BMCR_STARTNEG)
833 portreg |= KSZ8995MA_STARTNEG;
834 else
835 portreg &= ~KSZ8995MA_STARTNEG;
836 ksz8995ma_writereg(dev, KSZ8995MA_PC13_BASE +
837 KSZ8995MA_PORT_SIZE * phy, portreg);
838 } else if (reg == MII_ANAR) {
839 portreg = ksz8995ma_readreg(dev, KSZ8995MA_PC12_BASE +
840 KSZ8995MA_PORT_SIZE * phy);
841 portreg &= 0xf;
842 portreg |= ((data >> 5) & 0x0f);
843 ksz8995ma_writereg(dev, KSZ8995MA_PC12_BASE +
844 KSZ8995MA_PORT_SIZE * phy, portreg);
845 }
846 return (0);
847 }
848
849 static int
ksz8995ma_readreg(device_t dev,int addr)850 ksz8995ma_readreg(device_t dev, int addr)
851 {
852 uint8_t txBuf[8], rxBuf[8];
853 struct spi_command cmd;
854 int err;
855
856 memset(&cmd, 0, sizeof(cmd));
857 memset(txBuf, 0, sizeof(txBuf));
858 memset(rxBuf, 0, sizeof(rxBuf));
859
860 /* read spi */
861 txBuf[0] = KSZ8995MA_SPI_READ;
862 txBuf[1] = addr;
863 cmd.tx_cmd = &txBuf;
864 cmd.rx_cmd = &rxBuf;
865 cmd.tx_cmd_sz = 3;
866 cmd.rx_cmd_sz = 3;
867 err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd);
868 if (err)
869 return(0);
870
871 return (rxBuf[2]);
872 }
873
874 static int
ksz8995ma_writereg(device_t dev,int addr,int value)875 ksz8995ma_writereg(device_t dev, int addr, int value)
876 {
877 uint8_t txBuf[8], rxBuf[8];
878 struct spi_command cmd;
879 int err;
880
881 memset(&cmd, 0, sizeof(cmd));
882 memset(txBuf, 0, sizeof(txBuf));
883 memset(rxBuf, 0, sizeof(rxBuf));
884
885 /* write spi */
886 txBuf[0] = KSZ8995MA_SPI_WRITE;
887 txBuf[1] = addr;
888 txBuf[2] = value;
889 cmd.tx_cmd = &txBuf;
890 cmd.rx_cmd = &rxBuf;
891 cmd.tx_cmd_sz = 3;
892 cmd.rx_cmd_sz = 3;
893 err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd);
894 if (err)
895 return(0);
896
897 return (0);
898 }
899
900 static device_method_t ksz8995ma_methods[] = {
901 /* Device interface */
902 DEVMETHOD(device_probe, ksz8995ma_probe),
903 DEVMETHOD(device_attach, ksz8995ma_attach),
904 DEVMETHOD(device_detach, ksz8995ma_detach),
905
906 /* bus interface */
907 DEVMETHOD(bus_add_child, device_add_child_ordered),
908
909 /* MII interface */
910 DEVMETHOD(miibus_readreg, ksz8995ma_readphy),
911 DEVMETHOD(miibus_writereg, ksz8995ma_writephy),
912 DEVMETHOD(miibus_statchg, ksz8995ma_statchg),
913
914 /* etherswitch interface */
915 DEVMETHOD(etherswitch_lock, ksz8995ma_lock),
916 DEVMETHOD(etherswitch_unlock, ksz8995ma_unlock),
917 DEVMETHOD(etherswitch_getinfo, ksz8995ma_getinfo),
918 DEVMETHOD(etherswitch_readreg, ksz8995ma_readreg),
919 DEVMETHOD(etherswitch_writereg, ksz8995ma_writereg),
920 DEVMETHOD(etherswitch_readphyreg, ksz8995ma_readphy),
921 DEVMETHOD(etherswitch_writephyreg, ksz8995ma_writephy),
922 DEVMETHOD(etherswitch_getport, ksz8995ma_getport),
923 DEVMETHOD(etherswitch_setport, ksz8995ma_setport),
924 DEVMETHOD(etherswitch_getvgroup, ksz8995ma_getvgroup),
925 DEVMETHOD(etherswitch_setvgroup, ksz8995ma_setvgroup),
926 DEVMETHOD(etherswitch_setconf, ksz8995ma_setconf),
927 DEVMETHOD(etherswitch_getconf, ksz8995ma_getconf),
928
929 DEVMETHOD_END
930 };
931
932 DEFINE_CLASS_0(ksz8995ma, ksz8995ma_driver, ksz8995ma_methods,
933 sizeof(struct ksz8995ma_softc));
934
935 DRIVER_MODULE(ksz8995ma, spibus, ksz8995ma_driver, 0, 0);
936 DRIVER_MODULE(miibus, ksz8995ma, miibus_driver, 0, 0);
937 DRIVER_MODULE(etherswitch, ksz8995ma, etherswitch_driver, 0, 0);
938 MODULE_VERSION(ksz8995ma, 1);
939 MODULE_DEPEND(ksz8995ma, spibus, 1, 1, 1); /* XXX which versions? */
940 MODULE_DEPEND(ksz8995ma, miibus, 1, 1, 1); /* XXX which versions? */
941 MODULE_DEPEND(ksz8995ma, etherswitch, 1, 1, 1); /* XXX which versions? */
942