1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
7 * All rights reserved.
8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Driver for the AMD CPU on-die thermal sensors.
34 * Initially based on the k8temp Linux driver.
35 */
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/conf.h>
40 #include <sys/kernel.h>
41 #include <sys/lock.h>
42 #include <sys/module.h>
43 #include <sys/mutex.h>
44 #include <sys/sysctl.h>
45 #include <sys/systm.h>
46
47 #include <machine/cpufunc.h>
48 #include <machine/md_var.h>
49 #include <machine/specialreg.h>
50
51 #include <dev/pci/pcivar.h>
52 #include <x86/pci_cfgreg.h>
53
54 #include <dev/amdsmn/amdsmn.h>
55
56 typedef enum {
57 CORE0_SENSOR0,
58 CORE0_SENSOR1,
59 CORE1_SENSOR0,
60 CORE1_SENSOR1,
61 CORE0,
62 CORE1,
63 CCD1,
64 CCD_BASE = CCD1,
65 CCD2,
66 CCD3,
67 CCD4,
68 CCD5,
69 CCD6,
70 CCD7,
71 CCD8,
72 CCD9,
73 CCD10,
74 CCD11,
75 CCD12,
76 CCD_MAX = CCD12,
77 NUM_CCDS = CCD_MAX - CCD_BASE + 1,
78 } amdsensor_t;
79
80 struct amdtemp_softc {
81 int sc_ncores;
82 int sc_ntemps;
83 int sc_flags;
84 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */
85 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */
86 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */
87 int32_t sc_offset;
88 int32_t sc_temp_base;
89 int32_t (*sc_gettemp)(device_t, amdsensor_t);
90 struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
91 struct intr_config_hook sc_ich;
92 device_t sc_smn;
93 struct mtx sc_lock;
94 };
95
96 /*
97 * N.B. The numbers in macro names below are significant and represent CPU
98 * family and model numbers. Do not make up fictitious family or model numbers
99 * when adding support for new devices.
100 */
101 #define VENDORID_AMD 0x1022
102 #define DEVICEID_AMD_MISC0F 0x1103
103 #define DEVICEID_AMD_MISC10 0x1203
104 #define DEVICEID_AMD_MISC11 0x1303
105 #define DEVICEID_AMD_MISC14 0x1703
106 #define DEVICEID_AMD_MISC15 0x1603
107 #define DEVICEID_AMD_MISC15_M10H 0x1403
108 #define DEVICEID_AMD_MISC15_M30H 0x141d
109 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576
110 #define DEVICEID_AMD_MISC16 0x1533
111 #define DEVICEID_AMD_MISC16_M30H 0x1583
112 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450
113 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
114 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
115 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 /* Also F19H M50H */
116 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4
117 #define DEVICEID_AMD_HOSTB19H_M40H_ROOT 0x14b5
118 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 /* Also F1AH M40H */
119 #define DEVICEID_AMD_HOSTB19H_M70H_ROOT 0x14e8
120
121 static const struct amdtemp_product {
122 uint16_t amdtemp_vendorid;
123 uint16_t amdtemp_deviceid;
124 /*
125 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
126 * drivers do not attach to that device.
127 */
128 bool amdtemp_has_cpuid;
129 } amdtemp_products[] = {
130 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true },
131 { VENDORID_AMD, DEVICEID_AMD_MISC10, true },
132 { VENDORID_AMD, DEVICEID_AMD_MISC11, true },
133 { VENDORID_AMD, DEVICEID_AMD_MISC14, true },
134 { VENDORID_AMD, DEVICEID_AMD_MISC15, true },
135 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true },
136 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true },
137 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false },
138 { VENDORID_AMD, DEVICEID_AMD_MISC16, true },
139 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true },
140 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false },
141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
142 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
143 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
144 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false },
145 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M40H_ROOT, false },
146 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false },
147 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M70H_ROOT, false },
148 };
149
150 /*
151 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
152 */
153 #define AMDTEMP_REPTMP_CTRL 0xa4
154
155 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff
156 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21
157 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3
158 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16
159
160 /*
161 * Reported Temperature, Family 15h, M60+
162 *
163 * Same register bit definitions as other Family 15h CPUs, but access is
164 * indirect via SMN, like Family 17h.
165 */
166 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4
167
168 /*
169 * Reported Temperature, Family 17h
170 *
171 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
172 * provide the current temp. bit 19, when clear, means the temp is reported in
173 * a range 0.."225C" (probable typo for 255C), and when set changes the range
174 * to -49..206C.
175 */
176 #define AMDTEMP_17H_CUR_TMP 0x59800
177 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19)
178 /*
179 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the
180 * 49 degree offset should apply as well. This was revealed in a Linux
181 * patch from an AMD employee.
182 */
183 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16))
184 /*
185 * The following register set was discovered experimentally by Ondrej Čerman
186 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
187 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
188 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it.
189 */
190 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954
191 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
192
193 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00
194 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08
195
196 /*
197 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
198 */
199 #define AMDTEMP_CURTMP_RANGE_ADJUST 490
200
201 /*
202 * Thermaltrip Status Register (Family 0Fh only)
203 */
204 #define AMDTEMP_THERMTP_STAT 0xe4
205 #define AMDTEMP_TTSR_SELCORE 0x04
206 #define AMDTEMP_TTSR_SELSENSOR 0x40
207
208 /*
209 * DRAM Configuration High Register
210 */
211 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */
212 #define AMDTEMP_DRAM_MODE_DDR3 0x0100
213
214 /*
215 * CPU Family/Model Register
216 */
217 #define AMDTEMP_CPUID 0xfc
218
219 /*
220 * Device methods.
221 */
222 static void amdtemp_identify(driver_t *driver, device_t parent);
223 static int amdtemp_probe(device_t dev);
224 static int amdtemp_attach(device_t dev);
225 static void amdtemp_intrhook(void *arg);
226 static int amdtemp_detach(device_t dev);
227 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
228 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor);
229 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
230 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
231 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
232 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model);
233 static void amdtemp_probe_ccd_sensors1ah(device_t dev, uint32_t model);
234 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
235
236 static device_method_t amdtemp_methods[] = {
237 /* Device interface */
238 DEVMETHOD(device_identify, amdtemp_identify),
239 DEVMETHOD(device_probe, amdtemp_probe),
240 DEVMETHOD(device_attach, amdtemp_attach),
241 DEVMETHOD(device_detach, amdtemp_detach),
242
243 DEVMETHOD_END
244 };
245
246 static driver_t amdtemp_driver = {
247 "amdtemp",
248 amdtemp_methods,
249 sizeof(struct amdtemp_softc),
250 };
251
252 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL);
253 MODULE_VERSION(amdtemp, 1);
254 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
255 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
256 nitems(amdtemp_products));
257
258 static bool
amdtemp_match(device_t dev,const struct amdtemp_product ** product_out)259 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
260 {
261 int i;
262 uint16_t vendor, devid;
263
264 vendor = pci_get_vendor(dev);
265 devid = pci_get_device(dev);
266
267 for (i = 0; i < nitems(amdtemp_products); i++) {
268 if (vendor == amdtemp_products[i].amdtemp_vendorid &&
269 devid == amdtemp_products[i].amdtemp_deviceid) {
270 if (product_out != NULL)
271 *product_out = &amdtemp_products[i];
272 return (true);
273 }
274 }
275 return (false);
276 }
277
278 static void
amdtemp_identify(driver_t * driver,device_t parent)279 amdtemp_identify(driver_t *driver, device_t parent)
280 {
281 device_t child;
282
283 /* Make sure we're not being doubly invoked. */
284 if (device_find_child(parent, "amdtemp", -1) != NULL)
285 return;
286
287 if (amdtemp_match(parent, NULL)) {
288 child = device_add_child(parent, "amdtemp", DEVICE_UNIT_ANY);
289 if (child == NULL)
290 device_printf(parent, "add amdtemp child failed\n");
291 }
292 }
293
294 static int
amdtemp_probe(device_t dev)295 amdtemp_probe(device_t dev)
296 {
297 uint32_t family, model;
298
299 if (resource_disabled("amdtemp", 0))
300 return (ENXIO);
301 if (!amdtemp_match(device_get_parent(dev), NULL))
302 return (ENXIO);
303
304 family = CPUID_TO_FAMILY(cpu_id);
305 model = CPUID_TO_MODEL(cpu_id);
306
307 switch (family) {
308 case 0x0f:
309 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
310 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
311 return (ENXIO);
312 break;
313 case 0x10:
314 case 0x11:
315 case 0x12:
316 case 0x14:
317 case 0x15:
318 case 0x16:
319 case 0x17:
320 case 0x19:
321 case 0x1a:
322 break;
323 default:
324 return (ENXIO);
325 }
326 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
327
328 return (BUS_PROBE_GENERIC);
329 }
330
331 static int
amdtemp_attach(device_t dev)332 amdtemp_attach(device_t dev)
333 {
334 char tn[32];
335 u_int regs[4];
336 const struct amdtemp_product *product;
337 struct amdtemp_softc *sc;
338 struct sysctl_ctx_list *sysctlctx;
339 struct sysctl_oid *sysctlnode;
340 uint32_t cpuid, family, model;
341 u_int bid;
342 int erratum319, unit;
343 bool needsmn;
344
345 sc = device_get_softc(dev);
346 erratum319 = 0;
347 needsmn = false;
348
349 if (!amdtemp_match(device_get_parent(dev), &product))
350 return (ENXIO);
351
352 cpuid = cpu_id;
353 family = CPUID_TO_FAMILY(cpuid);
354 model = CPUID_TO_MODEL(cpuid);
355
356 /*
357 * This checks for the byzantine condition of running a heterogenous
358 * revision multi-socket system where the attach thread is potentially
359 * probing a remote socket's PCI device.
360 *
361 * Currently, such scenarios are unsupported on models using the SMN
362 * (because on those models, amdtemp(4) attaches to a different PCI
363 * device than the one that contains AMDTEMP_CPUID).
364 *
365 * The ancient 0x0F family of devices only supports this register from
366 * models 40h+.
367 */
368 if (product->amdtemp_has_cpuid && (family > 0x0f ||
369 (family == 0x0f && model >= 0x40))) {
370 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
371 4);
372 family = CPUID_TO_FAMILY(cpuid);
373 model = CPUID_TO_MODEL(cpuid);
374 }
375
376 switch (family) {
377 case 0x0f:
378 /*
379 * Thermaltrip Status Register
380 *
381 * - ThermSenseCoreSel
382 *
383 * Revision F & G: 0 - Core1, 1 - Core0
384 * Other: 0 - Core0, 1 - Core1
385 *
386 * - CurTmp
387 *
388 * Revision G: bits 23-14
389 * Other: bits 23-16
390 *
391 * XXX According to the BKDG, CurTmp, ThermSenseSel and
392 * ThermSenseCoreSel bits were introduced in Revision F
393 * but CurTmp seems working fine as early as Revision C.
394 * However, it is not clear whether ThermSenseSel and/or
395 * ThermSenseCoreSel work in undocumented cases as well.
396 * In fact, the Linux driver suggests it may not work but
397 * we just assume it does until we find otherwise.
398 *
399 * XXX According to Linux, CurTmp starts at -28C on
400 * Socket AM2 Revision G processors, which is not
401 * documented anywhere.
402 */
403 if (model >= 0x40)
404 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
405 if (model >= 0x60 && model != 0xc1) {
406 do_cpuid(0x80000001, regs);
407 bid = (regs[1] >> 9) & 0x1f;
408 switch (model) {
409 case 0x68: /* Socket S1g1 */
410 case 0x6c:
411 case 0x7c:
412 break;
413 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
414 if (bid != 0x0b && bid != 0x0c)
415 sc->sc_flags |=
416 AMDTEMP_FLAG_ALT_OFFSET;
417 break;
418 case 0x6f: /* Socket AM2 and ASB1 (1 core) */
419 case 0x7f:
420 if (bid != 0x07 && bid != 0x09 &&
421 bid != 0x0c)
422 sc->sc_flags |=
423 AMDTEMP_FLAG_ALT_OFFSET;
424 break;
425 default:
426 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
427 }
428 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
429 }
430
431 /*
432 * There are two sensors per core.
433 */
434 sc->sc_ntemps = 2;
435
436 sc->sc_gettemp = amdtemp_gettemp0f;
437 break;
438 case 0x10:
439 /*
440 * Erratum 319 Inaccurate Temperature Measurement
441 *
442 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
443 */
444 do_cpuid(0x80000001, regs);
445 switch ((regs[1] >> 28) & 0xf) {
446 case 0: /* Socket F */
447 erratum319 = 1;
448 break;
449 case 1: /* Socket AM2+ or AM3 */
450 if ((pci_cfgregread(pci_get_domain(dev),
451 pci_get_bus(dev), pci_get_slot(dev), 2,
452 AMDTEMP_DRAM_CONF_HIGH, 2) &
453 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
454 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
455 break;
456 /* XXX 00100F42h (RB-C2) exists in both formats. */
457 erratum319 = 1;
458 break;
459 }
460 /* FALLTHROUGH */
461 case 0x11:
462 case 0x12:
463 case 0x14:
464 case 0x15:
465 case 0x16:
466 sc->sc_ntemps = 1;
467 /*
468 * Some later (60h+) models of family 15h use a similar SMN
469 * network as family 17h. (However, the register index differs
470 * from 17h and the decoding matches other 10h-15h models,
471 * which differ from 17h.)
472 */
473 if (family == 0x15 && model >= 0x60) {
474 sc->sc_gettemp = amdtemp_gettemp15hm60h;
475 needsmn = true;
476 } else
477 sc->sc_gettemp = amdtemp_gettemp;
478 break;
479 case 0x17:
480 case 0x19:
481 case 0x1a:
482 sc->sc_ntemps = 1;
483 sc->sc_gettemp = amdtemp_gettemp17h;
484 needsmn = true;
485 break;
486 default:
487 device_printf(dev, "Bogus family 0x%x\n", family);
488 return (ENXIO);
489 }
490
491 if (needsmn) {
492 sc->sc_smn = device_find_child(
493 device_get_parent(dev), "amdsmn", -1);
494 if (sc->sc_smn == NULL) {
495 if (bootverbose)
496 device_printf(dev, "No SMN device found\n");
497 return (ENXIO);
498 }
499 }
500
501 /* Find number of cores per package. */
502 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
503 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
504 if (sc->sc_ncores > MAXCPU)
505 return (ENXIO);
506
507 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF);
508 if (erratum319)
509 device_printf(dev,
510 "Erratum 319: temperature measurement may be inaccurate\n");
511 if (bootverbose)
512 device_printf(dev, "Found %d cores and %d sensors.\n",
513 sc->sc_ncores,
514 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
515
516 /*
517 * dev.amdtemp.N tree.
518 */
519 unit = device_get_unit(dev);
520 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
521 TUNABLE_INT_FETCH(tn, &sc->sc_offset);
522
523 sysctlctx = device_get_sysctl_ctx(dev);
524 SYSCTL_ADD_INT(sysctlctx,
525 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
526 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
527 "Temperature sensor offset");
528 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
529 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
530 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");
531
532 SYSCTL_ADD_PROC(sysctlctx,
533 SYSCTL_CHILDREN(sysctlnode),
534 OID_AUTO, "sensor0",
535 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
536 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
537 "Core 0 / Sensor 0 temperature");
538
539 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE;
540
541 if (family == 0x17)
542 amdtemp_probe_ccd_sensors17h(dev, model);
543 else if (family == 0x19)
544 amdtemp_probe_ccd_sensors19h(dev, model);
545 else if (family == 0x1a)
546 amdtemp_probe_ccd_sensors1ah(dev, model);
547 else if (sc->sc_ntemps > 1) {
548 SYSCTL_ADD_PROC(sysctlctx,
549 SYSCTL_CHILDREN(sysctlnode),
550 OID_AUTO, "sensor1",
551 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
552 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
553 "Core 0 / Sensor 1 temperature");
554
555 if (sc->sc_ncores > 1) {
556 sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
558 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE,
559 0, "Core 1");
560
561 SYSCTL_ADD_PROC(sysctlctx,
562 SYSCTL_CHILDREN(sysctlnode),
563 OID_AUTO, "sensor0",
564 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
565 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
566 "Core 1 / Sensor 0 temperature");
567
568 SYSCTL_ADD_PROC(sysctlctx,
569 SYSCTL_CHILDREN(sysctlnode),
570 OID_AUTO, "sensor1",
571 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
572 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
573 "Core 1 / Sensor 1 temperature");
574 }
575 }
576
577 /*
578 * Try to create dev.cpu sysctl entries and setup intrhook function.
579 * This is needed because the cpu driver may be loaded late on boot,
580 * after us.
581 */
582 amdtemp_intrhook(dev);
583 sc->sc_ich.ich_func = amdtemp_intrhook;
584 sc->sc_ich.ich_arg = dev;
585 if (config_intrhook_establish(&sc->sc_ich) != 0) {
586 device_printf(dev, "config_intrhook_establish failed!\n");
587 return (ENXIO);
588 }
589
590 return (0);
591 }
592
593 void
amdtemp_intrhook(void * arg)594 amdtemp_intrhook(void *arg)
595 {
596 struct amdtemp_softc *sc;
597 struct sysctl_ctx_list *sysctlctx;
598 device_t dev = (device_t)arg;
599 device_t acpi, cpu, nexus;
600 amdsensor_t sensor;
601 int i;
602
603 sc = device_get_softc(dev);
604
605 /*
606 * dev.cpu.N.temperature.
607 */
608 nexus = device_find_child(root_bus, "nexus", 0);
609 acpi = device_find_child(nexus, "acpi", 0);
610
611 for (i = 0; i < sc->sc_ncores; i++) {
612 if (sc->sc_sysctl_cpu[i] != NULL)
613 continue;
614 cpu = device_find_child(acpi, "cpu",
615 device_get_unit(dev) * sc->sc_ncores + i);
616 if (cpu != NULL) {
617 sysctlctx = device_get_sysctl_ctx(cpu);
618
619 sensor = sc->sc_ntemps > 1 ?
620 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
621 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
622 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
623 OID_AUTO, "temperature",
624 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
625 dev, sensor, amdtemp_sysctl, "IK",
626 "Current temparature");
627 }
628 }
629 if (sc->sc_ich.ich_arg != NULL)
630 config_intrhook_disestablish(&sc->sc_ich);
631 }
632
633 int
amdtemp_detach(device_t dev)634 amdtemp_detach(device_t dev)
635 {
636 struct amdtemp_softc *sc = device_get_softc(dev);
637 int i;
638
639 for (i = 0; i < sc->sc_ncores; i++)
640 if (sc->sc_sysctl_cpu[i] != NULL)
641 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
642
643 /* NewBus removes the dev.amdtemp.N tree by itself. */
644
645 mtx_destroy(&sc->sc_lock);
646 return (0);
647 }
648
649 static int
amdtemp_sysctl(SYSCTL_HANDLER_ARGS)650 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
651 {
652 device_t dev = (device_t)arg1;
653 struct amdtemp_softc *sc = device_get_softc(dev);
654 amdsensor_t sensor = (amdsensor_t)arg2;
655 int32_t auxtemp[2], temp;
656 int error;
657
658 switch (sensor) {
659 case CORE0:
660 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
661 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
662 temp = imax(auxtemp[0], auxtemp[1]);
663 break;
664 case CORE1:
665 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
666 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
667 temp = imax(auxtemp[0], auxtemp[1]);
668 break;
669 default:
670 temp = sc->sc_gettemp(dev, sensor);
671 break;
672 }
673 error = sysctl_handle_int(oidp, &temp, 0, req);
674
675 return (error);
676 }
677
678 #define AMDTEMP_ZERO_C_TO_K 2731
679
680 static int32_t
amdtemp_gettemp0f(device_t dev,amdsensor_t sensor)681 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
682 {
683 struct amdtemp_softc *sc = device_get_softc(dev);
684 uint32_t mask, offset, temp;
685
686 mtx_lock(&sc->sc_lock);
687
688 /* Set Sensor/Core selector. */
689 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
690 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
691 switch (sensor) {
692 case CORE0_SENSOR1:
693 temp |= AMDTEMP_TTSR_SELSENSOR;
694 /* FALLTHROUGH */
695 case CORE0_SENSOR0:
696 case CORE0:
697 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
698 temp |= AMDTEMP_TTSR_SELCORE;
699 break;
700 case CORE1_SENSOR1:
701 temp |= AMDTEMP_TTSR_SELSENSOR;
702 /* FALLTHROUGH */
703 case CORE1_SENSOR0:
704 case CORE1:
705 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
706 temp |= AMDTEMP_TTSR_SELCORE;
707 break;
708 default:
709 __assert_unreachable();
710 }
711 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
712
713 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
714 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
715 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
716 temp = ((temp >> 14) & mask) * 5 / 2;
717 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
718
719 mtx_unlock(&sc->sc_lock);
720 return (temp);
721 }
722
723 static uint32_t
amdtemp_decode_fam10h_to_17h(int32_t sc_offset,uint32_t val,bool minus49)724 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
725 {
726 uint32_t temp;
727
728 /* Convert raw register subfield units (0.125C) to units of 0.1C. */
729 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
730
731 if (minus49)
732 temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
733
734 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
735 return (temp);
736 }
737
738 static uint32_t
amdtemp_decode_fam10h_to_16h(int32_t sc_offset,uint32_t val)739 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
740 {
741 bool minus49;
742
743 /*
744 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
745 * adjusted down by 49.0 degrees Celsius. (This adjustment is not
746 * documented in BKDGs prior to family 15h model 00h.)
747 */
748 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
749 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
750 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
751
752 return (amdtemp_decode_fam10h_to_17h(sc_offset,
753 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
754 }
755
756 static uint32_t
amdtemp_decode_fam17h_tctl(int32_t sc_offset,uint32_t val)757 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
758 {
759 bool minus49;
760
761 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0)
762 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL);
763 return (amdtemp_decode_fam10h_to_17h(sc_offset,
764 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
765 }
766
767 static int32_t
amdtemp_gettemp(device_t dev,amdsensor_t sensor)768 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
769 {
770 struct amdtemp_softc *sc = device_get_softc(dev);
771 uint32_t temp;
772
773 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
774 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
775 }
776
777 static int32_t
amdtemp_gettemp15hm60h(device_t dev,amdsensor_t sensor)778 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
779 {
780 struct amdtemp_softc *sc = device_get_softc(dev);
781 uint32_t val;
782 int error __diagused;
783
784 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
785 KASSERT(error == 0, ("amdsmn_read"));
786 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
787 }
788
789 static int32_t
amdtemp_gettemp17h(device_t dev,amdsensor_t sensor)790 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
791 {
792 struct amdtemp_softc *sc = device_get_softc(dev);
793 uint32_t val;
794 int error __diagused;
795
796 switch (sensor) {
797 case CORE0_SENSOR0:
798 /* Tctl */
799 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
800 KASSERT(error == 0, ("amdsmn_read"));
801 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
802 case CCD_BASE ... CCD_MAX:
803 /* Tccd<N> */
804 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
805 (((int)sensor - CCD_BASE) * sizeof(val)), &val);
806 KASSERT(error == 0, ("amdsmn_read2"));
807 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
808 ("sensor %d: not valid", (int)sensor));
809 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
810 default:
811 __assert_unreachable();
812 }
813 }
814
815 static void
amdtemp_probe_ccd_sensors(device_t dev,uint32_t maxreg)816 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg)
817 {
818 char sensor_name[16], sensor_descr[32];
819 struct amdtemp_softc *sc;
820 uint32_t i, val;
821 int error;
822
823 sc = device_get_softc(dev);
824 for (i = 0; i < maxreg; i++) {
825 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base +
826 (i * sizeof(val)), &val);
827 if (error != 0)
828 continue;
829 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
830 continue;
831
832 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
833 snprintf(sensor_descr, sizeof(sensor_descr),
834 "CCD %u temperature (Tccd%u)", i, i);
835
836 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
837 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
838 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
839 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);
840 }
841 }
842
843 static void
amdtemp_probe_ccd_sensors17h(device_t dev,uint32_t model)844 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
845 {
846 uint32_t maxreg;
847
848 switch (model) {
849 case 0x00 ... 0x2f: /* Zen1, Zen+ */
850 maxreg = 4;
851 break;
852 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
853 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
854 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
855 maxreg = 8;
856 _Static_assert((int)NUM_CCDS >= 8, "");
857 break;
858 default:
859 device_printf(dev,
860 "Unrecognized Family 17h Model: %02xh\n", model);
861 return;
862 }
863
864 amdtemp_probe_ccd_sensors(dev, maxreg);
865 }
866
867 static void
amdtemp_probe_ccd_sensors19h(device_t dev,uint32_t model)868 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model)
869 {
870 struct amdtemp_softc *sc = device_get_softc(dev);
871 uint32_t maxreg;
872
873 switch (model) {
874 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
875 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
876 case 0x50 ... 0x5f: /* Zen3 Ryzen "Cezanne" */
877 maxreg = 8;
878 _Static_assert((int)NUM_CCDS >= 8, "");
879 break;
880 case 0x10 ... 0x1f:
881 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE;
882 maxreg = 12;
883 _Static_assert((int)NUM_CCDS >= 12, "");
884 break;
885 case 0x40 ... 0x4f: /* Zen3+ Ryzen "Rembrandt" */
886 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
887 case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */
888 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;
889 maxreg = 8;
890 _Static_assert((int)NUM_CCDS >= 8, "");
891 break;
892 default:
893 device_printf(dev,
894 "Unrecognized Family 19h Model: %02xh\n", model);
895 return;
896 }
897
898 amdtemp_probe_ccd_sensors(dev, maxreg);
899 }
900
901 static void
amdtemp_probe_ccd_sensors1ah(device_t dev,uint32_t model)902 amdtemp_probe_ccd_sensors1ah(device_t dev, uint32_t model)
903 {
904 struct amdtemp_softc *sc = device_get_softc(dev);
905 uint32_t maxreg;
906
907 switch (model) {
908 case 0x40 ... 0x4f: /* Zen5 Ryzen "Granite Ridge" */
909 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;
910 maxreg = 8;
911 _Static_assert((int)NUM_CCDS >= 8, "");
912 break;
913 default:
914 device_printf(dev,
915 "Unrecognized Family 1ah Model: %02xh\n", model);
916 return;
917 }
918
919 amdtemp_probe_ccd_sensors(dev, maxreg);
920 }
921