1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include "dc_types.h"
28 #include "dm_services.h"
29 #include "dc.h"
30
31 #include "dcn32/dcn32_init.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "dcn32_resource.h"
36
37 #include "dcn20/dcn20_resource.h"
38 #include "dcn30/dcn30_resource.h"
39
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn30/dcn30_hubbub.h"
42 #include "dcn31/dcn31_hubbub.h"
43 #include "dcn32/dcn32_hubbub.h"
44 #include "dcn32/dcn32_mpc.h"
45 #include "dcn32/dcn32_hubp.h"
46 #include "irq/dcn32/irq_service_dcn32.h"
47 #include "dcn32/dcn32_dpp.h"
48 #include "dcn32/dcn32_optc.h"
49 #include "dcn20/dcn20_hwseq.h"
50 #include "dcn30/dcn30_hwseq.h"
51 #include "dce110/dce110_hwseq.h"
52 #include "dcn30/dcn30_opp.h"
53 #include "dcn20/dcn20_dsc.h"
54 #include "dcn30/dcn30_vpg.h"
55 #include "dcn30/dcn30_afmt.h"
56 #include "dcn30/dcn30_dio_stream_encoder.h"
57 #include "dcn32/dcn32_dio_stream_encoder.h"
58 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
59 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
60 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
61 #include "dcn31/dcn31_apg.h"
62 #include "dcn31/dcn31_dio_link_encoder.h"
63 #include "dcn32/dcn32_dio_link_encoder.h"
64 #include "dce/dce_clock_source.h"
65 #include "dce/dce_audio.h"
66 #include "dce/dce_hwseq.h"
67 #include "clk_mgr.h"
68 #include "virtual/virtual_stream_encoder.h"
69 #include "dml/display_mode_vba.h"
70 #include "dcn32/dcn32_dccg.h"
71 #include "dcn10/dcn10_resource.h"
72 #include "link.h"
73 #include "dcn31/dcn31_panel_cntl.h"
74
75 #include "dcn30/dcn30_dwb.h"
76 #include "dcn32/dcn32_mmhubbub.h"
77
78 #include "dcn/dcn_3_2_0_offset.h"
79 #include "dcn/dcn_3_2_0_sh_mask.h"
80 #include "nbio/nbio_4_3_0_offset.h"
81
82 #include "reg_helper.h"
83 #include "dce/dmub_abm.h"
84 #include "dce/dmub_psr.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87
88 #include "dml/dcn30/display_mode_vba_30.h"
89 #include "vm_helper.h"
90 #include "dcn20/dcn20_vmid.h"
91 #include "dml/dcn32/dcn32_fpu.h"
92
93 #include "dc_state_priv.h"
94
95 #include "dml2/dml2_wrapper.h"
96
97 #define DC_LOGGER_INIT(logger)
98
99 enum dcn32_clk_src_array_id {
100 DCN32_CLK_SRC_PLL0,
101 DCN32_CLK_SRC_PLL1,
102 DCN32_CLK_SRC_PLL2,
103 DCN32_CLK_SRC_PLL3,
104 DCN32_CLK_SRC_PLL4,
105 DCN32_CLK_SRC_TOTAL
106 };
107
108 /* begin *********************
109 * macros to expend register list macro defined in HW object header file
110 */
111
112 /* DCN */
113 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
114
115 #define BASE(seg) BASE_INNER(seg)
116
117 #define SR(reg_name)\
118 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
119 reg ## reg_name
120 #define SR_ARR(reg_name, id) \
121 REG_STRUCT[id].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
122
123 #define SR_ARR_INIT(reg_name, id, value) \
124 REG_STRUCT[id].reg_name = value
125
126 #define SRI(reg_name, block, id)\
127 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
128 reg ## block ## id ## _ ## reg_name
129
130 #define SRI_ARR(reg_name, block, id)\
131 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
132 reg ## block ## id ## _ ## reg_name
133
134 #define SR_ARR_I2C(reg_name, id) \
135 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
136
137 #define SRI_ARR_I2C(reg_name, block, id)\
138 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
139 reg ## block ## id ## _ ## reg_name
140
141 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
142 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
143 reg ## block ## id ## _ ## reg_name
144
145 #define SRI2(reg_name, block, id)\
146 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
147 reg ## reg_name
148 #define SRI2_ARR(reg_name, block, id)\
149 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
150 reg ## reg_name
151
152 #define SRIR(var_name, reg_name, block, id)\
153 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 reg ## block ## id ## _ ## reg_name
155
156 #define SRII(reg_name, block, id)\
157 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 reg ## block ## id ## _ ## reg_name
159
160 #define SRII_ARR_2(reg_name, block, id, inst)\
161 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
162 reg ## block ## id ## _ ## reg_name
163
164 #define SRII_MPC_RMU(reg_name, block, id)\
165 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
166 reg ## block ## id ## _ ## reg_name
167
168 #define SRII_DWB(reg_name, temp_name, block, id)\
169 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
170 reg ## block ## id ## _ ## temp_name
171
172 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
173 .field_name = reg_name ## __ ## field_name ## post_fix
174
175 #define DCCG_SRII(reg_name, block, id)\
176 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177 reg ## block ## id ## _ ## reg_name
178
179 #define VUPDATE_SRII(reg_name, block, id)\
180 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
181 reg ## reg_name ## _ ## block ## id
182
183 /* NBIO */
184 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
185
186 #define NBIO_BASE(seg) \
187 NBIO_BASE_INNER(seg)
188
189 #define NBIO_SR(reg_name)\
190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
191 regBIF_BX0_ ## reg_name
192 #define NBIO_SR_ARR(reg_name, id)\
193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
194 regBIF_BX0_ ## reg_name
195
196 #undef CTX
197 #define CTX ctx
198 #define REG(reg_name) \
199 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
200
201 static struct bios_registers bios_regs;
202
203 #define bios_regs_init() \
204 ( \
205 NBIO_SR(BIOS_SCRATCH_3),\
206 NBIO_SR(BIOS_SCRATCH_6)\
207 )
208
209 #define clk_src_regs_init(index, pllid)\
210 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
211
212 static struct dce110_clk_src_regs clk_src_regs[5];
213
214 static const struct dce110_clk_src_shift cs_shift = {
215 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
216 };
217
218 static const struct dce110_clk_src_mask cs_mask = {
219 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
220 };
221
222 #define abm_regs_init(id)\
223 ABM_DCN32_REG_LIST_RI(id)
224
225 static struct dce_abm_registers abm_regs[4];
226
227 static const struct dce_abm_shift abm_shift = {
228 ABM_MASK_SH_LIST_DCN32(__SHIFT)
229 };
230
231 static const struct dce_abm_mask abm_mask = {
232 ABM_MASK_SH_LIST_DCN32(_MASK)
233 };
234
235 #define audio_regs_init(id)\
236 AUD_COMMON_REG_LIST_RI(id)
237
238 static struct dce_audio_registers audio_regs[5];
239
240 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
241 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
242 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
243 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
244
245 static const struct dce_audio_shift audio_shift = {
246 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
247 };
248
249 static const struct dce_audio_mask audio_mask = {
250 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
251 };
252
253 #define vpg_regs_init(id)\
254 VPG_DCN3_REG_LIST_RI(id)
255
256 static struct dcn30_vpg_registers vpg_regs[10];
257
258 static const struct dcn30_vpg_shift vpg_shift = {
259 DCN3_VPG_MASK_SH_LIST(__SHIFT)
260 };
261
262 static const struct dcn30_vpg_mask vpg_mask = {
263 DCN3_VPG_MASK_SH_LIST(_MASK)
264 };
265
266 #define afmt_regs_init(id)\
267 AFMT_DCN3_REG_LIST_RI(id)
268
269 static struct dcn30_afmt_registers afmt_regs[6];
270
271 static const struct dcn30_afmt_shift afmt_shift = {
272 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
273 };
274
275 static const struct dcn30_afmt_mask afmt_mask = {
276 DCN3_AFMT_MASK_SH_LIST(_MASK)
277 };
278
279 #define apg_regs_init(id)\
280 APG_DCN31_REG_LIST_RI(id)
281
282 static struct dcn31_apg_registers apg_regs[4];
283
284 static const struct dcn31_apg_shift apg_shift = {
285 DCN31_APG_MASK_SH_LIST(__SHIFT)
286 };
287
288 static const struct dcn31_apg_mask apg_mask = {
289 DCN31_APG_MASK_SH_LIST(_MASK)
290 };
291
292 #define stream_enc_regs_init(id)\
293 SE_DCN32_REG_LIST_RI(id)
294
295 static struct dcn10_stream_enc_registers stream_enc_regs[5];
296
297 static const struct dcn10_stream_encoder_shift se_shift = {
298 SE_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
299 };
300
301 static const struct dcn10_stream_encoder_mask se_mask = {
302 SE_COMMON_MASK_SH_LIST_DCN32(_MASK)
303 };
304
305
306 #define aux_regs_init(id)\
307 DCN2_AUX_REG_LIST_RI(id)
308
309 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
310
311 #define hpd_regs_init(id)\
312 HPD_REG_LIST_RI(id)
313
314 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
315
316 #define link_regs_init(id, phyid)\
317 ( \
318 LE_DCN31_REG_LIST_RI(id), \
319 UNIPHY_DCN2_REG_LIST_RI(id, phyid)\
320 )
321 /*DPCS_DCN31_REG_LIST(id),*/ \
322
323 static struct dcn10_link_enc_registers link_enc_regs[5];
324
325 static const struct dcn10_link_enc_shift le_shift = {
326 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
327 //DPCS_DCN31_MASK_SH_LIST(__SHIFT)
328 };
329
330 static const struct dcn10_link_enc_mask le_mask = {
331 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
332 //DPCS_DCN31_MASK_SH_LIST(_MASK)
333 };
334
335 #define hpo_dp_stream_encoder_reg_init(id)\
336 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
337
338 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
339
340 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
341 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
342 };
343
344 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
345 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
346 };
347
348
349 #define hpo_dp_link_encoder_reg_init(id)\
350 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
351 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
352 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
353 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
354 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
355
356 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[2];
357
358 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
359 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
360 };
361
362 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
363 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
364 };
365
366 #define dpp_regs_init(id)\
367 DPP_REG_LIST_DCN30_COMMON_RI(id)
368
369 static struct dcn3_dpp_registers dpp_regs[4];
370
371 static const struct dcn3_dpp_shift tf_shift = {
372 DPP_REG_LIST_SH_MASK_DCN30_COMMON(__SHIFT)
373 };
374
375 static const struct dcn3_dpp_mask tf_mask = {
376 DPP_REG_LIST_SH_MASK_DCN30_COMMON(_MASK)
377 };
378
379
380 #define opp_regs_init(id)\
381 OPP_REG_LIST_DCN30_RI(id)
382
383 static struct dcn20_opp_registers opp_regs[4];
384
385 static const struct dcn20_opp_shift opp_shift = {
386 OPP_MASK_SH_LIST_DCN20(__SHIFT)
387 };
388
389 static const struct dcn20_opp_mask opp_mask = {
390 OPP_MASK_SH_LIST_DCN20(_MASK)
391 };
392
393 #define aux_engine_regs_init(id)\
394 ( \
395 AUX_COMMON_REG_LIST0_RI(id), \
396 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
397 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
398 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
399 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)\
400 )
401
402 static struct dce110_aux_registers aux_engine_regs[5];
403
404 static const struct dce110_aux_registers_shift aux_shift = {
405 DCN_AUX_MASK_SH_LIST(__SHIFT)
406 };
407
408 static const struct dce110_aux_registers_mask aux_mask = {
409 DCN_AUX_MASK_SH_LIST(_MASK)
410 };
411
412 #define dwbc_regs_dcn3_init(id)\
413 DWBC_COMMON_REG_LIST_DCN30_RI(id)
414
415 static struct dcn30_dwbc_registers dwbc30_regs[1];
416
417 static const struct dcn30_dwbc_shift dwbc30_shift = {
418 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
419 };
420
421 static const struct dcn30_dwbc_mask dwbc30_mask = {
422 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
423 };
424
425 #define mcif_wb_regs_dcn3_init(id)\
426 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
427
428 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
429
430 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
431 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
432 };
433
434 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
435 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
436 };
437
438 #define dsc_regsDCN20_init(id)\
439 DSC_REG_LIST_DCN20_RI(id)
440
441 static struct dcn20_dsc_registers dsc_regs[4];
442
443 static const struct dcn20_dsc_shift dsc_shift = {
444 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
445 };
446
447 static const struct dcn20_dsc_mask dsc_mask = {
448 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
449 };
450
451 static struct dcn30_mpc_registers mpc_regs;
452
453 #define dcn_mpc_regs_init() \
454 MPC_REG_LIST_DCN3_2_RI(0),\
455 MPC_REG_LIST_DCN3_2_RI(1),\
456 MPC_REG_LIST_DCN3_2_RI(2),\
457 MPC_REG_LIST_DCN3_2_RI(3),\
458 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
459 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
460 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
461 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
462 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
463
464 static const struct dcn30_mpc_shift mpc_shift = {
465 MPC_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
466 };
467
468 static const struct dcn30_mpc_mask mpc_mask = {
469 MPC_COMMON_MASK_SH_LIST_DCN32(_MASK)
470 };
471
472 #define optc_regs_init(id)\
473 OPTC_COMMON_REG_LIST_DCN3_2_RI(id)
474
475 static struct dcn_optc_registers optc_regs[4];
476
477 static const struct dcn_optc_shift optc_shift = {
478 OPTC_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
479 };
480
481 static const struct dcn_optc_mask optc_mask = {
482 OPTC_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
483 };
484
485 #define hubp_regs_init(id)\
486 HUBP_REG_LIST_DCN32_RI(id)
487
488 static struct dcn_hubp2_registers hubp_regs[4];
489
490
491 static const struct dcn_hubp2_shift hubp_shift = {
492 HUBP_MASK_SH_LIST_DCN32(__SHIFT)
493 };
494
495 static const struct dcn_hubp2_mask hubp_mask = {
496 HUBP_MASK_SH_LIST_DCN32(_MASK)
497 };
498
499 static struct dcn_hubbub_registers hubbub_reg;
500 #define hubbub_reg_init()\
501 HUBBUB_REG_LIST_DCN32_RI(0)
502
503 static const struct dcn_hubbub_shift hubbub_shift = {
504 HUBBUB_MASK_SH_LIST_DCN32(__SHIFT)
505 };
506
507 static const struct dcn_hubbub_mask hubbub_mask = {
508 HUBBUB_MASK_SH_LIST_DCN32(_MASK)
509 };
510
511 static struct dccg_registers dccg_regs;
512
513 #define dccg_regs_init()\
514 DCCG_REG_LIST_DCN32_RI()
515
516 static const struct dccg_shift dccg_shift = {
517 DCCG_MASK_SH_LIST_DCN32(__SHIFT)
518 };
519
520 static const struct dccg_mask dccg_mask = {
521 DCCG_MASK_SH_LIST_DCN32(_MASK)
522 };
523
524
525 #define SRII2(reg_name_pre, reg_name_post, id)\
526 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
527 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
528 reg ## reg_name_pre ## id ## _ ## reg_name_post
529
530
531 #define HWSEQ_DCN32_REG_LIST()\
532 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
533 SR(DIO_MEM_PWR_CTRL), \
534 SR(ODM_MEM_PWR_CTRL3), \
535 SR(MMHUBBUB_MEM_PWR_CNTL), \
536 SR(DCCG_GATE_DISABLE_CNTL), \
537 SR(DCCG_GATE_DISABLE_CNTL2), \
538 SR(DCFCLK_CNTL),\
539 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
540 SRII(PIXEL_RATE_CNTL, OTG, 0), \
541 SRII(PIXEL_RATE_CNTL, OTG, 1),\
542 SRII(PIXEL_RATE_CNTL, OTG, 2),\
543 SRII(PIXEL_RATE_CNTL, OTG, 3),\
544 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
545 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
546 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
547 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
548 SR(MICROSECOND_TIME_BASE_DIV), \
549 SR(MILLISECOND_TIME_BASE_DIV), \
550 SR(DISPCLK_FREQ_CHANGE_CNTL), \
551 SR(RBBMIF_TIMEOUT_DIS), \
552 SR(RBBMIF_TIMEOUT_DIS_2), \
553 SR(DCHUBBUB_CRC_CTRL), \
554 SR(DPP_TOP0_DPP_CRC_CTRL), \
555 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
556 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
557 SR(MPC_CRC_CTRL), \
558 SR(MPC_CRC_RESULT_GB), \
559 SR(MPC_CRC_RESULT_C), \
560 SR(MPC_CRC_RESULT_AR), \
561 SR(DOMAIN0_PG_CONFIG), \
562 SR(DOMAIN1_PG_CONFIG), \
563 SR(DOMAIN2_PG_CONFIG), \
564 SR(DOMAIN3_PG_CONFIG), \
565 SR(DOMAIN16_PG_CONFIG), \
566 SR(DOMAIN17_PG_CONFIG), \
567 SR(DOMAIN18_PG_CONFIG), \
568 SR(DOMAIN19_PG_CONFIG), \
569 SR(DOMAIN0_PG_STATUS), \
570 SR(DOMAIN1_PG_STATUS), \
571 SR(DOMAIN2_PG_STATUS), \
572 SR(DOMAIN3_PG_STATUS), \
573 SR(DOMAIN16_PG_STATUS), \
574 SR(DOMAIN17_PG_STATUS), \
575 SR(DOMAIN18_PG_STATUS), \
576 SR(DOMAIN19_PG_STATUS), \
577 SR(D1VGA_CONTROL), \
578 SR(D2VGA_CONTROL), \
579 SR(D3VGA_CONTROL), \
580 SR(D4VGA_CONTROL), \
581 SR(D5VGA_CONTROL), \
582 SR(D6VGA_CONTROL), \
583 SR(DC_IP_REQUEST_CNTL), \
584 SR(AZALIA_AUDIO_DTO), \
585 SR(AZALIA_CONTROLLER_CLOCK_GATING)
586
587 static struct dce_hwseq_registers hwseq_reg;
588
589 #define hwseq_reg_init()\
590 HWSEQ_DCN32_REG_LIST()
591
592 #define HWSEQ_DCN32_MASK_SH_LIST(mask_sh)\
593 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
594 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
595 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
599 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
600 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
601 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
602 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
603 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
604 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
605 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
606 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
607 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
608 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
609 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
610 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
611 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
614 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
615 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
616 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
617 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
618 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
619 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
620 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
621 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
622 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
623 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
624 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
625
626 static const struct dce_hwseq_shift hwseq_shift = {
627 HWSEQ_DCN32_MASK_SH_LIST(__SHIFT)
628 };
629
630 static const struct dce_hwseq_mask hwseq_mask = {
631 HWSEQ_DCN32_MASK_SH_LIST(_MASK)
632 };
633 #define vmid_regs_init(id)\
634 DCN20_VMID_REG_LIST_RI(id)
635
636 static struct dcn_vmid_registers vmid_regs[16];
637
638 static const struct dcn20_vmid_shift vmid_shifts = {
639 DCN20_VMID_MASK_SH_LIST(__SHIFT)
640 };
641
642 static const struct dcn20_vmid_mask vmid_masks = {
643 DCN20_VMID_MASK_SH_LIST(_MASK)
644 };
645
646 static const struct resource_caps res_cap_dcn32 = {
647 .num_timing_generator = 4,
648 .num_opp = 4,
649 .num_video_plane = 4,
650 .num_audio = 5,
651 .num_stream_encoder = 5,
652 .num_hpo_dp_stream_encoder = 4,
653 .num_hpo_dp_link_encoder = 2,
654 .num_pll = 5,
655 .num_dwb = 1,
656 .num_ddc = 5,
657 .num_vmid = 16,
658 .num_mpc_3dlut = 4,
659 .num_dsc = 4,
660 };
661
662 static const struct dc_plane_cap plane_cap = {
663 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
664 .per_pixel_alpha = true,
665
666 .pixel_format_support = {
667 .argb8888 = true,
668 .nv12 = true,
669 .fp16 = true,
670 .p010 = true,
671 .ayuv = false,
672 },
673
674 .max_upscale_factor = {
675 .argb8888 = 16000,
676 .nv12 = 16000,
677 .fp16 = 16000
678 },
679
680 // 6:1 downscaling ratio: 1000/6 = 166.666
681 .max_downscale_factor = {
682 .argb8888 = 167,
683 .nv12 = 167,
684 .fp16 = 167
685 },
686 64,
687 64
688 };
689
690 static const struct dc_debug_options debug_defaults_drv = {
691 .disable_dmcu = true,
692 .force_abm_enable = false,
693 .clock_trace = true,
694 .disable_pplib_clock_request = false,
695 .pipe_split_policy = MPC_SPLIT_AVOID, // Due to CRB, no need to MPC split anymore
696 .force_single_disp_pipe_split = false,
697 .disable_dcc = DCC_ENABLE,
698 .vsr_support = true,
699 .performance_trace = false,
700 .max_downscale_src_width = 7680,/*upto 8K*/
701 .disable_pplib_wm_range = false,
702 .scl_reset_length10 = true,
703 .sanity_checks = false,
704 .underflow_assert_delay_us = 0xFFFFFFFF,
705 .dwb_fi_phase = -1, // -1 = disable,
706 .dmub_command_table = true,
707 .enable_mem_low_power = {
708 .bits = {
709 .vga = false,
710 .i2c = false,
711 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
712 .dscl = false,
713 .cm = false,
714 .mpc = false,
715 .optc = true,
716 }
717 },
718 .use_max_lb = true,
719 .force_disable_subvp = false,
720 .exit_idle_opt_for_cursor_updates = true,
721 .using_dml2 = false,
722 .using_dml21 = false, // TODO : Temporary for N-1 validation. Remove after N-1 is done.
723 .enable_single_display_2to1_odm_policy = true,
724
725 /* Must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions*/
726 .enable_double_buffered_dsc_pg_support = true,
727 .enable_dp_dig_pixel_rate_div_policy = 1,
728 .allow_sw_cursor_fallback = false, // Linux can't do SW cursor "fallback"
729 .alloc_extra_way_for_cursor = true,
730 .min_prefetch_in_strobe_ns = 60000, // 60us
731 .disable_unbounded_requesting = false,
732 .override_dispclk_programming = true,
733 .disable_fpo_optimizations = false,
734 .fpo_vactive_margin_us = 2000, // 2000us
735 .disable_fpo_vactive = false,
736 .disable_boot_optimizations = false,
737 .disable_subvp_high_refresh = false,
738 .disable_dp_plus_plus_wa = true,
739 .fpo_vactive_min_active_margin_us = 200,
740 .fpo_vactive_max_blank_us = 1000,
741 .enable_legacy_fast_update = false,
742 };
743
dcn32_aux_engine_create(struct dc_context * ctx,uint32_t inst)744 static struct dce_aux *dcn32_aux_engine_create(
745 struct dc_context *ctx,
746 uint32_t inst)
747 {
748 struct aux_engine_dce110 *aux_engine =
749 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
750
751 if (!aux_engine)
752 return NULL;
753
754 #undef REG_STRUCT
755 #define REG_STRUCT aux_engine_regs
756 aux_engine_regs_init(0),
757 aux_engine_regs_init(1),
758 aux_engine_regs_init(2),
759 aux_engine_regs_init(3),
760 aux_engine_regs_init(4);
761
762 dce110_aux_engine_construct(aux_engine, ctx, inst,
763 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
764 &aux_engine_regs[inst],
765 &aux_mask,
766 &aux_shift,
767 ctx->dc->caps.extended_aux_timeout_support);
768
769 return &aux_engine->base;
770 }
771 #define i2c_inst_regs_init(id)\
772 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
773
774 static struct dce_i2c_registers i2c_hw_regs[5];
775
776 static const struct dce_i2c_shift i2c_shifts = {
777 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
778 };
779
780 static const struct dce_i2c_mask i2c_masks = {
781 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
782 };
783
dcn32_i2c_hw_create(struct dc_context * ctx,uint32_t inst)784 static struct dce_i2c_hw *dcn32_i2c_hw_create(
785 struct dc_context *ctx,
786 uint32_t inst)
787 {
788 struct dce_i2c_hw *dce_i2c_hw =
789 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
790
791 if (!dce_i2c_hw)
792 return NULL;
793
794 #undef REG_STRUCT
795 #define REG_STRUCT i2c_hw_regs
796 i2c_inst_regs_init(1),
797 i2c_inst_regs_init(2),
798 i2c_inst_regs_init(3),
799 i2c_inst_regs_init(4),
800 i2c_inst_regs_init(5);
801
802 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
803 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
804
805 return dce_i2c_hw;
806 }
807
dcn32_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)808 static struct clock_source *dcn32_clock_source_create(
809 struct dc_context *ctx,
810 struct dc_bios *bios,
811 enum clock_source_id id,
812 const struct dce110_clk_src_regs *regs,
813 bool dp_clk_src)
814 {
815 struct dce110_clk_src *clk_src =
816 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
817
818 if (!clk_src)
819 return NULL;
820
821 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
822 regs, &cs_shift, &cs_mask)) {
823 clk_src->base.dp_clk_src = dp_clk_src;
824 return &clk_src->base;
825 }
826
827 kfree(clk_src);
828 BREAK_TO_DEBUGGER();
829 return NULL;
830 }
831
dcn32_hubbub_create(struct dc_context * ctx)832 static struct hubbub *dcn32_hubbub_create(struct dc_context *ctx)
833 {
834 int i;
835
836 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
837 GFP_KERNEL);
838
839 if (!hubbub2)
840 return NULL;
841
842 #undef REG_STRUCT
843 #define REG_STRUCT hubbub_reg
844 hubbub_reg_init();
845
846 #undef REG_STRUCT
847 #define REG_STRUCT vmid_regs
848 vmid_regs_init(0),
849 vmid_regs_init(1),
850 vmid_regs_init(2),
851 vmid_regs_init(3),
852 vmid_regs_init(4),
853 vmid_regs_init(5),
854 vmid_regs_init(6),
855 vmid_regs_init(7),
856 vmid_regs_init(8),
857 vmid_regs_init(9),
858 vmid_regs_init(10),
859 vmid_regs_init(11),
860 vmid_regs_init(12),
861 vmid_regs_init(13),
862 vmid_regs_init(14),
863 vmid_regs_init(15);
864
865 hubbub32_construct(hubbub2, ctx,
866 &hubbub_reg,
867 &hubbub_shift,
868 &hubbub_mask,
869 ctx->dc->dml.ip.det_buffer_size_kbytes,
870 ctx->dc->dml.ip.pixel_chunk_size_kbytes,
871 ctx->dc->dml.ip.config_return_buffer_size_in_kbytes);
872
873
874 for (i = 0; i < res_cap_dcn32.num_vmid; i++) {
875 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
876
877 vmid->ctx = ctx;
878
879 vmid->regs = &vmid_regs[i];
880 vmid->shifts = &vmid_shifts;
881 vmid->masks = &vmid_masks;
882 }
883
884 return &hubbub2->base;
885 }
886
dcn32_hubp_create(struct dc_context * ctx,uint32_t inst)887 static struct hubp *dcn32_hubp_create(
888 struct dc_context *ctx,
889 uint32_t inst)
890 {
891 struct dcn20_hubp *hubp2 =
892 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
893
894 if (!hubp2)
895 return NULL;
896
897 #undef REG_STRUCT
898 #define REG_STRUCT hubp_regs
899 hubp_regs_init(0),
900 hubp_regs_init(1),
901 hubp_regs_init(2),
902 hubp_regs_init(3);
903
904 if (hubp32_construct(hubp2, ctx, inst,
905 &hubp_regs[inst], &hubp_shift, &hubp_mask))
906 return &hubp2->base;
907
908 BREAK_TO_DEBUGGER();
909 kfree(hubp2);
910 return NULL;
911 }
912
dcn32_dpp_destroy(struct dpp ** dpp)913 static void dcn32_dpp_destroy(struct dpp **dpp)
914 {
915 kfree(TO_DCN30_DPP(*dpp));
916 *dpp = NULL;
917 }
918
dcn32_dpp_create(struct dc_context * ctx,uint32_t inst)919 static struct dpp *dcn32_dpp_create(
920 struct dc_context *ctx,
921 uint32_t inst)
922 {
923 struct dcn3_dpp *dpp3 =
924 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
925
926 if (!dpp3)
927 return NULL;
928
929 #undef REG_STRUCT
930 #define REG_STRUCT dpp_regs
931 dpp_regs_init(0),
932 dpp_regs_init(1),
933 dpp_regs_init(2),
934 dpp_regs_init(3);
935
936 if (dpp32_construct(dpp3, ctx, inst,
937 &dpp_regs[inst], &tf_shift, &tf_mask))
938 return &dpp3->base;
939
940 BREAK_TO_DEBUGGER();
941 kfree(dpp3);
942 return NULL;
943 }
944
dcn32_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)945 static struct mpc *dcn32_mpc_create(
946 struct dc_context *ctx,
947 int num_mpcc,
948 int num_rmu)
949 {
950 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
951 GFP_KERNEL);
952
953 if (!mpc30)
954 return NULL;
955
956 #undef REG_STRUCT
957 #define REG_STRUCT mpc_regs
958 dcn_mpc_regs_init();
959
960 dcn32_mpc_construct(mpc30, ctx,
961 &mpc_regs,
962 &mpc_shift,
963 &mpc_mask,
964 num_mpcc,
965 num_rmu);
966
967 return &mpc30->base;
968 }
969
dcn32_opp_create(struct dc_context * ctx,uint32_t inst)970 static struct output_pixel_processor *dcn32_opp_create(
971 struct dc_context *ctx, uint32_t inst)
972 {
973 struct dcn20_opp *opp2 =
974 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
975
976 if (!opp2) {
977 BREAK_TO_DEBUGGER();
978 return NULL;
979 }
980
981 #undef REG_STRUCT
982 #define REG_STRUCT opp_regs
983 opp_regs_init(0),
984 opp_regs_init(1),
985 opp_regs_init(2),
986 opp_regs_init(3);
987
988 dcn20_opp_construct(opp2, ctx, inst,
989 &opp_regs[inst], &opp_shift, &opp_mask);
990 return &opp2->base;
991 }
992
993
dcn32_timing_generator_create(struct dc_context * ctx,uint32_t instance)994 static struct timing_generator *dcn32_timing_generator_create(
995 struct dc_context *ctx,
996 uint32_t instance)
997 {
998 struct optc *tgn10 =
999 kzalloc(sizeof(struct optc), GFP_KERNEL);
1000
1001 if (!tgn10)
1002 return NULL;
1003
1004 #undef REG_STRUCT
1005 #define REG_STRUCT optc_regs
1006 optc_regs_init(0),
1007 optc_regs_init(1),
1008 optc_regs_init(2),
1009 optc_regs_init(3);
1010
1011 tgn10->base.inst = instance;
1012 tgn10->base.ctx = ctx;
1013
1014 tgn10->tg_regs = &optc_regs[instance];
1015 tgn10->tg_shift = &optc_shift;
1016 tgn10->tg_mask = &optc_mask;
1017
1018 dcn32_timing_generator_init(tgn10);
1019
1020 return &tgn10->base;
1021 }
1022
1023 static const struct encoder_feature_support link_enc_feature = {
1024 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1025 .max_hdmi_pixel_clock = 600000,
1026 .hdmi_ycbcr420_supported = true,
1027 .dp_ycbcr420_supported = true,
1028 .fec_supported = true,
1029 .flags.bits.IS_HBR2_CAPABLE = true,
1030 .flags.bits.IS_HBR3_CAPABLE = true,
1031 .flags.bits.IS_TPS3_CAPABLE = true,
1032 .flags.bits.IS_TPS4_CAPABLE = true
1033 };
1034
dcn32_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1035 static struct link_encoder *dcn32_link_encoder_create(
1036 struct dc_context *ctx,
1037 const struct encoder_init_data *enc_init_data)
1038 {
1039 struct dcn20_link_encoder *enc20 =
1040 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1041
1042 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs))
1043 return NULL;
1044
1045 #undef REG_STRUCT
1046 #define REG_STRUCT link_enc_aux_regs
1047 aux_regs_init(0),
1048 aux_regs_init(1),
1049 aux_regs_init(2),
1050 aux_regs_init(3),
1051 aux_regs_init(4);
1052
1053 #undef REG_STRUCT
1054 #define REG_STRUCT link_enc_hpd_regs
1055 hpd_regs_init(0),
1056 hpd_regs_init(1),
1057 hpd_regs_init(2),
1058 hpd_regs_init(3),
1059 hpd_regs_init(4);
1060
1061 #undef REG_STRUCT
1062 #define REG_STRUCT link_enc_regs
1063 link_regs_init(0, A),
1064 link_regs_init(1, B),
1065 link_regs_init(2, C),
1066 link_regs_init(3, D),
1067 link_regs_init(4, E);
1068
1069 dcn32_link_encoder_construct(enc20,
1070 enc_init_data,
1071 &link_enc_feature,
1072 &link_enc_regs[enc_init_data->transmitter],
1073 &link_enc_aux_regs[enc_init_data->channel - 1],
1074 &link_enc_hpd_regs[enc_init_data->hpd_source],
1075 &le_shift,
1076 &le_mask);
1077
1078 return &enc20->enc10.base;
1079 }
1080
dcn32_panel_cntl_create(const struct panel_cntl_init_data * init_data)1081 struct panel_cntl *dcn32_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1082 {
1083 struct dcn31_panel_cntl *panel_cntl =
1084 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1085
1086 if (!panel_cntl)
1087 return NULL;
1088
1089 dcn31_panel_cntl_construct(panel_cntl, init_data);
1090
1091 return &panel_cntl->base;
1092 }
1093
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1094 static void read_dce_straps(
1095 struct dc_context *ctx,
1096 struct resource_straps *straps)
1097 {
1098 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1099 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1100
1101 }
1102
dcn32_create_audio(struct dc_context * ctx,unsigned int inst)1103 static struct audio *dcn32_create_audio(
1104 struct dc_context *ctx, unsigned int inst)
1105 {
1106
1107 #undef REG_STRUCT
1108 #define REG_STRUCT audio_regs
1109 audio_regs_init(0),
1110 audio_regs_init(1),
1111 audio_regs_init(2),
1112 audio_regs_init(3),
1113 audio_regs_init(4);
1114
1115 return dce_audio_create(ctx, inst,
1116 &audio_regs[inst], &audio_shift, &audio_mask);
1117 }
1118
dcn32_vpg_create(struct dc_context * ctx,uint32_t inst)1119 static struct vpg *dcn32_vpg_create(
1120 struct dc_context *ctx,
1121 uint32_t inst)
1122 {
1123 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1124
1125 if (!vpg3)
1126 return NULL;
1127
1128 #undef REG_STRUCT
1129 #define REG_STRUCT vpg_regs
1130 vpg_regs_init(0),
1131 vpg_regs_init(1),
1132 vpg_regs_init(2),
1133 vpg_regs_init(3),
1134 vpg_regs_init(4),
1135 vpg_regs_init(5),
1136 vpg_regs_init(6),
1137 vpg_regs_init(7),
1138 vpg_regs_init(8),
1139 vpg_regs_init(9);
1140
1141 vpg3_construct(vpg3, ctx, inst,
1142 &vpg_regs[inst],
1143 &vpg_shift,
1144 &vpg_mask);
1145
1146 return &vpg3->base;
1147 }
1148
dcn32_afmt_create(struct dc_context * ctx,uint32_t inst)1149 static struct afmt *dcn32_afmt_create(
1150 struct dc_context *ctx,
1151 uint32_t inst)
1152 {
1153 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1154
1155 if (!afmt3)
1156 return NULL;
1157
1158 #undef REG_STRUCT
1159 #define REG_STRUCT afmt_regs
1160 afmt_regs_init(0),
1161 afmt_regs_init(1),
1162 afmt_regs_init(2),
1163 afmt_regs_init(3),
1164 afmt_regs_init(4),
1165 afmt_regs_init(5);
1166
1167 afmt3_construct(afmt3, ctx, inst,
1168 &afmt_regs[inst],
1169 &afmt_shift,
1170 &afmt_mask);
1171
1172 return &afmt3->base;
1173 }
1174
dcn31_apg_create(struct dc_context * ctx,uint32_t inst)1175 static struct apg *dcn31_apg_create(
1176 struct dc_context *ctx,
1177 uint32_t inst)
1178 {
1179 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1180
1181 if (!apg31)
1182 return NULL;
1183
1184 #undef REG_STRUCT
1185 #define REG_STRUCT apg_regs
1186 apg_regs_init(0),
1187 apg_regs_init(1),
1188 apg_regs_init(2),
1189 apg_regs_init(3);
1190
1191 apg31_construct(apg31, ctx, inst,
1192 &apg_regs[inst],
1193 &apg_shift,
1194 &apg_mask);
1195
1196 return &apg31->base;
1197 }
1198
dcn32_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1199 static struct stream_encoder *dcn32_stream_encoder_create(
1200 enum engine_id eng_id,
1201 struct dc_context *ctx)
1202 {
1203 struct dcn10_stream_encoder *enc1;
1204 struct vpg *vpg;
1205 struct afmt *afmt;
1206 int vpg_inst;
1207 int afmt_inst;
1208
1209 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1210 if (eng_id <= ENGINE_ID_DIGF) {
1211 vpg_inst = eng_id;
1212 afmt_inst = eng_id;
1213 } else
1214 return NULL;
1215
1216 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1217 vpg = dcn32_vpg_create(ctx, vpg_inst);
1218 afmt = dcn32_afmt_create(ctx, afmt_inst);
1219
1220 if (!enc1 || !vpg || !afmt) {
1221 kfree(enc1);
1222 kfree(vpg);
1223 kfree(afmt);
1224 return NULL;
1225 }
1226
1227 #undef REG_STRUCT
1228 #define REG_STRUCT stream_enc_regs
1229 stream_enc_regs_init(0),
1230 stream_enc_regs_init(1),
1231 stream_enc_regs_init(2),
1232 stream_enc_regs_init(3),
1233 stream_enc_regs_init(4);
1234
1235 dcn32_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1236 eng_id, vpg, afmt,
1237 &stream_enc_regs[eng_id],
1238 &se_shift, &se_mask);
1239
1240 return &enc1->base;
1241 }
1242
dcn32_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1243 static struct hpo_dp_stream_encoder *dcn32_hpo_dp_stream_encoder_create(
1244 enum engine_id eng_id,
1245 struct dc_context *ctx)
1246 {
1247 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1248 struct vpg *vpg;
1249 struct apg *apg;
1250 uint32_t hpo_dp_inst;
1251 uint32_t vpg_inst;
1252 uint32_t apg_inst;
1253
1254 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1255 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1256
1257 /* Mapping of VPG register blocks to HPO DP block instance:
1258 * VPG[6] -> HPO_DP[0]
1259 * VPG[7] -> HPO_DP[1]
1260 * VPG[8] -> HPO_DP[2]
1261 * VPG[9] -> HPO_DP[3]
1262 */
1263 vpg_inst = hpo_dp_inst + 6;
1264
1265 /* Mapping of APG register blocks to HPO DP block instance:
1266 * APG[0] -> HPO_DP[0]
1267 * APG[1] -> HPO_DP[1]
1268 * APG[2] -> HPO_DP[2]
1269 * APG[3] -> HPO_DP[3]
1270 */
1271 apg_inst = hpo_dp_inst;
1272
1273 /* allocate HPO stream encoder and create VPG sub-block */
1274 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1275 vpg = dcn32_vpg_create(ctx, vpg_inst);
1276 apg = dcn31_apg_create(ctx, apg_inst);
1277
1278 if (!hpo_dp_enc31 || !vpg || !apg) {
1279 kfree(hpo_dp_enc31);
1280 kfree(vpg);
1281 kfree(apg);
1282 return NULL;
1283 }
1284
1285 #undef REG_STRUCT
1286 #define REG_STRUCT hpo_dp_stream_enc_regs
1287 hpo_dp_stream_encoder_reg_init(0),
1288 hpo_dp_stream_encoder_reg_init(1),
1289 hpo_dp_stream_encoder_reg_init(2),
1290 hpo_dp_stream_encoder_reg_init(3);
1291
1292 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1293 hpo_dp_inst, eng_id, vpg, apg,
1294 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1295 &hpo_dp_se_shift, &hpo_dp_se_mask);
1296
1297 return &hpo_dp_enc31->base;
1298 }
1299
dcn32_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1300 static struct hpo_dp_link_encoder *dcn32_hpo_dp_link_encoder_create(
1301 uint8_t inst,
1302 struct dc_context *ctx)
1303 {
1304 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1305
1306 /* allocate HPO link encoder */
1307 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1308 if (!hpo_dp_enc31)
1309 return NULL; /* out of memory */
1310
1311 #undef REG_STRUCT
1312 #define REG_STRUCT hpo_dp_link_enc_regs
1313 hpo_dp_link_encoder_reg_init(0),
1314 hpo_dp_link_encoder_reg_init(1);
1315
1316 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1317 &hpo_dp_link_enc_regs[inst],
1318 &hpo_dp_le_shift, &hpo_dp_le_mask);
1319
1320 return &hpo_dp_enc31->base;
1321 }
1322
dcn32_hwseq_create(struct dc_context * ctx)1323 static struct dce_hwseq *dcn32_hwseq_create(
1324 struct dc_context *ctx)
1325 {
1326 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1327
1328 #undef REG_STRUCT
1329 #define REG_STRUCT hwseq_reg
1330 hwseq_reg_init();
1331
1332 if (hws) {
1333 hws->ctx = ctx;
1334 hws->regs = &hwseq_reg;
1335 hws->shifts = &hwseq_shift;
1336 hws->masks = &hwseq_mask;
1337 }
1338 return hws;
1339 }
1340 static const struct resource_create_funcs res_create_funcs = {
1341 .read_dce_straps = read_dce_straps,
1342 .create_audio = dcn32_create_audio,
1343 .create_stream_encoder = dcn32_stream_encoder_create,
1344 .create_hpo_dp_stream_encoder = dcn32_hpo_dp_stream_encoder_create,
1345 .create_hpo_dp_link_encoder = dcn32_hpo_dp_link_encoder_create,
1346 .create_hwseq = dcn32_hwseq_create,
1347 };
1348
dcn32_resource_destruct(struct dcn32_resource_pool * pool)1349 static void dcn32_resource_destruct(struct dcn32_resource_pool *pool)
1350 {
1351 unsigned int i;
1352
1353 for (i = 0; i < pool->base.stream_enc_count; i++) {
1354 if (pool->base.stream_enc[i] != NULL) {
1355 if (pool->base.stream_enc[i]->vpg != NULL) {
1356 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1357 pool->base.stream_enc[i]->vpg = NULL;
1358 }
1359 if (pool->base.stream_enc[i]->afmt != NULL) {
1360 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1361 pool->base.stream_enc[i]->afmt = NULL;
1362 }
1363 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1364 pool->base.stream_enc[i] = NULL;
1365 }
1366 }
1367
1368 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1369 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1370 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1371 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1372 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1373 }
1374 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1375 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1376 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1377 }
1378 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1379 pool->base.hpo_dp_stream_enc[i] = NULL;
1380 }
1381 }
1382
1383 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1384 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1385 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1386 pool->base.hpo_dp_link_enc[i] = NULL;
1387 }
1388 }
1389
1390 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1391 if (pool->base.dscs[i] != NULL)
1392 dcn20_dsc_destroy(&pool->base.dscs[i]);
1393 }
1394
1395 if (pool->base.mpc != NULL) {
1396 kfree(TO_DCN20_MPC(pool->base.mpc));
1397 pool->base.mpc = NULL;
1398 }
1399 if (pool->base.hubbub != NULL) {
1400 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1401 pool->base.hubbub = NULL;
1402 }
1403 for (i = 0; i < pool->base.pipe_count; i++) {
1404 if (pool->base.dpps[i] != NULL)
1405 dcn32_dpp_destroy(&pool->base.dpps[i]);
1406
1407 if (pool->base.ipps[i] != NULL)
1408 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1409
1410 if (pool->base.hubps[i] != NULL) {
1411 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1412 pool->base.hubps[i] = NULL;
1413 }
1414
1415 if (pool->base.irqs != NULL) {
1416 dal_irq_service_destroy(&pool->base.irqs);
1417 }
1418 }
1419
1420 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1421 if (pool->base.engines[i] != NULL)
1422 dce110_engine_destroy(&pool->base.engines[i]);
1423 if (pool->base.hw_i2cs[i] != NULL) {
1424 kfree(pool->base.hw_i2cs[i]);
1425 pool->base.hw_i2cs[i] = NULL;
1426 }
1427 if (pool->base.sw_i2cs[i] != NULL) {
1428 kfree(pool->base.sw_i2cs[i]);
1429 pool->base.sw_i2cs[i] = NULL;
1430 }
1431 }
1432
1433 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1434 if (pool->base.opps[i] != NULL)
1435 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1436 }
1437
1438 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1439 if (pool->base.timing_generators[i] != NULL) {
1440 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1441 pool->base.timing_generators[i] = NULL;
1442 }
1443 }
1444
1445 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1446 if (pool->base.dwbc[i] != NULL) {
1447 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1448 pool->base.dwbc[i] = NULL;
1449 }
1450 if (pool->base.mcif_wb[i] != NULL) {
1451 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1452 pool->base.mcif_wb[i] = NULL;
1453 }
1454 }
1455
1456 for (i = 0; i < pool->base.audio_count; i++) {
1457 if (pool->base.audios[i])
1458 dce_aud_destroy(&pool->base.audios[i]);
1459 }
1460
1461 for (i = 0; i < pool->base.clk_src_count; i++) {
1462 if (pool->base.clock_sources[i] != NULL) {
1463 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1464 pool->base.clock_sources[i] = NULL;
1465 }
1466 }
1467
1468 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1469 if (pool->base.mpc_lut[i] != NULL) {
1470 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1471 pool->base.mpc_lut[i] = NULL;
1472 }
1473 if (pool->base.mpc_shaper[i] != NULL) {
1474 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1475 pool->base.mpc_shaper[i] = NULL;
1476 }
1477 }
1478
1479 if (pool->base.dp_clock_source != NULL) {
1480 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1481 pool->base.dp_clock_source = NULL;
1482 }
1483
1484 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1485 if (pool->base.multiple_abms[i] != NULL)
1486 dce_abm_destroy(&pool->base.multiple_abms[i]);
1487 }
1488
1489 if (pool->base.psr != NULL)
1490 dmub_psr_destroy(&pool->base.psr);
1491
1492 if (pool->base.dccg != NULL)
1493 dcn_dccg_destroy(&pool->base.dccg);
1494
1495 if (pool->base.oem_device != NULL) {
1496 struct dc *dc = pool->base.oem_device->ctx->dc;
1497
1498 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1499 }
1500 }
1501
1502
dcn32_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1503 static bool dcn32_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1504 {
1505 int i;
1506 uint32_t dwb_count = pool->res_cap->num_dwb;
1507
1508 for (i = 0; i < dwb_count; i++) {
1509 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1510 GFP_KERNEL);
1511
1512 if (!dwbc30) {
1513 dm_error("DC: failed to create dwbc30!\n");
1514 return false;
1515 }
1516
1517 #undef REG_STRUCT
1518 #define REG_STRUCT dwbc30_regs
1519 dwbc_regs_dcn3_init(0);
1520
1521 dcn30_dwbc_construct(dwbc30, ctx,
1522 &dwbc30_regs[i],
1523 &dwbc30_shift,
1524 &dwbc30_mask,
1525 i);
1526
1527 pool->dwbc[i] = &dwbc30->base;
1528 }
1529 return true;
1530 }
1531
dcn32_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1532 static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1533 {
1534 int i;
1535 uint32_t dwb_count = pool->res_cap->num_dwb;
1536
1537 for (i = 0; i < dwb_count; i++) {
1538 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1539 GFP_KERNEL);
1540
1541 if (!mcif_wb30) {
1542 dm_error("DC: failed to create mcif_wb30!\n");
1543 return false;
1544 }
1545
1546 #undef REG_STRUCT
1547 #define REG_STRUCT mcif_wb30_regs
1548 mcif_wb_regs_dcn3_init(0);
1549
1550 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1551 &mcif_wb30_regs[i],
1552 &mcif_wb30_shift,
1553 &mcif_wb30_mask,
1554 i);
1555
1556 pool->mcif_wb[i] = &mcif_wb30->base;
1557 }
1558 return true;
1559 }
1560
dcn32_dsc_create(struct dc_context * ctx,uint32_t inst)1561 static struct display_stream_compressor *dcn32_dsc_create(
1562 struct dc_context *ctx, uint32_t inst)
1563 {
1564 struct dcn20_dsc *dsc =
1565 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1566
1567 if (!dsc) {
1568 BREAK_TO_DEBUGGER();
1569 return NULL;
1570 }
1571
1572 #undef REG_STRUCT
1573 #define REG_STRUCT dsc_regs
1574 dsc_regsDCN20_init(0),
1575 dsc_regsDCN20_init(1),
1576 dsc_regsDCN20_init(2),
1577 dsc_regsDCN20_init(3);
1578
1579 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1580
1581 dsc->max_image_width = 6016;
1582
1583 return &dsc->base;
1584 }
1585
dcn32_destroy_resource_pool(struct resource_pool ** pool)1586 static void dcn32_destroy_resource_pool(struct resource_pool **pool)
1587 {
1588 struct dcn32_resource_pool *dcn32_pool = TO_DCN32_RES_POOL(*pool);
1589
1590 dcn32_resource_destruct(dcn32_pool);
1591 kfree(dcn32_pool);
1592 *pool = NULL;
1593 }
1594
dcn32_acquire_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,int mpcc_id,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1595 bool dcn32_acquire_post_bldn_3dlut(
1596 struct resource_context *res_ctx,
1597 const struct resource_pool *pool,
1598 int mpcc_id,
1599 struct dc_3dlut **lut,
1600 struct dc_transfer_func **shaper)
1601 {
1602 bool ret = false;
1603
1604 ASSERT(*lut == NULL && *shaper == NULL);
1605 *lut = NULL;
1606 *shaper = NULL;
1607
1608 if (!res_ctx->is_mpc_3dlut_acquired[mpcc_id]) {
1609 *lut = pool->mpc_lut[mpcc_id];
1610 *shaper = pool->mpc_shaper[mpcc_id];
1611 res_ctx->is_mpc_3dlut_acquired[mpcc_id] = true;
1612 ret = true;
1613 }
1614 return ret;
1615 }
1616
dcn32_release_post_bldn_3dlut(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_3dlut ** lut,struct dc_transfer_func ** shaper)1617 bool dcn32_release_post_bldn_3dlut(
1618 struct resource_context *res_ctx,
1619 const struct resource_pool *pool,
1620 struct dc_3dlut **lut,
1621 struct dc_transfer_func **shaper)
1622 {
1623 int i;
1624 bool ret = false;
1625
1626 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1627 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1628 res_ctx->is_mpc_3dlut_acquired[i] = false;
1629 pool->mpc_lut[i]->state.raw = 0;
1630 *lut = NULL;
1631 *shaper = NULL;
1632 ret = true;
1633 break;
1634 }
1635 }
1636 return ret;
1637 }
1638
dcn32_enable_phantom_plane(struct dc * dc,struct dc_state * context,struct dc_stream_state * phantom_stream,unsigned int dc_pipe_idx)1639 static void dcn32_enable_phantom_plane(struct dc *dc,
1640 struct dc_state *context,
1641 struct dc_stream_state *phantom_stream,
1642 unsigned int dc_pipe_idx)
1643 {
1644 struct dc_plane_state *phantom_plane = NULL;
1645 struct dc_plane_state *prev_phantom_plane = NULL;
1646 struct pipe_ctx *curr_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1647
1648 while (curr_pipe) {
1649 if (curr_pipe->top_pipe && curr_pipe->top_pipe->plane_state == curr_pipe->plane_state)
1650 phantom_plane = prev_phantom_plane;
1651 else
1652 phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);
1653
1654 if (!phantom_plane)
1655 continue;
1656
1657 memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
1658 memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
1659 sizeof(phantom_plane->scaling_quality));
1660 memcpy(&phantom_plane->src_rect, &curr_pipe->plane_state->src_rect, sizeof(phantom_plane->src_rect));
1661 memcpy(&phantom_plane->dst_rect, &curr_pipe->plane_state->dst_rect, sizeof(phantom_plane->dst_rect));
1662 memcpy(&phantom_plane->clip_rect, &curr_pipe->plane_state->clip_rect, sizeof(phantom_plane->clip_rect));
1663 memcpy(&phantom_plane->plane_size, &curr_pipe->plane_state->plane_size,
1664 sizeof(phantom_plane->plane_size));
1665 memcpy(&phantom_plane->tiling_info, &curr_pipe->plane_state->tiling_info,
1666 sizeof(phantom_plane->tiling_info));
1667 memcpy(&phantom_plane->dcc, &curr_pipe->plane_state->dcc, sizeof(phantom_plane->dcc));
1668 phantom_plane->format = curr_pipe->plane_state->format;
1669 phantom_plane->rotation = curr_pipe->plane_state->rotation;
1670 phantom_plane->visible = curr_pipe->plane_state->visible;
1671
1672 /* Shadow pipe has small viewport. */
1673 phantom_plane->clip_rect.y = 0;
1674 phantom_plane->clip_rect.height = phantom_stream->src.height;
1675
1676 dc_state_add_phantom_plane(dc, phantom_stream, phantom_plane, context);
1677
1678 curr_pipe = curr_pipe->bottom_pipe;
1679 prev_phantom_plane = phantom_plane;
1680 }
1681 }
1682
dcn32_enable_phantom_stream(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int dc_pipe_idx)1683 static struct dc_stream_state *dcn32_enable_phantom_stream(struct dc *dc,
1684 struct dc_state *context,
1685 display_e2e_pipe_params_st *pipes,
1686 unsigned int pipe_cnt,
1687 unsigned int dc_pipe_idx)
1688 {
1689 struct dc_stream_state *phantom_stream = NULL;
1690 struct pipe_ctx *ref_pipe = &context->res_ctx.pipe_ctx[dc_pipe_idx];
1691
1692 phantom_stream = dc_state_create_phantom_stream(dc, context, ref_pipe->stream);
1693 if (!phantom_stream)
1694 return phantom_stream;
1695
1696 /* stream has limited viewport and small timing */
1697 memcpy(&phantom_stream->timing, &ref_pipe->stream->timing, sizeof(phantom_stream->timing));
1698 memcpy(&phantom_stream->src, &ref_pipe->stream->src, sizeof(phantom_stream->src));
1699 memcpy(&phantom_stream->dst, &ref_pipe->stream->dst, sizeof(phantom_stream->dst));
1700 DC_FP_START();
1701 dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_idx);
1702 DC_FP_END();
1703
1704 dc_state_add_phantom_stream(dc, context, phantom_stream, ref_pipe->stream);
1705 return phantom_stream;
1706 }
1707
1708 /* TODO: Input to this function should indicate which pipe indexes (or streams)
1709 * require a phantom pipe / stream
1710 */
dcn32_add_phantom_pipes(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,unsigned int pipe_cnt,unsigned int index)1711 void dcn32_add_phantom_pipes(struct dc *dc, struct dc_state *context,
1712 display_e2e_pipe_params_st *pipes,
1713 unsigned int pipe_cnt,
1714 unsigned int index)
1715 {
1716 struct dc_stream_state *phantom_stream = NULL;
1717 unsigned int i;
1718
1719 // The index of the DC pipe passed into this function is guarenteed to
1720 // be a valid candidate for SubVP (i.e. has a plane, stream, doesn't
1721 // already have phantom pipe assigned, etc.) by previous checks.
1722 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index);
1723 if (!phantom_stream)
1724 return;
1725
1726 dcn32_enable_phantom_plane(dc, context, phantom_stream, index);
1727
1728 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1729 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1730
1731 // Build scaling params for phantom pipes which were newly added.
1732 // We determine which phantom pipes were added by comparing with
1733 // the phantom stream.
1734 if (pipe->plane_state && pipe->stream && pipe->stream == phantom_stream &&
1735 dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) {
1736 pipe->stream->use_dynamic_meta = false;
1737 pipe->plane_state->flip_immediate = false;
1738 if (!resource_build_scaling_params(pipe)) {
1739 // Log / remove phantom pipes since failed to build scaling params
1740 }
1741 }
1742 }
1743 }
1744
dml1_validate(struct dc * dc,struct dc_state * context,bool fast_validate)1745 static bool dml1_validate(struct dc *dc, struct dc_state *context, bool fast_validate)
1746 {
1747 bool out = false;
1748
1749 BW_VAL_TRACE_SETUP();
1750
1751 int vlevel = 0;
1752 int pipe_cnt = 0;
1753 display_e2e_pipe_params_st *pipes = kcalloc(dc->res_pool->pipe_count,
1754 sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1755
1756 /* To handle Freesync properly, setting FreeSync DML parameters
1757 * to its default state for the first stage of validation
1758 */
1759 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;
1760 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
1761
1762 DC_LOGGER_INIT(dc->ctx->logger);
1763
1764 BW_VAL_TRACE_COUNT();
1765
1766 if (!pipes)
1767 goto validate_fail;
1768
1769 DC_FP_START();
1770 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
1771 DC_FP_END();
1772
1773 if (pipe_cnt == 0)
1774 goto validate_out;
1775
1776 if (!out)
1777 goto validate_fail;
1778
1779 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1780
1781 if (fast_validate) {
1782 BW_VAL_TRACE_SKIP(fast);
1783 goto validate_out;
1784 }
1785
1786 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
1787
1788 dcn32_override_min_req_memclk(dc, context);
1789 dcn32_override_min_req_dcfclk(dc, context);
1790
1791 BW_VAL_TRACE_END_WATERMARKS();
1792
1793 goto validate_out;
1794
1795 validate_fail:
1796 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1797 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1798
1799 BW_VAL_TRACE_SKIP(fail);
1800 out = false;
1801
1802 validate_out:
1803 kfree(pipes);
1804
1805 BW_VAL_TRACE_FINISH();
1806
1807 return out;
1808 }
1809
dcn32_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1810 enum dc_status dcn32_validate_bandwidth(struct dc *dc,
1811 struct dc_state *context,
1812 bool fast_validate)
1813 {
1814 unsigned int i;
1815 enum dc_status status;
1816 const struct dc_stream_state *stream;
1817
1818 /* reset cursor limitations on subvp */
1819 for (i = 0; i < context->stream_count; i++) {
1820 stream = context->streams[i];
1821
1822 if (dc_state_can_clear_stream_cursor_subvp_limit(stream, context)) {
1823 dc_state_set_stream_cursor_subvp_limit(stream, context, false);
1824 }
1825 }
1826
1827 if (dc->debug.using_dml2)
1828 status = dml2_validate(dc, context,
1829 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1830 fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1831 else
1832 status = dml1_validate(dc, context, fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1833
1834 if (!fast_validate && status == DC_OK && dc_state_is_subvp_in_use(context)) {
1835 /* check new stream configuration still supports cursor if subvp used */
1836 for (i = 0; i < context->stream_count; i++) {
1837 stream = context->streams[i];
1838
1839 if (dc_state_get_stream_subvp_type(context, stream) != SUBVP_PHANTOM &&
1840 stream->cursor_position.enable &&
1841 !dc_stream_check_cursor_attributes(stream, context, &stream->cursor_attributes)) {
1842 /* hw cursor cannot be supported with subvp active, so disable subvp for now */
1843 dc_state_set_stream_cursor_subvp_limit(stream, context, true);
1844 status = DC_FAIL_HW_CURSOR_SUPPORT;
1845 }
1846 };
1847 }
1848
1849 if (!fast_validate && status == DC_FAIL_HW_CURSOR_SUPPORT) {
1850 /* attempt to validate again with subvp disabled due to cursor */
1851 if (dc->debug.using_dml2)
1852 status = dml2_validate(dc, context,
1853 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1854 fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1855 else
1856 status = dml1_validate(dc, context, fast_validate) ? DC_OK : DC_FAIL_BANDWIDTH_VALIDATE;
1857 }
1858
1859 return status;
1860 }
1861
dcn32_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1862 int dcn32_populate_dml_pipes_from_context(
1863 struct dc *dc, struct dc_state *context,
1864 display_e2e_pipe_params_st *pipes,
1865 bool fast_validate)
1866 {
1867 int i, pipe_cnt;
1868 struct resource_context *res_ctx = &context->res_ctx;
1869 struct pipe_ctx *pipe = NULL;
1870 bool subvp_in_use = false;
1871 struct dc_crtc_timing *timing;
1872 int subvp_main_pipe_index = -1;
1873 enum mall_stream_type mall_type;
1874 bool single_display_subvp = false;
1875 struct dc_stream_state *stream = NULL;
1876 int num_subvp_main = 0;
1877 int num_subvp_phantom = 0;
1878 int num_subvp_none = 0;
1879 int odm_slice_count;
1880
1881 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1882
1883 /* For single display subvp, look for subvp main so if we have phantom
1884 * pipe, we can set odm policy to match main pipe
1885 */
1886 for (i = 0; i < context->stream_count; i++) {
1887 stream = context->streams[i];
1888 mall_type = dc_state_get_stream_subvp_type(context, stream);
1889 if (mall_type == SUBVP_MAIN)
1890 num_subvp_main++;
1891 else if (mall_type == SUBVP_PHANTOM)
1892 num_subvp_phantom++;
1893 else
1894 num_subvp_none++;
1895 }
1896 if (num_subvp_main == 1 && num_subvp_phantom == 1 && num_subvp_none == 0)
1897 single_display_subvp = true;
1898
1899 if (single_display_subvp) {
1900 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1901 pipe = &res_ctx->pipe_ctx[i];
1902 if (!res_ctx->pipe_ctx[i].stream)
1903 continue;
1904
1905 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1906 if (mall_type == SUBVP_MAIN) {
1907 if (resource_is_pipe_type(pipe, OTG_MASTER))
1908 subvp_main_pipe_index = i;
1909 }
1910 pipe_cnt++;
1911 }
1912 }
1913
1914 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1915
1916 if (!res_ctx->pipe_ctx[i].stream)
1917 continue;
1918 pipe = &res_ctx->pipe_ctx[i];
1919 timing = &pipe->stream->timing;
1920
1921 pipes[pipe_cnt].pipe.src.gpuvm = true;
1922 DC_FP_START();
1923 dcn32_zero_pipe_dcc_fraction(pipes, pipe_cnt);
1924 DC_FP_END();
1925 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1926 if (dc->config.enable_windowed_mpo_odm &&
1927 dc->debug.enable_single_display_2to1_odm_policy) {
1928 /* For single display subvp, if pipe is phantom pipe,
1929 * then copy odm policy from subvp main pipe
1930 */
1931 mall_type = dc_state_get_pipe_subvp_type(context, pipe);
1932 if (single_display_subvp && (mall_type == SUBVP_PHANTOM)) {
1933 if (subvp_main_pipe_index < 0) {
1934 odm_slice_count = -1;
1935 ASSERT(0);
1936 } else {
1937 odm_slice_count = resource_get_odm_slice_count(&res_ctx->pipe_ctx[subvp_main_pipe_index]);
1938 }
1939 } else {
1940 odm_slice_count = resource_get_odm_slice_count(pipe);
1941 }
1942 switch (odm_slice_count) {
1943 case 2:
1944 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
1945 break;
1946 case 4:
1947 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_4to1;
1948 break;
1949 default:
1950 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1951 }
1952 } else {
1953 pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_dal;
1954 }
1955
1956 pipes[pipe_cnt].pipe.src.gpuvm_min_page_size_kbytes = 256; // according to spreadsheet
1957 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1958 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_19;
1959
1960 /* Only populate DML input with subvp info for full updates.
1961 * This is just a workaround -- needs a proper fix.
1962 */
1963 if (!fast_validate) {
1964 switch (dc_state_get_pipe_subvp_type(context, pipe)) {
1965 case SUBVP_MAIN:
1966 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_sub_viewport;
1967 subvp_in_use = true;
1968 break;
1969 case SUBVP_PHANTOM:
1970 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_phantom_pipe;
1971 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1972 // Disallow unbounded req for SubVP according to DCHUB programming guide
1973 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1974 break;
1975 case SUBVP_NONE:
1976 pipes[pipe_cnt].pipe.src.use_mall_for_pstate_change = dm_use_mall_pstate_change_disable;
1977 pipes[pipe_cnt].pipe.src.use_mall_for_static_screen = dm_use_mall_static_screen_disable;
1978 break;
1979 default:
1980 break;
1981 }
1982 }
1983
1984 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1985 if (pipes[pipe_cnt].dout.dsc_enable) {
1986 switch (timing->display_color_depth) {
1987 case COLOR_DEPTH_888:
1988 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1989 break;
1990 case COLOR_DEPTH_101010:
1991 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1992 break;
1993 case COLOR_DEPTH_121212:
1994 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1995 break;
1996 default:
1997 ASSERT(0);
1998 break;
1999 }
2000 }
2001
2002
2003 pipe_cnt++;
2004 }
2005
2006 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
2007 * the DET available for each pipe). Use the DET override input to maintain our driver
2008 * policy.
2009 */
2010 dcn32_set_det_allocations(dc, context, pipes);
2011
2012 // In general cases we want to keep the dram clock change requirement
2013 // (prefer configs that support MCLK switch). Only override to false
2014 // for SubVP
2015 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)
2016 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;
2017 else
2018 context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;
2019
2020 return pipe_cnt;
2021 }
2022
dcn32_calculate_mall_ways_from_bytes(const struct dc * dc,unsigned int total_size_in_mall_bytes)2023 unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned int total_size_in_mall_bytes)
2024 {
2025 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
2026
2027 if (total_size_in_mall_bytes == 0) {
2028 return 0;
2029 }
2030
2031 if (dc->caps.max_cab_allocation_bytes == 0) {
2032 return 0xffffffff;
2033 }
2034
2035 /* add 2 lines for worst case alignment */
2036 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
2037
2038 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
2039 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
2040 num_ways = cache_lines_used / lines_per_way;
2041 if (cache_lines_used % lines_per_way > 0)
2042 num_ways++;
2043
2044 return num_ways;
2045 }
2046
2047 static struct dc_cap_funcs cap_funcs = {
2048 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap,
2049 .get_subvp_en = dcn32_subvp_in_use,
2050 };
2051
dcn32_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel)2052 void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,
2053 display_e2e_pipe_params_st *pipes,
2054 int pipe_cnt,
2055 int vlevel)
2056 {
2057 DC_FP_START();
2058 dcn32_calculate_wm_and_dlg_fpu(dc, context, pipes, pipe_cnt, vlevel);
2059 DC_FP_END();
2060 }
2061
dcn32_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)2062 static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2063 {
2064 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
2065
2066 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
2067
2068 DC_FP_START();
2069
2070 dcn32_update_bw_bounding_box_fpu(dc, bw_params);
2071
2072 dml2_opt->use_clock_dc_limits = false;
2073 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
2074 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
2075
2076 dml2_opt->use_clock_dc_limits = true;
2077 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
2078 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
2079
2080 DC_FP_END();
2081 }
2082
dcn32_get_max_hw_cursor_size(const struct dc * dc,struct dc_state * state,const struct dc_stream_state * stream)2083 unsigned int dcn32_get_max_hw_cursor_size(const struct dc *dc,
2084 struct dc_state *state,
2085 const struct dc_stream_state *stream)
2086 {
2087 bool limit_cur_to_buf;
2088
2089 limit_cur_to_buf = dc_state_get_stream_subvp_cursor_limit(stream, state) &&
2090 !stream->hw_cursor_req;
2091
2092 return limit_cur_to_buf ? dc->caps.max_buffered_cursor_size : dc->caps.max_cursor_size;
2093 }
2094
2095 static struct resource_funcs dcn32_res_pool_funcs = {
2096 .destroy = dcn32_destroy_resource_pool,
2097 .link_enc_create = dcn32_link_encoder_create,
2098 .link_enc_create_minimal = NULL,
2099 .panel_cntl_create = dcn32_panel_cntl_create,
2100 .validate_bandwidth = dcn32_validate_bandwidth,
2101 .calculate_wm_and_dlg = dcn32_calculate_wm_and_dlg,
2102 .populate_dml_pipes = dcn32_populate_dml_pipes_from_context,
2103 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
2104 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
2105 .release_pipe = dcn20_release_pipe,
2106 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2107 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2108 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2109 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2110 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2111 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2112 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
2113 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
2114 .update_bw_bounding_box = dcn32_update_bw_bounding_box,
2115 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2116 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2117 .add_phantom_pipes = dcn32_add_phantom_pipes,
2118 .build_pipe_pix_clk_params = dcn20_build_pipe_pix_clk_params,
2119 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
2120 .get_vstartup_for_pipe = dcn10_get_vstartup_for_pipe,
2121 .get_max_hw_cursor_size = dcn32_get_max_hw_cursor_size,
2122 };
2123
read_pipe_fuses(struct dc_context * ctx)2124 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2125 {
2126 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2127 /* DCN32 support max 4 pipes */
2128 value = value & 0xf;
2129 return value;
2130 }
2131
2132
dcn32_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn32_resource_pool * pool)2133 static bool dcn32_resource_construct(
2134 uint8_t num_virtual_links,
2135 struct dc *dc,
2136 struct dcn32_resource_pool *pool)
2137 {
2138 int i, j;
2139 struct dc_context *ctx = dc->ctx;
2140 struct irq_service_init_data init_data;
2141 struct ddc_service_init_data ddc_init_data = {0};
2142 uint32_t pipe_fuses = 0;
2143 uint32_t num_pipes = 4;
2144
2145 #undef REG_STRUCT
2146 #define REG_STRUCT bios_regs
2147 bios_regs_init();
2148
2149 #undef REG_STRUCT
2150 #define REG_STRUCT clk_src_regs
2151 clk_src_regs_init(0, A),
2152 clk_src_regs_init(1, B),
2153 clk_src_regs_init(2, C),
2154 clk_src_regs_init(3, D),
2155 clk_src_regs_init(4, E);
2156
2157 #undef REG_STRUCT
2158 #define REG_STRUCT abm_regs
2159 abm_regs_init(0),
2160 abm_regs_init(1),
2161 abm_regs_init(2),
2162 abm_regs_init(3);
2163
2164 #undef REG_STRUCT
2165 #define REG_STRUCT dccg_regs
2166 dccg_regs_init();
2167
2168 ctx->dc_bios->regs = &bios_regs;
2169
2170 pool->base.res_cap = &res_cap_dcn32;
2171 /* max number of pipes for ASIC before checking for pipe fuses */
2172 num_pipes = pool->base.res_cap->num_timing_generator;
2173 pipe_fuses = read_pipe_fuses(ctx);
2174
2175 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
2176 if (pipe_fuses & 1 << i)
2177 num_pipes--;
2178
2179 if (pipe_fuses & 1)
2180 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
2181
2182 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
2183 ASSERT(0); //Entire DCN is harvested!
2184
2185 /* within dml lib, initial value is hard coded, if ASIC pipe is fused, the
2186 * value will be changed, update max_num_dpp and max_num_otg for dml.
2187 */
2188 dcn3_2_ip.max_num_dpp = num_pipes;
2189 dcn3_2_ip.max_num_otg = num_pipes;
2190
2191 pool->base.funcs = &dcn32_res_pool_funcs;
2192
2193 /*************************************************
2194 * Resource + asic cap harcoding *
2195 *************************************************/
2196 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2197 pool->base.timing_generator_count = num_pipes;
2198 pool->base.pipe_count = num_pipes;
2199 pool->base.mpcc_count = num_pipes;
2200 dc->caps.max_downscale_ratio = 600;
2201 dc->caps.i2c_speed_in_khz = 100;
2202 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a applied by default*/
2203 /* TODO: Bring max_cursor_size back to 256 after subvp cursor corruption is fixed*/
2204 dc->caps.max_cursor_size = 64;
2205 dc->caps.max_buffered_cursor_size = 64; // sqrt(16 * 1024 / 4)
2206 dc->caps.min_horizontal_blanking_period = 80;
2207 dc->caps.dmdata_alloc_size = 2048;
2208 dc->caps.mall_size_per_mem_channel = 4;
2209 /* total size = mall per channel * num channels * 1024 * 1024 */
2210 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2211 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2212
2213 dc->caps.cache_line_size = 64;
2214 dc->caps.cache_num_ways = 16;
2215
2216 /* Calculate the available MALL space */
2217 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
2218 dc, dc->ctx->dc_bios->vram_info.num_chans) *
2219 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
2220 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
2221
2222 dc->caps.subvp_fw_processing_delay_us = 15;
2223 dc->caps.subvp_drr_max_vblank_margin_us = 40;
2224 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
2225 dc->caps.subvp_swath_height_margin_lines = 16;
2226 dc->caps.subvp_pstate_allow_width_us = 20;
2227 dc->caps.subvp_vertical_int_margin_us = 30;
2228 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
2229
2230 dc->caps.max_slave_planes = 2;
2231 dc->caps.max_slave_yuv_planes = 2;
2232 dc->caps.max_slave_rgb_planes = 2;
2233 dc->caps.post_blend_color_processing = true;
2234 dc->caps.force_dp_tps4_for_cp2520 = true;
2235 if (dc->config.forceHBR2CP2520)
2236 dc->caps.force_dp_tps4_for_cp2520 = false;
2237 dc->caps.dp_hpo = true;
2238 dc->caps.dp_hdmi21_pcon_support = true;
2239 dc->caps.edp_dsc_support = true;
2240 dc->caps.extended_aux_timeout_support = true;
2241 dc->caps.dmcub_support = true;
2242 dc->caps.seamless_odm = true;
2243 dc->caps.max_v_total = (1 << 15) - 1;
2244 dc->caps.vtotal_limited_by_fp2 = true;
2245
2246 /* Color pipeline capabilities */
2247 dc->caps.color.dpp.dcn_arch = 1;
2248 dc->caps.color.dpp.input_lut_shared = 0;
2249 dc->caps.color.dpp.icsc = 1;
2250 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2251 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2252 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2253 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2254 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2255 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2256 dc->caps.color.dpp.post_csc = 1;
2257 dc->caps.color.dpp.gamma_corr = 1;
2258 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2259
2260 dc->caps.color.dpp.hw_3d_lut = 1;
2261 dc->caps.color.dpp.ogam_ram = 0; // no OGAM in DPP since DCN1
2262 // no OGAM ROM on DCN2 and later ASICs
2263 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2264 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2265 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2266 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2267 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2268 dc->caps.color.dpp.ocsc = 0;
2269
2270 dc->caps.color.mpc.gamut_remap = 1;
2271 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
2272 dc->caps.color.mpc.ogam_ram = 1;
2273 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2274 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2275 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2276 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2277 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2278 dc->caps.color.mpc.ocsc = 1;
2279
2280 /* Use pipe context based otg sync logic */
2281 dc->config.use_pipe_ctx_sync_logic = true;
2282
2283 dc->config.dc_mode_clk_limit_support = true;
2284 dc->config.enable_windowed_mpo_odm = true;
2285 dc->config.disable_hbr_audio_dp2 = true;
2286 /* read VBIOS LTTPR caps */
2287 {
2288 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2289 enum bp_result bp_query_result;
2290 uint8_t is_vbios_lttpr_enable = 0;
2291
2292 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2293 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2294 }
2295
2296 /* interop bit is implicit */
2297 {
2298 dc->caps.vbios_lttpr_aware = true;
2299 }
2300 }
2301
2302 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2303 dc->debug = debug_defaults_drv;
2304
2305 // Init the vm_helper
2306 if (dc->vm_helper)
2307 vm_helper_init(dc->vm_helper, 16);
2308
2309 /*************************************************
2310 * Create resources *
2311 *************************************************/
2312
2313 /* Clock Sources for Pixel Clock*/
2314 pool->base.clock_sources[DCN32_CLK_SRC_PLL0] =
2315 dcn32_clock_source_create(ctx, ctx->dc_bios,
2316 CLOCK_SOURCE_COMBO_PHY_PLL0,
2317 &clk_src_regs[0], false);
2318 pool->base.clock_sources[DCN32_CLK_SRC_PLL1] =
2319 dcn32_clock_source_create(ctx, ctx->dc_bios,
2320 CLOCK_SOURCE_COMBO_PHY_PLL1,
2321 &clk_src_regs[1], false);
2322 pool->base.clock_sources[DCN32_CLK_SRC_PLL2] =
2323 dcn32_clock_source_create(ctx, ctx->dc_bios,
2324 CLOCK_SOURCE_COMBO_PHY_PLL2,
2325 &clk_src_regs[2], false);
2326 pool->base.clock_sources[DCN32_CLK_SRC_PLL3] =
2327 dcn32_clock_source_create(ctx, ctx->dc_bios,
2328 CLOCK_SOURCE_COMBO_PHY_PLL3,
2329 &clk_src_regs[3], false);
2330 pool->base.clock_sources[DCN32_CLK_SRC_PLL4] =
2331 dcn32_clock_source_create(ctx, ctx->dc_bios,
2332 CLOCK_SOURCE_COMBO_PHY_PLL4,
2333 &clk_src_regs[4], false);
2334
2335 pool->base.clk_src_count = DCN32_CLK_SRC_TOTAL;
2336
2337 /* todo: not reuse phy_pll registers */
2338 pool->base.dp_clock_source =
2339 dcn32_clock_source_create(ctx, ctx->dc_bios,
2340 CLOCK_SOURCE_ID_DP_DTO,
2341 &clk_src_regs[0], true);
2342
2343 for (i = 0; i < pool->base.clk_src_count; i++) {
2344 if (pool->base.clock_sources[i] == NULL) {
2345 dm_error("DC: failed to create clock sources!\n");
2346 BREAK_TO_DEBUGGER();
2347 goto create_fail;
2348 }
2349 }
2350
2351 /* DCCG */
2352 pool->base.dccg = dccg32_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2353 if (pool->base.dccg == NULL) {
2354 dm_error("DC: failed to create dccg!\n");
2355 BREAK_TO_DEBUGGER();
2356 goto create_fail;
2357 }
2358
2359 /* DML */
2360 dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);
2361
2362 /* IRQ Service */
2363 init_data.ctx = dc->ctx;
2364 pool->base.irqs = dal_irq_service_dcn32_create(&init_data);
2365 if (!pool->base.irqs)
2366 goto create_fail;
2367
2368 /* HUBBUB */
2369 pool->base.hubbub = dcn32_hubbub_create(ctx);
2370 if (pool->base.hubbub == NULL) {
2371 BREAK_TO_DEBUGGER();
2372 dm_error("DC: failed to create hubbub!\n");
2373 goto create_fail;
2374 }
2375
2376 /* HUBPs, DPPs, OPPs, TGs, ABMs */
2377 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2378
2379 /* if pipe is disabled, skip instance of HW pipe,
2380 * i.e, skip ASIC register instance
2381 */
2382 if (pipe_fuses & 1 << i)
2383 continue;
2384
2385 /* HUBPs */
2386 pool->base.hubps[j] = dcn32_hubp_create(ctx, i);
2387 if (pool->base.hubps[j] == NULL) {
2388 BREAK_TO_DEBUGGER();
2389 dm_error(
2390 "DC: failed to create hubps!\n");
2391 goto create_fail;
2392 }
2393
2394 /* DPPs */
2395 pool->base.dpps[j] = dcn32_dpp_create(ctx, i);
2396 if (pool->base.dpps[j] == NULL) {
2397 BREAK_TO_DEBUGGER();
2398 dm_error(
2399 "DC: failed to create dpps!\n");
2400 goto create_fail;
2401 }
2402
2403 /* OPPs */
2404 pool->base.opps[j] = dcn32_opp_create(ctx, i);
2405 if (pool->base.opps[j] == NULL) {
2406 BREAK_TO_DEBUGGER();
2407 dm_error(
2408 "DC: failed to create output pixel processor!\n");
2409 goto create_fail;
2410 }
2411
2412 /* TGs */
2413 pool->base.timing_generators[j] = dcn32_timing_generator_create(
2414 ctx, i);
2415 if (pool->base.timing_generators[j] == NULL) {
2416 BREAK_TO_DEBUGGER();
2417 dm_error("DC: failed to create tg!\n");
2418 goto create_fail;
2419 }
2420
2421 /* ABMs */
2422 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
2423 &abm_regs[i],
2424 &abm_shift,
2425 &abm_mask);
2426 if (pool->base.multiple_abms[j] == NULL) {
2427 dm_error("DC: failed to create abm for pipe %d!\n", i);
2428 BREAK_TO_DEBUGGER();
2429 goto create_fail;
2430 }
2431
2432 /* index for resource pool arrays for next valid pipe */
2433 j++;
2434 }
2435
2436 /* PSR */
2437 pool->base.psr = dmub_psr_create(ctx);
2438 if (pool->base.psr == NULL) {
2439 dm_error("DC: failed to create psr obj!\n");
2440 BREAK_TO_DEBUGGER();
2441 goto create_fail;
2442 }
2443
2444 /* MPCCs */
2445 pool->base.mpc = dcn32_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2446 if (pool->base.mpc == NULL) {
2447 BREAK_TO_DEBUGGER();
2448 dm_error("DC: failed to create mpc!\n");
2449 goto create_fail;
2450 }
2451
2452 /* DSCs */
2453 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2454 pool->base.dscs[i] = dcn32_dsc_create(ctx, i);
2455 if (pool->base.dscs[i] == NULL) {
2456 BREAK_TO_DEBUGGER();
2457 dm_error("DC: failed to create display stream compressor %d!\n", i);
2458 goto create_fail;
2459 }
2460 }
2461
2462 /* DWB */
2463 if (!dcn32_dwbc_create(ctx, &pool->base)) {
2464 BREAK_TO_DEBUGGER();
2465 dm_error("DC: failed to create dwbc!\n");
2466 goto create_fail;
2467 }
2468
2469 /* MMHUBBUB */
2470 if (!dcn32_mmhubbub_create(ctx, &pool->base)) {
2471 BREAK_TO_DEBUGGER();
2472 dm_error("DC: failed to create mcif_wb!\n");
2473 goto create_fail;
2474 }
2475
2476 /* AUX and I2C */
2477 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2478 pool->base.engines[i] = dcn32_aux_engine_create(ctx, i);
2479 if (pool->base.engines[i] == NULL) {
2480 BREAK_TO_DEBUGGER();
2481 dm_error(
2482 "DC:failed to create aux engine!!\n");
2483 goto create_fail;
2484 }
2485 pool->base.hw_i2cs[i] = dcn32_i2c_hw_create(ctx, i);
2486 if (pool->base.hw_i2cs[i] == NULL) {
2487 BREAK_TO_DEBUGGER();
2488 dm_error(
2489 "DC:failed to create hw i2c!!\n");
2490 goto create_fail;
2491 }
2492 pool->base.sw_i2cs[i] = NULL;
2493 }
2494
2495 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2496 if (!resource_construct(num_virtual_links, dc, &pool->base,
2497 &res_create_funcs))
2498 goto create_fail;
2499
2500 /* HW Sequencer init functions and Plane caps */
2501 dcn32_hw_sequencer_init_functions(dc);
2502
2503 dc->caps.max_planes = pool->base.pipe_count;
2504
2505 for (i = 0; i < dc->caps.max_planes; ++i)
2506 dc->caps.planes[i] = plane_cap;
2507
2508 dc->cap_funcs = cap_funcs;
2509
2510 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2511 ddc_init_data.ctx = dc->ctx;
2512 ddc_init_data.link = NULL;
2513 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2514 ddc_init_data.id.enum_id = 0;
2515 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2516 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2517 } else {
2518 pool->base.oem_device = NULL;
2519 }
2520
2521 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2522 dc->dml2_options.use_native_pstate_optimization = false;
2523 dc->dml2_options.use_native_soc_bb_construction = true;
2524 dc->dml2_options.minimize_dispclk_using_odm = true;
2525
2526 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2527 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2528 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2529 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2530
2531 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2532 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2533 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2534 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2535
2536 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2537 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2538
2539 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2540 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2541 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2542 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2543 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2544 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2545 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2546
2547 dc->dml2_options.max_segments_per_hubp = 18;
2548 dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;
2549 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2550
2551 if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev) && (dc->config.sdpif_request_limit_words_per_umc == 0))
2552 dc->config.sdpif_request_limit_words_per_umc = 16;
2553
2554 return true;
2555
2556 create_fail:
2557
2558 dcn32_resource_destruct(pool);
2559
2560 return false;
2561 }
2562
dcn32_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2563 struct resource_pool *dcn32_create_resource_pool(
2564 const struct dc_init_data *init_data,
2565 struct dc *dc)
2566 {
2567 struct dcn32_resource_pool *pool =
2568 kzalloc(sizeof(struct dcn32_resource_pool), GFP_KERNEL);
2569
2570 if (!pool)
2571 return NULL;
2572
2573 if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
2574 return &pool->base;
2575
2576 BREAK_TO_DEBUGGER();
2577 kfree(pool);
2578 return NULL;
2579 }
2580
2581 /*
2582 * Find the most optimal free pipe from res_ctx, which could be used as a
2583 * secondary dpp pipe for input opp head pipe.
2584 *
2585 * a free pipe - a pipe in input res_ctx not yet used for any streams or
2586 * planes.
2587 * secondary dpp pipe - a pipe gets inserted to a head OPP pipe's MPC blending
2588 * tree. This is typical used for rendering MPO planes or additional offset
2589 * areas in MPCC combine.
2590 *
2591 * Hardware Transition Minimization Algorithm for Finding a Secondary DPP Pipe
2592 * -------------------------------------------------------------------------
2593 *
2594 * PROBLEM:
2595 *
2596 * 1. There is a hardware limitation that a secondary DPP pipe cannot be
2597 * transferred from one MPC blending tree to the other in a single frame.
2598 * Otherwise it could cause glitches on the screen.
2599 *
2600 * For instance, we cannot transition from state 1 to state 2 in one frame. This
2601 * is because PIPE1 is transferred from PIPE0's MPC blending tree over to
2602 * PIPE2's MPC blending tree, which is not supported by hardware.
2603 * To support this transition we need to first remove PIPE1 from PIPE0's MPC
2604 * blending tree in one frame and then insert PIPE1 to PIPE2's MPC blending tree
2605 * in the next frame. This is not optimal as it will delay the flip for two
2606 * frames.
2607 *
2608 * State 1:
2609 * PIPE0 -- secondary DPP pipe --> (PIPE1)
2610 * PIPE2 -- secondary DPP pipe --> NONE
2611 *
2612 * State 2:
2613 * PIPE0 -- secondary DPP pipe --> NONE
2614 * PIPE2 -- secondary DPP pipe --> (PIPE1)
2615 *
2616 * 2. We want to in general minimize the unnecessary changes in pipe topology.
2617 * If a pipe is already added in current blending tree and there are no changes
2618 * to plane topology, we don't want to swap it with another free pipe
2619 * unnecessarily in every update. Powering up and down a pipe would require a
2620 * full update which delays the flip for 1 frame. If we use the original pipe
2621 * we don't have to toggle its power. So we can flip faster.
2622 */
dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_opp_head)2623 int dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2624 const struct resource_context *cur_res_ctx,
2625 struct resource_context *new_res_ctx,
2626 const struct resource_pool *pool,
2627 const struct pipe_ctx *new_opp_head)
2628 {
2629 const struct pipe_ctx *cur_opp_head;
2630 int free_pipe_idx;
2631
2632 cur_opp_head = &cur_res_ctx->pipe_ctx[new_opp_head->pipe_idx];
2633 free_pipe_idx = resource_find_free_pipe_used_in_cur_mpc_blending_tree(
2634 cur_res_ctx, new_res_ctx, cur_opp_head);
2635
2636 /* Up until here if we have not found a free secondary pipe, we will
2637 * need to wait for at least one frame to complete the transition
2638 * sequence.
2639 */
2640 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2641 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2642 cur_res_ctx, new_res_ctx, pool);
2643
2644 /* Up until here if we have not found a free secondary pipe, we will
2645 * need to wait for at least two frames to complete the transition
2646 * sequence. It really doesn't matter which pipe we decide take from
2647 * current enabled pipes. It won't save our frame time when we swap only
2648 * one pipe or more pipes.
2649 */
2650 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2651 free_pipe_idx = resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
2652 cur_res_ctx, new_res_ctx, pool);
2653
2654 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2655 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2656
2657 return free_pipe_idx;
2658 }
2659
find_idle_secondary_pipe_check_mpo(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)2660 static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
2661 struct resource_context *res_ctx,
2662 const struct resource_pool *pool,
2663 const struct pipe_ctx *primary_pipe)
2664 {
2665 int i;
2666 struct pipe_ctx *secondary_pipe = NULL;
2667 struct pipe_ctx *next_odm_mpo_pipe = NULL;
2668 int primary_index, preferred_pipe_idx;
2669 struct pipe_ctx *old_primary_pipe = NULL;
2670
2671 /*
2672 * Modified from find_idle_secondary_pipe
2673 * With windowed MPO and ODM, we want to avoid the case where we want a
2674 * free pipe for the left side but the free pipe is being used on the
2675 * right side.
2676 * Add check on current_state if the primary_pipe is the left side,
2677 * to check the right side ( primary_pipe->next_odm_pipe ) to see if
2678 * it is using a pipe for MPO ( primary_pipe->next_odm_pipe->bottom_pipe )
2679 * - If so, then don't use this pipe
2680 * EXCEPTION - 3 plane ( 2 MPO plane ) case
2681 * - in this case, the primary pipe has already gotten a free pipe for the
2682 * MPO window in the left
2683 * - when it tries to get a free pipe for the MPO window on the right,
2684 * it will see that it is already assigned to the right side
2685 * ( primary_pipe->next_odm_pipe ). But in this case, we want this
2686 * free pipe, since it will be for the right side. So add an
2687 * additional condition, that skipping the free pipe on the right only
2688 * applies if the primary pipe has no bottom pipe currently assigned
2689 */
2690 if (primary_pipe) {
2691 primary_index = primary_pipe->pipe_idx;
2692 old_primary_pipe = &primary_pipe->stream->ctx->dc->current_state->res_ctx.pipe_ctx[primary_index];
2693 if ((old_primary_pipe->next_odm_pipe) && (old_primary_pipe->next_odm_pipe->bottom_pipe)
2694 && (!primary_pipe->bottom_pipe))
2695 next_odm_mpo_pipe = old_primary_pipe->next_odm_pipe->bottom_pipe;
2696
2697 preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
2698 if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
2699 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
2700 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2701 secondary_pipe->pipe_idx = preferred_pipe_idx;
2702 }
2703 }
2704
2705 /*
2706 * search backwards for the second pipe to keep pipe
2707 * assignment more consistent
2708 */
2709 if (!secondary_pipe)
2710 for (i = pool->pipe_count - 1; i >= 0; i--) {
2711 if ((res_ctx->pipe_ctx[i].stream == NULL) &&
2712 !(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
2713 secondary_pipe = &res_ctx->pipe_ctx[i];
2714 secondary_pipe->pipe_idx = i;
2715 break;
2716 }
2717 }
2718
2719 return secondary_pipe;
2720 }
2721
dcn32_acquire_idle_pipe_for_head_pipe_in_layer(struct dc_state * state,const struct resource_pool * pool,struct dc_stream_state * stream,const struct pipe_ctx * head_pipe)2722 static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2723 struct dc_state *state,
2724 const struct resource_pool *pool,
2725 struct dc_stream_state *stream,
2726 const struct pipe_ctx *head_pipe)
2727 {
2728 struct resource_context *res_ctx = &state->res_ctx;
2729 struct pipe_ctx *idle_pipe, *pipe;
2730 struct resource_context *old_ctx = &stream->ctx->dc->current_state->res_ctx;
2731 int head_index;
2732
2733 if (!head_pipe) {
2734 ASSERT(0);
2735 return NULL;
2736 }
2737
2738 /*
2739 * Modified from dcn20_acquire_idle_pipe_for_layer
2740 * Check if head_pipe in old_context already has bottom_pipe allocated.
2741 * - If so, check if that pipe is available in the current context.
2742 * -- If so, reuse pipe from old_context
2743 */
2744 head_index = head_pipe->pipe_idx;
2745 pipe = &old_ctx->pipe_ctx[head_index];
2746 if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
2747 idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
2748 idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
2749 } else {
2750 idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
2751 if (!idle_pipe)
2752 return NULL;
2753 }
2754
2755 idle_pipe->stream = head_pipe->stream;
2756 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
2757 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
2758
2759 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
2760 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
2761 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
2762 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
2763
2764 return idle_pipe;
2765 }
2766
find_optimal_free_pipe_as_secondary_opp_head(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool,const struct pipe_ctx * new_otg_master)2767 static int find_optimal_free_pipe_as_secondary_opp_head(
2768 const struct resource_context *cur_res_ctx,
2769 struct resource_context *new_res_ctx,
2770 const struct resource_pool *pool,
2771 const struct pipe_ctx *new_otg_master)
2772 {
2773 const struct pipe_ctx *cur_otg_master;
2774 int free_pipe_idx;
2775
2776 cur_otg_master = &cur_res_ctx->pipe_ctx[new_otg_master->pipe_idx];
2777 free_pipe_idx = resource_find_free_pipe_used_as_sec_opp_head_by_cur_otg_master(
2778 cur_res_ctx, new_res_ctx, cur_otg_master);
2779
2780 /* Up until here if we have not found a free secondary pipe, we will
2781 * need to wait for at least one frame to complete the transition
2782 * sequence.
2783 */
2784 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2785 free_pipe_idx = recource_find_free_pipe_not_used_in_cur_res_ctx(
2786 cur_res_ctx, new_res_ctx, pool);
2787
2788 if (free_pipe_idx == FREE_PIPE_INDEX_NOT_FOUND)
2789 free_pipe_idx = resource_find_any_free_pipe(new_res_ctx, pool);
2790
2791 return free_pipe_idx;
2792 }
2793
dcn32_acquire_free_pipe_as_secondary_dpp_pipe(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head_pipe)2794 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
2795 const struct dc_state *cur_ctx,
2796 struct dc_state *new_ctx,
2797 const struct resource_pool *pool,
2798 const struct pipe_ctx *opp_head_pipe)
2799 {
2800
2801 int free_pipe_idx;
2802 struct pipe_ctx *free_pipe;
2803
2804 if (!opp_head_pipe->stream->ctx->dc->config.enable_windowed_mpo_odm)
2805 return dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
2806 new_ctx, pool, opp_head_pipe->stream, opp_head_pipe);
2807
2808 free_pipe_idx = dcn32_find_optimal_free_pipe_as_secondary_dpp_pipe(
2809 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2810 pool, opp_head_pipe);
2811 if (free_pipe_idx >= 0) {
2812 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2813 free_pipe->pipe_idx = free_pipe_idx;
2814 free_pipe->stream = opp_head_pipe->stream;
2815 free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
2816 free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
2817
2818 free_pipe->plane_res.hubp = pool->hubps[free_pipe->pipe_idx];
2819 free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
2820 free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
2821 free_pipe->plane_res.mpcc_inst =
2822 pool->dpps[free_pipe->pipe_idx]->inst;
2823 } else {
2824 ASSERT(opp_head_pipe);
2825 free_pipe = NULL;
2826 }
2827
2828 return free_pipe;
2829 }
2830
dcn32_acquire_free_pipe_as_secondary_opp_head(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * otg_master)2831 struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
2832 const struct dc_state *cur_ctx,
2833 struct dc_state *new_ctx,
2834 const struct resource_pool *pool,
2835 const struct pipe_ctx *otg_master)
2836 {
2837 int free_pipe_idx = find_optimal_free_pipe_as_secondary_opp_head(
2838 &cur_ctx->res_ctx, &new_ctx->res_ctx,
2839 pool, otg_master);
2840 struct pipe_ctx *free_pipe;
2841
2842 if (free_pipe_idx >= 0) {
2843 free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
2844 free_pipe->pipe_idx = free_pipe_idx;
2845 free_pipe->stream = otg_master->stream;
2846 free_pipe->stream_res.tg = otg_master->stream_res.tg;
2847 free_pipe->stream_res.dsc = NULL;
2848 free_pipe->stream_res.opp = pool->opps[free_pipe_idx];
2849 free_pipe->plane_res.mi = pool->mis[free_pipe_idx];
2850 free_pipe->plane_res.hubp = pool->hubps[free_pipe_idx];
2851 free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
2852 free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
2853 free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
2854 free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
2855 free_pipe->hblank_borrow = otg_master->hblank_borrow;
2856 if (free_pipe->stream->timing.flags.DSC == 1) {
2857 dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
2858 &new_ctx->res_ctx,
2859 &free_pipe->stream_res.dsc,
2860 free_pipe_idx);
2861 ASSERT(free_pipe->stream_res.dsc);
2862 if (free_pipe->stream_res.dsc == NULL) {
2863 memset(free_pipe, 0, sizeof(*free_pipe));
2864 free_pipe = NULL;
2865 }
2866 }
2867 } else {
2868 ASSERT(otg_master);
2869 free_pipe = NULL;
2870 }
2871
2872 return free_pipe;
2873 }
2874
dcn32_calc_num_avail_chans_for_mall(struct dc * dc,int num_chans)2875 unsigned int dcn32_calc_num_avail_chans_for_mall(struct dc *dc, int num_chans)
2876 {
2877 /*
2878 * DCN32 and DCN321 SKUs may have different sizes for MALL
2879 * but we may not be able to access all the MALL space.
2880 * If the num_chans is power of 2, then we can access all
2881 * of the available MALL space. Otherwise, we can only
2882 * access:
2883 *
2884 * max_cab_size_in_bytes = total_cache_size_in_bytes *
2885 * ((2^floor(log2(num_chans)))/num_chans)
2886 *
2887 * Calculating the MALL sizes for all available SKUs, we
2888 * have come up with the follow simplified check.
2889 * - we have max_chans which provides the max MALL size.
2890 * Each chans supports 4MB of MALL so:
2891 *
2892 * total_cache_size_in_bytes = max_chans * 4 MB
2893 *
2894 * - we have avail_chans which shows the number of channels
2895 * we can use if we can't access the entire MALL space.
2896 * It is generally half of max_chans
2897 * - so we use the following checks:
2898 *
2899 * if (num_chans == max_chans), return max_chans
2900 * if (num_chans < max_chans), return avail_chans
2901 *
2902 * - exception is GC_11_0_0 where we can't access max_chans,
2903 * so we define max_avail_chans as the maximum available
2904 * MALL space
2905 *
2906 */
2907 int gc_11_0_0_max_chans = 48;
2908 int gc_11_0_0_max_avail_chans = 32;
2909 int gc_11_0_0_avail_chans = 16;
2910 int gc_11_0_3_max_chans = 16;
2911 int gc_11_0_3_avail_chans = 8;
2912 int gc_11_0_2_max_chans = 8;
2913 int gc_11_0_2_avail_chans = 4;
2914
2915 if (ASICREV_IS_GC_11_0_0(dc->ctx->asic_id.hw_internal_rev)) {
2916 return (num_chans == gc_11_0_0_max_chans) ?
2917 gc_11_0_0_max_avail_chans : gc_11_0_0_avail_chans;
2918 } else if (ASICREV_IS_GC_11_0_2(dc->ctx->asic_id.hw_internal_rev)) {
2919 return (num_chans == gc_11_0_2_max_chans) ?
2920 gc_11_0_2_max_chans : gc_11_0_2_avail_chans;
2921 } else { // if (ASICREV_IS_GC_11_0_3(dc->ctx->asic_id.hw_internal_rev)) {
2922 return (num_chans == gc_11_0_3_max_chans) ?
2923 gc_11_0_3_max_chans : gc_11_0_3_avail_chans;
2924 }
2925 }
2926