xref: /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.h (revision b7e1e969c887c897947fdc3754fe9b0c24acb155)
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DC_HWSS_DCN31_H__
27 #define __DC_HWSS_DCN31_H__
28 
29 #include "hw_sequencer_private.h"
30 
31 struct dc;
32 
33 void dcn31_init_hw(struct dc *dc);
34 
35 void dcn31_dsc_pg_control(
36 		struct dce_hwseq *hws,
37 		unsigned int dsc_inst,
38 		bool power_on);
39 
40 void dcn31_enable_power_gating_plane(
41 	struct dce_hwseq *hws,
42 	bool enable);
43 
44 void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx);
45 
46 void dcn31_z10_restore(const struct dc *dc);
47 void dcn31_z10_save_init(struct dc *dc);
48 
49 void dcn31_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on);
50 int dcn31_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config);
51 void dcn31_reset_hw_ctx_wrap(
52 		struct dc *dc,
53 		struct dc_state *context);
54 bool dcn31_is_abm_supported(struct dc *dc,
55 		struct dc_state *context, struct dc_stream_state *stream);
56 void dcn31_init_pipes(struct dc *dc, struct dc_state *context);
57 void dcn31_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable);
58 
59 void dcn31_set_static_screen_control(struct pipe_ctx **pipe_ctx,
60 		int num_pipes, const struct dc_static_screen_params *params);
61 
62 
63 #endif /* __DC_HWSS_DCN31_H__ */
64