1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> 5 */ 6 7#include <dt-bindings/clock/sophgo,cv1800.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus: cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 timebase-frequency = <25000000>; 19 20 cpu0: cpu@0 { 21 compatible = "thead,c906", "riscv"; 22 device_type = "cpu"; 23 reg = <0>; 24 d-cache-block-size = <64>; 25 d-cache-sets = <512>; 26 d-cache-size = <65536>; 27 i-cache-block-size = <64>; 28 i-cache-sets = <128>; 29 i-cache-size = <32768>; 30 mmu-type = "riscv,sv39"; 31 riscv,isa = "rv64imafdc"; 32 riscv,isa-base = "rv64i"; 33 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", 34 "zifencei", "zihpm"; 35 36 cpu0_intc: interrupt-controller { 37 compatible = "riscv,cpu-intc"; 38 interrupt-controller; 39 #interrupt-cells = <1>; 40 }; 41 }; 42 }; 43 44 osc: oscillator { 45 compatible = "fixed-clock"; 46 clock-output-names = "osc_25m"; 47 #clock-cells = <0>; 48 }; 49 50 soc { 51 compatible = "simple-bus"; 52 interrupt-parent = <&plic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 dma-noncoherent; 56 ranges; 57 58 clk: clock-controller@3002000 { 59 reg = <0x03002000 0x1000>; 60 clocks = <&osc>; 61 #clock-cells = <1>; 62 }; 63 64 gpio0: gpio@3020000 { 65 compatible = "snps,dw-apb-gpio"; 66 reg = <0x3020000 0x1000>; 67 #address-cells = <1>; 68 #size-cells = <0>; 69 70 porta: gpio-controller@0 { 71 compatible = "snps,dw-apb-gpio-port"; 72 gpio-controller; 73 #gpio-cells = <2>; 74 ngpios = <32>; 75 reg = <0>; 76 interrupt-controller; 77 #interrupt-cells = <2>; 78 interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; 79 }; 80 }; 81 82 gpio1: gpio@3021000 { 83 compatible = "snps,dw-apb-gpio"; 84 reg = <0x3021000 0x1000>; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 88 portb: gpio-controller@0 { 89 compatible = "snps,dw-apb-gpio-port"; 90 gpio-controller; 91 #gpio-cells = <2>; 92 ngpios = <32>; 93 reg = <0>; 94 interrupt-controller; 95 #interrupt-cells = <2>; 96 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; 97 }; 98 }; 99 100 gpio2: gpio@3022000 { 101 compatible = "snps,dw-apb-gpio"; 102 reg = <0x3022000 0x1000>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 106 portc: gpio-controller@0 { 107 compatible = "snps,dw-apb-gpio-port"; 108 gpio-controller; 109 #gpio-cells = <2>; 110 ngpios = <32>; 111 reg = <0>; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; 115 }; 116 }; 117 118 gpio3: gpio@3023000 { 119 compatible = "snps,dw-apb-gpio"; 120 reg = <0x3023000 0x1000>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 portd: gpio-controller@0 { 125 compatible = "snps,dw-apb-gpio-port"; 126 gpio-controller; 127 #gpio-cells = <2>; 128 ngpios = <32>; 129 reg = <0>; 130 interrupt-controller; 131 #interrupt-cells = <2>; 132 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; 133 }; 134 }; 135 136 saradc: adc@30f0000 { 137 compatible = "sophgo,cv1800b-saradc"; 138 reg = <0x030f0000 0x1000>; 139 clocks = <&clk CLK_SARADC>; 140 interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; 141 #address-cells = <1>; 142 #size-cells = <0>; 143 status = "disabled"; 144 145 channel@0 { 146 reg = <0>; 147 }; 148 149 channel@1 { 150 reg = <1>; 151 }; 152 153 channel@2 { 154 reg = <2>; 155 }; 156 }; 157 158 i2c0: i2c@4000000 { 159 compatible = "snps,designware-i2c"; 160 reg = <0x04000000 0x10000>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; 164 clock-names = "ref", "pclk"; 165 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; 166 status = "disabled"; 167 }; 168 169 i2c1: i2c@4010000 { 170 compatible = "snps,designware-i2c"; 171 reg = <0x04010000 0x10000>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; 175 clock-names = "ref", "pclk"; 176 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; 177 status = "disabled"; 178 }; 179 180 i2c2: i2c@4020000 { 181 compatible = "snps,designware-i2c"; 182 reg = <0x04020000 0x10000>; 183 #address-cells = <1>; 184 #size-cells = <0>; 185 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; 186 clock-names = "ref", "pclk"; 187 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 188 status = "disabled"; 189 }; 190 191 i2c3: i2c@4030000 { 192 compatible = "snps,designware-i2c"; 193 reg = <0x04030000 0x10000>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; 197 clock-names = "ref", "pclk"; 198 interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; 199 status = "disabled"; 200 }; 201 202 i2c4: i2c@4040000 { 203 compatible = "snps,designware-i2c"; 204 reg = <0x04040000 0x10000>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; 208 clock-names = "ref", "pclk"; 209 interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; 210 status = "disabled"; 211 }; 212 213 uart0: serial@4140000 { 214 compatible = "snps,dw-apb-uart"; 215 reg = <0x04140000 0x100>; 216 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; 218 clock-names = "baudclk", "apb_pclk"; 219 reg-shift = <2>; 220 reg-io-width = <4>; 221 status = "disabled"; 222 }; 223 224 uart1: serial@4150000 { 225 compatible = "snps,dw-apb-uart"; 226 reg = <0x04150000 0x100>; 227 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 228 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; 229 clock-names = "baudclk", "apb_pclk"; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 status = "disabled"; 233 }; 234 235 uart2: serial@4160000 { 236 compatible = "snps,dw-apb-uart"; 237 reg = <0x04160000 0x100>; 238 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; 240 clock-names = "baudclk", "apb_pclk"; 241 reg-shift = <2>; 242 reg-io-width = <4>; 243 status = "disabled"; 244 }; 245 246 uart3: serial@4170000 { 247 compatible = "snps,dw-apb-uart"; 248 reg = <0x04170000 0x100>; 249 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; 251 clock-names = "baudclk", "apb_pclk"; 252 reg-shift = <2>; 253 reg-io-width = <4>; 254 status = "disabled"; 255 }; 256 257 spi0: spi@4180000 { 258 compatible = "snps,dw-apb-ssi"; 259 reg = <0x04180000 0x10000>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; 263 clock-names = "ssi_clk", "pclk"; 264 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 }; 267 268 spi1: spi@4190000 { 269 compatible = "snps,dw-apb-ssi"; 270 reg = <0x04190000 0x10000>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; 274 clock-names = "ssi_clk", "pclk"; 275 interrupts = <55 IRQ_TYPE_LEVEL_HIGH>; 276 status = "disabled"; 277 }; 278 279 spi2: spi@41a0000 { 280 compatible = "snps,dw-apb-ssi"; 281 reg = <0x041a0000 0x10000>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; 285 clock-names = "ssi_clk", "pclk"; 286 interrupts = <56 IRQ_TYPE_LEVEL_HIGH>; 287 status = "disabled"; 288 }; 289 290 spi3: spi@41b0000 { 291 compatible = "snps,dw-apb-ssi"; 292 reg = <0x041b0000 0x10000>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; 296 clock-names = "ssi_clk", "pclk"; 297 interrupts = <57 IRQ_TYPE_LEVEL_HIGH>; 298 status = "disabled"; 299 }; 300 301 uart4: serial@41c0000 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x041c0000 0x100>; 304 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 305 clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; 306 clock-names = "baudclk", "apb_pclk"; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 status = "disabled"; 310 }; 311 312 sdhci0: mmc@4310000 { 313 compatible = "sophgo,cv1800b-dwcmshc"; 314 reg = <0x4310000 0x1000>; 315 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&clk CLK_AXI4_SD0>, 317 <&clk CLK_SD0>; 318 clock-names = "core", "bus"; 319 status = "disabled"; 320 }; 321 322 sdhci1: mmc@4320000 { 323 compatible = "sophgo,cv1800b-dwcmshc"; 324 reg = <0x4320000 0x1000>; 325 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&clk CLK_AXI4_SD1>, 327 <&clk CLK_SD1>; 328 clock-names = "core", "bus"; 329 status = "disabled"; 330 }; 331 332 dmac: dma-controller@4330000 { 333 compatible = "snps,axi-dma-1.01a"; 334 reg = <0x04330000 0x1000>; 335 interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; 337 clock-names = "core-clk", "cfgr-clk"; 338 #dma-cells = <1>; 339 dma-channels = <8>; 340 snps,block-size = <1024 1024 1024 1024 341 1024 1024 1024 1024>; 342 snps,priority = <0 1 2 3 4 5 6 7>; 343 snps,dma-masters = <2>; 344 snps,data-width = <4>; 345 status = "disabled"; 346 }; 347 348 plic: interrupt-controller@70000000 { 349 reg = <0x70000000 0x4000000>; 350 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; 351 interrupt-controller; 352 #address-cells = <0>; 353 #interrupt-cells = <2>; 354 riscv,ndev = <101>; 355 }; 356 357 clint: timer@74000000 { 358 reg = <0x74000000 0x10000>; 359 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; 360 }; 361 }; 362}; 363