1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright (c) 2022, Arm Limited. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited. All rights reserved. 5 * 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 aliases { 16 serial0 = &uart0; 17 serial1 = &uart1; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu: cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a35"; 31 reg = <0>; 32 next-level-cache = <&L2_0>; 33 }; 34 }; 35 36 memory@88200000 { 37 device_type = "memory"; 38 reg = <0x88200000 0x77e00000>; 39 }; 40 41 gic: interrupt-controller@1c000000 { 42 compatible = "arm,gic-400"; 43 #interrupt-cells = <3>; 44 #address-cells = <0>; 45 interrupt-controller; 46 reg = <0x1c010000 0x1000>, 47 <0x1c02f000 0x2000>, 48 <0x1c04f000 0x1000>, 49 <0x1c06f000 0x2000>; 50 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 51 IRQ_TYPE_LEVEL_LOW)>; 52 }; 53 54 L2_0: l2-cache0 { 55 compatible = "cache"; 56 cache-unified; 57 cache-level = <2>; 58 cache-size = <0x80000>; 59 cache-line-size = <64>; 60 cache-sets = <1024>; 61 }; 62 63 refclk100mhz: refclk100mhz { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <100000000>; 67 clock-output-names = "apb_pclk"; 68 }; 69 70 smbclk: refclk24mhzx2 { 71 /* Reference 24MHz clock x 2 */ 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <48000000>; 75 clock-output-names = "smclk"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 82 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 84 }; 85 86 uartclk: uartclk { 87 /* UART clock - 50MHz */ 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <50000000>; 91 clock-output-names = "uartclk"; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0", "arm,psci-0.2"; 96 method = "smc"; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 interrupt-parent = <&gic>; 104 ranges; 105 106 timer@1a220000 { 107 compatible = "arm,armv7-timer-mem"; 108 reg = <0x1a220000 0x1000>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 clock-frequency = <50000000>; 112 ranges; 113 114 frame@1a230000 { 115 frame-number = <0>; 116 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 117 reg = <0x1a230000 0x1000>; 118 }; 119 }; 120 121 uart0: serial@1a510000 { 122 compatible = "arm,pl011", "arm,primecell"; 123 reg = <0x1a510000 0x1000>; 124 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&uartclk>, <&refclk100mhz>; 126 clock-names = "uartclk", "apb_pclk"; 127 }; 128 129 uart1: serial@1a520000 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x1a520000 0x1000>; 132 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&uartclk>, <&refclk100mhz>; 134 clock-names = "uartclk", "apb_pclk"; 135 }; 136 137 mhu_hse1: mailbox@1b820000 { 138 compatible = "arm,mhuv2-tx", "arm,primecell"; 139 reg = <0x1b820000 0x1000>; 140 clocks = <&refclk100mhz>; 141 clock-names = "apb_pclk"; 142 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 143 #mbox-cells = <2>; 144 arm,mhuv2-protocols = <0 0>; 145 secure-status = "okay"; /* secure-world-only */ 146 status = "disabled"; 147 }; 148 149 mhu_seh1: mailbox@1b830000 { 150 compatible = "arm,mhuv2-rx", "arm,primecell"; 151 reg = <0x1b830000 0x1000>; 152 clocks = <&refclk100mhz>; 153 clock-names = "apb_pclk"; 154 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 155 #mbox-cells = <2>; 156 arm,mhuv2-protocols = <0 0>; 157 secure-status = "okay"; /* secure-world-only */ 158 status = "disabled"; 159 }; 160 }; 161}; 162