1 /*
2 * Copyright 2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of Freescale Semiconductor nor the
12 * names of its contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include "fsl_fman_prs.h"
34
fman_prs_get_err_event(struct fman_prs_regs * regs,uint32_t ev_mask)35 uint32_t fman_prs_get_err_event(struct fman_prs_regs *regs, uint32_t ev_mask)
36 {
37 return ioread32be(®s->fmpr_perr) & ev_mask;
38 }
39
fman_prs_get_err_ev_mask(struct fman_prs_regs * regs)40 uint32_t fman_prs_get_err_ev_mask(struct fman_prs_regs *regs)
41 {
42 return ioread32be(®s->fmpr_perer);
43 }
44
fman_prs_ack_err_event(struct fman_prs_regs * regs,uint32_t event)45 void fman_prs_ack_err_event(struct fman_prs_regs *regs, uint32_t event)
46 {
47 iowrite32be(event, ®s->fmpr_perr);
48 }
49
fman_prs_get_expt_event(struct fman_prs_regs * regs,uint32_t ev_mask)50 uint32_t fman_prs_get_expt_event(struct fman_prs_regs *regs, uint32_t ev_mask)
51 {
52 return ioread32be(®s->fmpr_pevr) & ev_mask;
53 }
54
fman_prs_get_expt_ev_mask(struct fman_prs_regs * regs)55 uint32_t fman_prs_get_expt_ev_mask(struct fman_prs_regs *regs)
56 {
57 return ioread32be(®s->fmpr_pever);
58 }
59
fman_prs_ack_expt_event(struct fman_prs_regs * regs,uint32_t event)60 void fman_prs_ack_expt_event(struct fman_prs_regs *regs, uint32_t event)
61 {
62 iowrite32be(event, ®s->fmpr_pevr);
63 }
64
fman_prs_defconfig(struct fman_prs_cfg * cfg)65 void fman_prs_defconfig(struct fman_prs_cfg *cfg)
66 {
67 cfg->port_id_stat = 0;
68 cfg->max_prs_cyc_lim = DEFAULT_MAX_PRS_CYC_LIM;
69 cfg->prs_exceptions = 0x03000000;
70 }
71
fman_prs_init(struct fman_prs_regs * regs,struct fman_prs_cfg * cfg)72 int fman_prs_init(struct fman_prs_regs *regs, struct fman_prs_cfg *cfg)
73 {
74 uint32_t tmp;
75
76 iowrite32be(cfg->max_prs_cyc_lim, ®s->fmpr_rpclim);
77 iowrite32be((FM_PCD_PRS_SINGLE_ECC | FM_PCD_PRS_PORT_IDLE_STS),
78 ®s->fmpr_pevr);
79
80 if (cfg->prs_exceptions & FM_PCD_EX_PRS_SINGLE_ECC)
81 iowrite32be(FM_PCD_PRS_SINGLE_ECC, ®s->fmpr_pever);
82 else
83 iowrite32be(0, ®s->fmpr_pever);
84
85 iowrite32be(FM_PCD_PRS_DOUBLE_ECC, ®s->fmpr_perr);
86
87 tmp = 0;
88 if (cfg->prs_exceptions & FM_PCD_EX_PRS_DOUBLE_ECC)
89 tmp |= FM_PCD_PRS_DOUBLE_ECC;
90 iowrite32be(tmp, ®s->fmpr_perer);
91
92 iowrite32be(cfg->port_id_stat, ®s->fmpr_ppsc);
93
94 return 0;
95 }
96
fman_prs_enable(struct fman_prs_regs * regs)97 void fman_prs_enable(struct fman_prs_regs *regs)
98 {
99 uint32_t tmp;
100
101 tmp = ioread32be(®s->fmpr_rpimac) | FM_PCD_PRS_RPIMAC_EN;
102 iowrite32be(tmp, ®s->fmpr_rpimac);
103 }
104
fman_prs_disable(struct fman_prs_regs * regs)105 void fman_prs_disable(struct fman_prs_regs *regs)
106 {
107 uint32_t tmp;
108
109 tmp = ioread32be(®s->fmpr_rpimac) & ~FM_PCD_PRS_RPIMAC_EN;
110 iowrite32be(tmp, ®s->fmpr_rpimac);
111 }
112
fman_prs_is_enabled(struct fman_prs_regs * regs)113 int fman_prs_is_enabled(struct fman_prs_regs *regs)
114 {
115 return ioread32be(®s->fmpr_rpimac) & FM_PCD_PRS_RPIMAC_EN;
116 }
117
fman_prs_set_stst_port_msk(struct fman_prs_regs * regs,uint32_t pid_msk)118 void fman_prs_set_stst_port_msk(struct fman_prs_regs *regs, uint32_t pid_msk)
119 {
120 iowrite32be(pid_msk, ®s->fmpr_ppsc);
121 }
122
fman_prs_set_stst(struct fman_prs_regs * regs,bool enable)123 void fman_prs_set_stst(struct fman_prs_regs *regs, bool enable)
124 {
125 if (enable)
126 iowrite32be(FM_PCD_PRS_PPSC_ALL_PORTS, ®s->fmpr_ppsc);
127 else
128 iowrite32be(0, ®s->fmpr_ppsc);
129 }
130