1//===-- BuiltinsHexagon.def - Hexagon Builtin function database --*- C++ -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the Hexagon-specific builtin function database. Users of 10// this file must define the BUILTIN macro to make use of this information. 11// 12//===----------------------------------------------------------------------===// 13 14// The format of this database matches clang/Basic/Builtins.def. 15 16#if defined(BUILTIN) && !defined(TARGET_BUILTIN) 17# define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS) 18#endif 19 20#pragma push_macro("V73") 21#define V73 "v73" 22#pragma push_macro("V71") 23#define V71 "v71|" V73 24#pragma push_macro("V69") 25#define V69 "v69|" V71 26#pragma push_macro("V68") 27#define V68 "v68|" V69 28#pragma push_macro("V67") 29#define V67 "v67|" V68 30#pragma push_macro("V66") 31#define V66 "v66|" V67 32#pragma push_macro("V65") 33#define V65 "v65|" V66 34#pragma push_macro("V62") 35#define V62 "v62|" V65 36#pragma push_macro("V60") 37#define V60 "v60|" V62 38#pragma push_macro("V55") 39#define V55 "v55|" V60 40#pragma push_macro("V5") 41#define V5 "v5|" V55 42 43#pragma push_macro("HVXV73") 44#define HVXV73 "hvxv73" 45#pragma push_macro("HVXV71") 46#define HVXV71 "hvxv71|" HVXV73 47#pragma push_macro("HVXV69") 48#define HVXV69 "hvxv69|" HVXV71 49#pragma push_macro("HVXV68") 50#define HVXV68 "hvxv68|" HVXV69 51#pragma push_macro("HVXV67") 52#define HVXV67 "hvxv67|" HVXV68 53#pragma push_macro("HVXV66") 54#define HVXV66 "hvxv66|" HVXV67 55#pragma push_macro("HVXV65") 56#define HVXV65 "hvxv65|" HVXV66 57#pragma push_macro("HVXV62") 58#define HVXV62 "hvxv62|" HVXV65 59#pragma push_macro("HVXV60") 60#define HVXV60 "hvxv60|" HVXV62 61 62 63// The builtins below are not autogenerated from iset.py. 64// Make sure you do not overwrite these. 65TARGET_BUILTIN(__builtin_SI_to_SXTHI_asrh, "ii", "", V5) 66TARGET_BUILTIN(__builtin_brev_ldd, "v*LLi*CLLi*iC", "", V5) 67TARGET_BUILTIN(__builtin_brev_ldw, "v*i*Ci*iC", "", V5) 68TARGET_BUILTIN(__builtin_brev_ldh, "v*s*Cs*iC", "", V5) 69TARGET_BUILTIN(__builtin_brev_lduh, "v*Us*CUs*iC", "", V5) 70TARGET_BUILTIN(__builtin_brev_ldb, "v*Sc*CSc*iC", "", V5) 71TARGET_BUILTIN(__builtin_brev_ldub, "v*Uc*CUc*iC", "", V5) 72TARGET_BUILTIN(__builtin_circ_ldd, "LLi*LLi*LLi*iIi", "", V5) 73TARGET_BUILTIN(__builtin_circ_ldw, "i*i*i*iIi", "", V5) 74TARGET_BUILTIN(__builtin_circ_ldh, "s*s*s*iIi", "", V5) 75TARGET_BUILTIN(__builtin_circ_lduh, "Us*Us*Us*iIi", "", V5) 76TARGET_BUILTIN(__builtin_circ_ldb, "c*c*c*iIi", "", V5) 77TARGET_BUILTIN(__builtin_circ_ldub, "Uc*Uc*Uc*iIi", "", V5) 78TARGET_BUILTIN(__builtin_brev_std, "LLi*CLLi*LLiiC", "", V5) 79TARGET_BUILTIN(__builtin_brev_stw, "i*Ci*iiC", "", V5) 80TARGET_BUILTIN(__builtin_brev_sth, "s*Cs*iiC", "", V5) 81TARGET_BUILTIN(__builtin_brev_sthhi, "s*Cs*iiC", "", V5) 82TARGET_BUILTIN(__builtin_brev_stb, "c*Cc*iiC", "", V5) 83TARGET_BUILTIN(__builtin_circ_std, "LLi*LLi*LLiiIi", "", V5) 84TARGET_BUILTIN(__builtin_circ_stw, "i*i*iiIi", "", V5) 85TARGET_BUILTIN(__builtin_circ_sth, "s*s*iiIi", "", V5) 86TARGET_BUILTIN(__builtin_circ_sthhi, "s*s*iiIi", "", V5) 87TARGET_BUILTIN(__builtin_circ_stb, "c*c*iiIi", "", V5) 88TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pci, "iv*IiivC*", "", V5) 89TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pci, "iv*IiivC*", "", V5) 90TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pci, "iv*IiivC*", "", V5) 91TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pci, "iv*IiivC*", "", V5) 92TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pci, "iv*IiivC*", "", V5) 93TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pci, "LLiv*IiivC*", "", V5) 94TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrub_pcr, "iv*ivC*", "", V5) 95TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrb_pcr, "iv*ivC*", "", V5) 96TARGET_BUILTIN(__builtin_HEXAGON_L2_loadruh_pcr, "iv*ivC*", "", V5) 97TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrh_pcr, "iv*ivC*", "", V5) 98TARGET_BUILTIN(__builtin_HEXAGON_L2_loadri_pcr, "iv*ivC*", "", V5) 99TARGET_BUILTIN(__builtin_HEXAGON_L2_loadrd_pcr, "LLiv*ivC*", "", V5) 100 101TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pci, "vv*IiiivC*", "", V5) 102TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pci, "vv*IiiivC*", "", V5) 103TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pci, "vv*IiiivC*", "", V5) 104TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pci, "vv*IiiivC*", "", V5) 105TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pci, "vv*IiiLLivC*", "", V5) 106TARGET_BUILTIN(__builtin_HEXAGON_S2_storerb_pcr, "vv*iivC*", "", V5) 107TARGET_BUILTIN(__builtin_HEXAGON_S2_storerh_pcr, "vv*iivC*", "", V5) 108TARGET_BUILTIN(__builtin_HEXAGON_S2_storerf_pcr, "vv*iivC*", "", V5) 109TARGET_BUILTIN(__builtin_HEXAGON_S2_storeri_pcr, "vv*iivC*", "", V5) 110TARGET_BUILTIN(__builtin_HEXAGON_S2_storerd_pcr, "vv*iLLivC*", "", V5) 111 112TARGET_BUILTIN(__builtin_HEXAGON_prefetch,"vv*","", V5) 113TARGET_BUILTIN(__builtin_HEXAGON_A6_vminub_RdP,"LLiLLiLLi","", V62) 114 115TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq,"vV64bv*V16i","", HVXV60) 116TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq,"vV64bv*V16i","", HVXV60) 117TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq,"vV64bv*V16i","", HVXV60) 118TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq,"vV64bv*V16i","", HVXV60) 119TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstoreq_128B,"vV128bv*V32i","", HVXV60) 120TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorenq_128B,"vV128bv*V32i","", HVXV60) 121TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentq_128B,"vV128bv*V32i","", HVXV60) 122TARGET_BUILTIN(__builtin_HEXAGON_V6_vmaskedstorentnq_128B,"vV128bv*V32i","", HVXV60) 123 124 125// These are only valid on v65 126TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt,"V32iV16iLLi","", "hvxv65") 127TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_128B,"V64iV32iLLi","", "hvxv65") 128TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65") 129TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpybub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65") 130TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt,"V32iV16iLLi","", "hvxv65") 131TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_128B,"V64iV32iLLi","", "hvxv65") 132TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc,"V32iV32iV16iLLi","", "hvxv65") 133TARGET_BUILTIN(__builtin_HEXAGON_V6_vrmpyub_rtt_acc_128B,"V64iV64iV32iLLi","", "hvxv65") 134 135#include "clang/Basic/BuiltinsHexagonDep.def" 136 137#pragma pop_macro("HVXV60") 138#pragma pop_macro("HVXV62") 139#pragma pop_macro("HVXV65") 140#pragma pop_macro("HVXV66") 141#pragma pop_macro("HVXV67") 142#pragma pop_macro("HVXV68") 143#pragma pop_macro("HVXV69") 144#pragma pop_macro("HVXV71") 145#pragma pop_macro("HVXV73") 146 147#pragma pop_macro("V5") 148#pragma pop_macro("V55") 149#pragma pop_macro("V60") 150#pragma pop_macro("V62") 151#pragma pop_macro("V65") 152#pragma pop_macro("V66") 153#pragma pop_macro("V67") 154#pragma pop_macro("V68") 155#pragma pop_macro("V69") 156#pragma pop_macro("V71") 157#pragma pop_macro("V73") 158 159#undef BUILTIN 160#undef TARGET_BUILTIN 161 162