1[ 2 { 3 "ArchStdEvent": "L1D_CACHE_RD" 4 }, 5 { 6 "ArchStdEvent": "L1D_CACHE_WR" 7 }, 8 { 9 "ArchStdEvent": "L1D_CACHE_REFILL_RD" 10 }, 11 { 12 "ArchStdEvent": "L1D_CACHE_REFILL_WR" 13 }, 14 { 15 "ArchStdEvent": "L1D_CACHE_REFILL_INNER" 16 }, 17 { 18 "ArchStdEvent": "L1D_CACHE_REFILL_OUTER" 19 }, 20 { 21 "ArchStdEvent": "L1D_CACHE_WB_VICTIM" 22 }, 23 { 24 "ArchStdEvent": "L1D_CACHE_WB_CLEAN" 25 }, 26 { 27 "ArchStdEvent": "L1D_CACHE_INVAL" 28 }, 29 { 30 "ArchStdEvent": "L1D_TLB_REFILL_RD" 31 }, 32 { 33 "ArchStdEvent": "L1D_TLB_REFILL_WR" 34 }, 35 { 36 "ArchStdEvent": "L1D_TLB_RD" 37 }, 38 { 39 "ArchStdEvent": "L1D_TLB_WR" 40 }, 41 { 42 "ArchStdEvent": "L2D_TLB_REFILL_RD" 43 }, 44 { 45 "ArchStdEvent": "L2D_TLB_REFILL_WR" 46 }, 47 { 48 "ArchStdEvent": "L2D_TLB_RD" 49 }, 50 { 51 "ArchStdEvent": "L2D_TLB_WR" 52 }, 53 { 54 "ArchStdEvent": "BUS_ACCESS_RD" 55 }, 56 { 57 "ArchStdEvent": "BUS_ACCESS_WR" 58 }, 59 { 60 "ArchStdEvent": "MEM_ACCESS_RD" 61 }, 62 { 63 "ArchStdEvent": "MEM_ACCESS_WR" 64 }, 65 { 66 "ArchStdEvent": "UNALIGNED_LD_SPEC" 67 }, 68 { 69 "ArchStdEvent": "UNALIGNED_ST_SPEC" 70 }, 71 { 72 "ArchStdEvent": "UNALIGNED_LDST_SPEC" 73 }, 74 { 75 "ArchStdEvent": "EXC_UNDEF" 76 }, 77 { 78 "ArchStdEvent": "EXC_SVC" 79 }, 80 { 81 "ArchStdEvent": "EXC_PABORT" 82 }, 83 { 84 "ArchStdEvent": "EXC_DABORT" 85 }, 86 { 87 "ArchStdEvent": "EXC_IRQ" 88 }, 89 { 90 "ArchStdEvent": "EXC_FIQ" 91 }, 92 { 93 "ArchStdEvent": "EXC_SMC" 94 }, 95 { 96 "ArchStdEvent": "EXC_HVC" 97 }, 98 { 99 "ArchStdEvent": "EXC_TRAP_PABORT" 100 }, 101 { 102 "ArchStdEvent": "EXC_TRAP_DABORT" 103 }, 104 { 105 "ArchStdEvent": "EXC_TRAP_OTHER" 106 }, 107 { 108 "ArchStdEvent": "EXC_TRAP_IRQ" 109 }, 110 { 111 "ArchStdEvent": "EXC_TRAP_FIQ" 112 } 113] 114