1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 *
18 * NO WARRANTY
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
30 */
31
32 #include <sys/cdefs.h>
33 /*
34 * Broadcom Common PCI/PCIe Support.
35 *
36 * This base driver implementation is shared by the bhnd_pcib (root complex)
37 * and bhnd_pci_hostb (host bridge) drivers.
38 */
39
40 #include <sys/param.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/bus.h>
44 #include <sys/module.h>
45 #include <sys/systm.h>
46
47 #include <machine/bus.h>
48 #include <sys/rman.h>
49 #include <machine/resource.h>
50
51 #include <dev/bhnd/bhnd.h>
52 #include <dev/mdio/mdio.h>
53
54 #include "bhnd_pcireg.h"
55 #include "bhnd_pcivar.h"
56
57 static int bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc);
58 static int bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd);
59 static int bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc);
60 static void bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc);
61 static int bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc,
62 uint32_t cmd);
63 static int bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
64 uint16_t *data_read);
65
66 static struct bhnd_device_quirk bhnd_pci_quirks[];
67 static struct bhnd_device_quirk bhnd_pcie_quirks[];
68
69 #define BHND_PCI_QUIRKS bhnd_pci_quirks
70 #define BHND_PCIE_QUIRKS bhnd_pcie_quirks
71 #define BHND_PCI_DEV(_core, _desc, ...) \
72 { BHND_DEVICE(BCM, _core, _desc, BHND_ ## _core ## _QUIRKS, \
73 ## __VA_ARGS__), BHND_PCI_REGFMT_ ## _core }
74
75 static const struct bhnd_pci_device {
76 struct bhnd_device device;
77 bhnd_pci_regfmt_t regfmt; /**< register format */
78 } bhnd_pci_devs[] = {
79 BHND_PCI_DEV(PCI, "Host-PCI bridge", BHND_DF_HOSTB),
80 BHND_PCI_DEV(PCI, "PCI-BHND bridge", BHND_DF_SOC),
81 BHND_PCI_DEV(PCIE, "PCIe-G1 Host-PCI bridge", BHND_DF_HOSTB),
82 BHND_PCI_DEV(PCIE, "PCIe-G1 PCI-BHND bridge", BHND_DF_SOC),
83 { BHND_DEVICE_END, 0 }
84 };
85
86 /* Device quirks tables */
87 static struct bhnd_device_quirk bhnd_pci_quirks[] = { BHND_DEVICE_QUIRK_END };
88 static struct bhnd_device_quirk bhnd_pcie_quirks[] = {
89 BHND_CORE_QUIRK(HWREV_GTE(10), BHND_PCI_QUIRK_SD_C22_EXTADDR),
90
91 BHND_DEVICE_QUIRK_END
92 };
93
94 #define BHND_PCIE_MDIO_CTL_DELAY 10 /**< usec delay required between
95 * MDIO_CTL/MDIO_DATA accesses. */
96 #define BHND_PCIE_MDIO_RETRY_DELAY 2000 /**< usec delay before retrying
97 * BHND_PCIE_MDIOCTL_DONE. */
98 #define BHND_PCIE_MDIO_RETRY_COUNT 200 /**< number of times to loop waiting
99 * for BHND_PCIE_MDIOCTL_DONE. */
100
101 #define BHND_PCI_READ_4(_sc, _reg) \
102 bhnd_bus_read_4((_sc)->mem_res, (_reg))
103 #define BHND_PCI_WRITE_4(_sc, _reg, _val) \
104 bhnd_bus_write_4((_sc)->mem_res, (_reg), (_val))
105
106 #define BHND_PCIE_ASSERT(sc) \
107 KASSERT(bhnd_get_class(sc->dev) == BHND_DEVCLASS_PCIE, \
108 ("not a pcie device!"));
109
110 int
bhnd_pci_generic_probe(device_t dev)111 bhnd_pci_generic_probe(device_t dev)
112 {
113 const struct bhnd_device *id;
114
115 id = bhnd_device_lookup(dev, &bhnd_pci_devs[0].device,
116 sizeof(bhnd_pci_devs[0]));
117 if (id == NULL)
118 return (ENXIO);
119
120 bhnd_set_custom_core_desc(dev, id->desc);
121 return (BUS_PROBE_DEFAULT);
122 }
123
124 int
bhnd_pci_generic_attach(device_t dev)125 bhnd_pci_generic_attach(device_t dev)
126 {
127 struct bhnd_pci_softc *sc;
128
129 sc = device_get_softc(dev);
130 sc->dev = dev;
131 sc->quirks = bhnd_device_quirks(dev, &bhnd_pci_devs[0].device,
132 sizeof(bhnd_pci_devs[0]));
133
134 /* Allocate bus resources */
135 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
136 RF_ACTIVE);
137 if (sc->mem_res == NULL)
138 return (ENXIO);
139
140 BHND_PCI_LOCK_INIT(sc);
141
142 /* Probe and attach children */
143 bus_attach_children(dev);
144
145 return (0);
146 }
147
148 int
bhnd_pci_generic_detach(device_t dev)149 bhnd_pci_generic_detach(device_t dev)
150 {
151 struct bhnd_pci_softc *sc;
152 int error;
153
154 sc = device_get_softc(dev);
155
156 if ((error = bus_generic_detach(dev)))
157 return (error);
158
159 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res);
160
161 BHND_PCI_LOCK_DESTROY(sc);
162
163 return (0);
164 }
165
166 static struct resource_list *
bhnd_pci_get_resource_list(device_t dev,device_t child)167 bhnd_pci_get_resource_list(device_t dev, device_t child)
168 {
169 struct bhnd_pci_devinfo *dinfo;
170
171 if (device_get_parent(child) != dev)
172 return (NULL);
173
174 dinfo = device_get_ivars(child);
175 return (&dinfo->resources);
176 }
177
178 static device_t
bhnd_pci_add_child(device_t dev,u_int order,const char * name,int unit)179 bhnd_pci_add_child(device_t dev, u_int order, const char *name, int unit)
180 {
181 struct bhnd_pci_devinfo *dinfo;
182 device_t child;
183
184 child = device_add_child_ordered(dev, order, name, unit);
185 if (child == NULL)
186 return (NULL);
187
188 dinfo = malloc(sizeof(struct bhnd_pci_devinfo), M_DEVBUF, M_NOWAIT);
189 if (dinfo == NULL) {
190 device_delete_child(dev, child);
191 return (NULL);
192 }
193
194 resource_list_init(&dinfo->resources);
195
196 device_set_ivars(child, dinfo);
197 return (child);
198 }
199
200 static void
bhnd_pci_child_deleted(device_t dev,device_t child)201 bhnd_pci_child_deleted(device_t dev, device_t child)
202 {
203 struct bhnd_pci_devinfo *dinfo;
204
205 if (device_get_parent(child) != dev)
206 return;
207
208 dinfo = device_get_ivars(child);
209 if (dinfo != NULL) {
210 resource_list_free(&dinfo->resources);
211 free(dinfo, M_DEVBUF);
212 }
213
214 device_set_ivars(child, NULL);
215 }
216
217 int
bhnd_pci_generic_suspend(device_t dev)218 bhnd_pci_generic_suspend(device_t dev)
219 {
220 return (bus_generic_suspend(dev));
221 }
222
223 int
bhnd_pci_generic_resume(device_t dev)224 bhnd_pci_generic_resume(device_t dev)
225 {
226 return (bus_generic_resume(dev));
227 }
228
229 /**
230 * Read a 32-bit PCIe TLP/DLLP/PLP protocol register.
231 *
232 * @param sc The bhndb_pci driver state.
233 * @param addr The protocol register offset.
234 */
235 uint32_t
bhnd_pcie_read_proto_reg(struct bhnd_pci_softc * sc,uint32_t addr)236 bhnd_pcie_read_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr)
237 {
238 uint32_t val;
239
240 BHND_PCIE_ASSERT(sc);
241
242 BHND_PCI_LOCK(sc);
243 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
244 val = BHND_PCI_READ_4(sc, BHND_PCIE_IND_DATA);
245 BHND_PCI_UNLOCK(sc);
246
247 return (val);
248 }
249
250 /**
251 * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value.
252 *
253 * @param sc The bhndb_pci driver state.
254 * @param addr The protocol register offset.
255 * @param val The value to write to @p addr.
256 */
257 void
bhnd_pcie_write_proto_reg(struct bhnd_pci_softc * sc,uint32_t addr,uint32_t val)258 bhnd_pcie_write_proto_reg(struct bhnd_pci_softc *sc, uint32_t addr,
259 uint32_t val)
260 {
261 BHND_PCIE_ASSERT(sc);
262
263 BHND_PCI_LOCK(sc);
264 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_ADDR, addr);
265 BHND_PCI_WRITE_4(sc, BHND_PCIE_IND_DATA, val);
266 BHND_PCI_UNLOCK(sc);
267 }
268
269 /* Spin until the MDIO device reports itself as idle, or timeout is reached. */
270 static int
bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc * sc)271 bhnd_pcie_mdio_wait_idle(struct bhnd_pci_softc *sc)
272 {
273 uint32_t ctl;
274
275 /* Spin waiting for the BUSY flag to clear */
276 for (int i = 0; i < BHND_PCIE_MDIO_RETRY_COUNT; i++) {
277 ctl = BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_CTL);
278 if ((ctl & BHND_PCIE_MDIOCTL_DONE))
279 return (0);
280
281 DELAY(BHND_PCIE_MDIO_RETRY_DELAY);
282 }
283
284 return (ETIMEDOUT);
285 }
286
287 /**
288 * Write an MDIO IOCTL and wait for completion.
289 */
290 static int
bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc * sc,uint32_t cmd)291 bhnd_pcie_mdio_ioctl(struct bhnd_pci_softc *sc, uint32_t cmd)
292 {
293 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
294
295 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_CTL, cmd);
296 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
297 return (0);
298 }
299
300 /**
301 * Enable MDIO device
302 */
303 static int
bhnd_pcie_mdio_enable(struct bhnd_pci_softc * sc)304 bhnd_pcie_mdio_enable(struct bhnd_pci_softc *sc)
305 {
306 uint32_t ctl;
307
308 BHND_PCIE_ASSERT(sc);
309
310 /* Enable MDIO clock and preamble mode */
311 ctl = BHND_PCIE_MDIOCTL_PREAM_EN|BHND_PCIE_MDIOCTL_DIVISOR_VAL;
312 return (bhnd_pcie_mdio_ioctl(sc, ctl));
313 }
314
315 /**
316 * Disable MDIO device.
317 */
318 static void
bhnd_pcie_mdio_disable(struct bhnd_pci_softc * sc)319 bhnd_pcie_mdio_disable(struct bhnd_pci_softc *sc)
320 {
321 if (bhnd_pcie_mdio_ioctl(sc, 0))
322 device_printf(sc->dev, "failed to disable MDIO clock\n");
323 }
324
325 /**
326 * Issue a write command and wait for completion
327 */
328 static int
bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc * sc,uint32_t cmd)329 bhnd_pcie_mdio_cmd_write(struct bhnd_pci_softc *sc, uint32_t cmd)
330 {
331 int error;
332
333 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
334
335 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_WRITE;
336
337 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
338 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
339
340 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
341 return (error);
342
343 return (0);
344 }
345
346 /**
347 * Issue an MDIO read command, wait for completion, and return
348 * the result in @p data_read.
349 */
350 static int
bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc * sc,uint32_t cmd,uint16_t * data_read)351 bhnd_pcie_mdio_cmd_read(struct bhnd_pci_softc *sc, uint32_t cmd,
352 uint16_t *data_read)
353 {
354 int error;
355
356 BHND_PCI_LOCK_ASSERT(sc, MA_OWNED);
357
358 cmd |= BHND_PCIE_MDIODATA_START|BHND_PCIE_MDIODATA_TA|BHND_PCIE_MDIODATA_CMD_READ;
359 BHND_PCI_WRITE_4(sc, BHND_PCIE_MDIO_DATA, cmd);
360 DELAY(BHND_PCIE_MDIO_CTL_DELAY);
361
362 if ((error = bhnd_pcie_mdio_wait_idle(sc)))
363 return (error);
364
365 *data_read = (BHND_PCI_READ_4(sc, BHND_PCIE_MDIO_DATA) &
366 BHND_PCIE_MDIODATA_DATA_MASK);
367 return (0);
368 }
369
370 int
bhnd_pcie_mdio_read(struct bhnd_pci_softc * sc,int phy,int reg)371 bhnd_pcie_mdio_read(struct bhnd_pci_softc *sc, int phy, int reg)
372 {
373 uint32_t cmd;
374 uint16_t val;
375 int error;
376
377 /* Enable MDIO access */
378 BHND_PCI_LOCK(sc);
379 bhnd_pcie_mdio_enable(sc);
380
381 /* Issue the read */
382 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
383 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
384
385 /* Disable MDIO access */
386 bhnd_pcie_mdio_disable(sc);
387 BHND_PCI_UNLOCK(sc);
388
389 if (error)
390 return (~0U);
391
392 return (val);
393 }
394
395 int
bhnd_pcie_mdio_write(struct bhnd_pci_softc * sc,int phy,int reg,int val)396 bhnd_pcie_mdio_write(struct bhnd_pci_softc *sc, int phy, int reg, int val)
397 {
398 uint32_t cmd;
399 int error;
400
401 /* Enable MDIO access */
402 BHND_PCI_LOCK(sc);
403 bhnd_pcie_mdio_enable(sc);
404
405 /* Issue the write */
406 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) | (val & BHND_PCIE_MDIODATA_DATA_MASK);
407 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
408
409 /* Disable MDIO access */
410 bhnd_pcie_mdio_disable(sc);
411 BHND_PCI_UNLOCK(sc);
412
413 return (error);
414 }
415
416 int
bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc * sc,int phy,int devaddr,int reg)417 bhnd_pcie_mdio_read_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
418 int reg)
419 {
420 uint32_t cmd;
421 uint16_t val;
422 int error;
423
424 if (devaddr == MDIO_DEVADDR_NONE)
425 return (bhnd_pcie_mdio_read(sc, phy, reg));
426
427 /* Extended register access is only supported for the SerDes device,
428 * using the non-standard C22 extended address mechanism */
429 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
430 phy != BHND_PCIE_PHYADDR_SD)
431 {
432 return (~0U);
433 }
434
435 /* Enable MDIO access */
436 BHND_PCI_LOCK(sc);
437 bhnd_pcie_mdio_enable(sc);
438
439 /* Write the block address to the address extension register */
440 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
441 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
442 goto cleanup;
443
444 /* Issue the read */
445 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg);
446 error = bhnd_pcie_mdio_cmd_read(sc, cmd, &val);
447
448 cleanup:
449 bhnd_pcie_mdio_disable(sc);
450 BHND_PCI_UNLOCK(sc);
451
452 if (error)
453 return (~0U);
454
455 return (val);
456 }
457
458 int
bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc * sc,int phy,int devaddr,int reg,int val)459 bhnd_pcie_mdio_write_ext(struct bhnd_pci_softc *sc, int phy, int devaddr,
460 int reg, int val)
461 {
462 uint32_t cmd;
463 int error;
464
465 if (devaddr == MDIO_DEVADDR_NONE)
466 return (bhnd_pcie_mdio_write(sc, phy, reg, val));
467
468 /* Extended register access is only supported for the SerDes device,
469 * using the non-standard C22 extended address mechanism */
470 if (!(sc->quirks & BHND_PCI_QUIRK_SD_C22_EXTADDR) ||
471 phy != BHND_PCIE_PHYADDR_SD)
472 {
473 return (~0U);
474 }
475
476 /* Enable MDIO access */
477 BHND_PCI_LOCK(sc);
478 bhnd_pcie_mdio_enable(sc);
479
480 /* Write the block address to the address extension register */
481 cmd = BHND_PCIE_MDIODATA_ADDR(phy, BHND_PCIE_SD_ADDREXT) | devaddr;
482 if ((error = bhnd_pcie_mdio_cmd_write(sc, cmd)))
483 goto cleanup;
484
485 /* Issue the write */
486 cmd = BHND_PCIE_MDIODATA_ADDR(phy, reg) |
487 (val & BHND_PCIE_MDIODATA_DATA_MASK);
488 error = bhnd_pcie_mdio_cmd_write(sc, cmd);
489
490 cleanup:
491 bhnd_pcie_mdio_disable(sc);
492 BHND_PCI_UNLOCK(sc);
493
494 return (error);
495 }
496
497 static device_method_t bhnd_pci_methods[] = {
498 /* Device interface */
499 DEVMETHOD(device_probe, bhnd_pci_generic_probe),
500 DEVMETHOD(device_attach, bhnd_pci_generic_attach),
501 DEVMETHOD(device_detach, bhnd_pci_generic_detach),
502 DEVMETHOD(device_suspend, bhnd_pci_generic_suspend),
503 DEVMETHOD(device_resume, bhnd_pci_generic_resume),
504
505 /* Bus interface */
506 DEVMETHOD(bus_add_child, bhnd_pci_add_child),
507 DEVMETHOD(bus_child_deleted, bhnd_pci_child_deleted),
508 DEVMETHOD(bus_print_child, bus_generic_print_child),
509 DEVMETHOD(bus_get_resource_list, bhnd_pci_get_resource_list),
510 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
511 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
512 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource),
513
514 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
515 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
516 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
517 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
518 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
519
520 DEVMETHOD_END
521 };
522
523 DEFINE_CLASS_0(bhnd_pci, bhnd_pci_driver, bhnd_pci_methods, sizeof(struct bhnd_pci_softc));
524 MODULE_DEPEND(bhnd_pci, bhnd, 1, 1, 1);
525 MODULE_DEPEND(bhnd_pci, pci, 1, 1, 1);
526 MODULE_VERSION(bhnd_pci, 1);
527