xref: /illumos-gate/usr/src/uts/common/io/audio/drv/audiovia823x/audiovia823x.h (revision 68c47f65208790c466e5e484f2293d3baed71c6a)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Purpose: Definitions for the via8233 driver
29  */
30 /*
31  * This file is part of Open Sound System
32  *
33  * Copyright (C) 4Front Technologies 1996-2008.
34  *
35  * This software is released under CDDL 1.0 source license.
36  * See the COPYING file included in the main directory of this source
37  * distribution for the license terms and conditions.
38  */
39 #ifndef	AUDIOVIA823X_H
40 #define	AUDIOVIA823X_H
41 
42 #define	AUVIA_NAME		"audiovia823x"
43 
44 #define	VIA_VENDOR_ID		0x1106
45 #define	VIA_8233_ID		0x3059
46 #define	VIA_8233A_ID		0x7059
47 
48 /* pci configuration registers */
49 #define	AUVIA_PCICFG		0x40		/* Via chip specific cfg reg */
50 #define	AUVIA_PCICFG_LEGACY	0x00ff0000	/* legacy enables mask */
51 #define	AUVIA_PCICFG_ACLINKEN	0x00008000	/* AC'97 link enable */
52 #define	AUVIA_PCICFG_NRST	0x00004000	/* inverse of AC'97 reset */
53 #define	AUVIA_PCICFG_ACSYNC	0x00002000	/* AC'97 sync */
54 #define	AUVIA_PCICFG_SRCEN	0x00000800	/* sample rate converter en */
55 #define	AUVIA_PCICFG_SGDEN	0x00000400	/* SGD enable */
56 #define	AUVIA_PCICFG_FMEN	0x00000200 	/* FM synth enable (legacy) */
57 #define	AUVIA_PCICFG_SBEN	0x00000100	/* SB compat enable (legacy) */
58 #define	AUVIA_PCICFG_PRIVALID	0x00000001	/* primary codec ready */
59 
60 #define	AUVIA_PLAY_SGD_NUM	1
61 #define	AUVIA_REC_SGD_NUM	0
62 #define	AUVIA_NUM_PORTC		2
63 #define	AUVIA_NUM_SGD		16	/* number of fragments */
64 
65 #define	AUVIA_SGD_EOL		0x80000000
66 #define	AUVIA_SGD_FLAG		0x40000000
67 
68 #define	CODEC_TIMEOUT_COUNT		500
69 
70 #define	REG_PLAYBASE		0x40	/* Multichannel SGD */
71 #define	REG_RECBASE		0x60
72 #define	REG_CODEC		0x80	/* Access AC97 Codec */
73 #define	REG_GSTAT		0x84	/* Global status */
74 
75 /* REG_CODEC */
76 #define	CODEC_IN_CMD		0x01000000	/* busy in sending */
77 #define	CODEC_STA_VALID		0x02000000	/* 1:status data is valid */
78 #define	CODEC_RD		0x00800000	/* Read CODEC status */
79 #define	CODEC_WR		0x00000000	/* Write CODEC status */
80 #define	CODEC_INDEX		0x007F0000	/* Index of command register */
81 #define	CODEC_DATA		0x0000FFFF	/* AC97 status register data */
82 
83 /* registers that are offsets relative to a port */
84 #define	OFF_STATUS		0x00
85 #define	OFF_CTRL		0x01
86 #define	OFF_PLAYFMT		0x02
87 #define	OFF_RECFIFO		0x02
88 #define	OFF_DMA			0x04
89 #define	OFF_CHANNELS		0x08
90 #define	OFF_RECFMT		0x08
91 #define	OFF_COUNT		0x0C
92 
93 /* bits for above offsets */
94 #define	STATUS_INTR		0x3
95 
96 #define	CTRL_START		0x80
97 #define	CTRL_TERMINATE		0x40
98 #define	CTRL_AUTOSTART		0x20
99 #define	CTRL_MULTICHORDER	0x10	/* SGD 0x40 only, Center/LFE order */
100 #define	CTRL_FLAG		0x01
101 
102 #define	PLAYFMT_16BIT		0x80
103 #define	PLAYFMT_STEREO		0x20	/* Num channels (1-6), upper nybble */
104 #define	PLAYFMT_6CH		0x60
105 #define	PLAYFMT_4CH		0x40
106 
107 #define	RECFIFO_ENABLE		0x40
108 
109 #define	RECFMT_48K		0x00ffffff
110 #define	RECFMT_STEREO		0x00100000
111 #define	RECFMT_16BIT		0x00200000
112 
113 
114 typedef struct {
115 	unsigned int phaddr;
116 	unsigned int flags;
117 } SGD_entry;
118 
119 typedef struct auvia_portc auvia_portc_t;
120 typedef struct auvia_devc auvia_devc_t;
121 
122 struct auvia_portc {
123 	auvia_devc_t		*devc;
124 	audio_engine_t		*engine;
125 	caddr_t			base;		/* base for registers */
126 	int			nchan;
127 
128 	ddi_dma_handle_t	sgd_dmah;	/* dma for descriptors */
129 	ddi_acc_handle_t	sgd_acch;
130 	uint32_t		sgd_paddr;
131 	caddr_t			sgd_kaddr;
132 
133 	ddi_dma_handle_t	buf_dmah;	/* dma for buffers */
134 	ddi_acc_handle_t	buf_acch;
135 	uint32_t		buf_paddr;
136 	caddr_t			buf_kaddr;
137 	size_t			buf_size;
138 	int			syncdir;
139 
140 	unsigned		nframes;
141 	unsigned		pos;
142 
143 	uint64_t		count;
144 
145 	/* helper functions */
146 	void			(*reset)(auvia_portc_t *);
147 };
148 
149 
150 struct auvia_devc {
151 	dev_info_t		*dip;
152 	audio_dev_t		*adev;
153 	ac97_t			*ac97;
154 
155 	char			*chip_name;
156 	int			chip_type;
157 #define	CHIP_8233		0
158 #define	CHIP_8233A		1
159 
160 	/* registers */
161 	ddi_acc_handle_t	pcih;
162 	ddi_acc_handle_t	regsh;
163 	caddr_t			base;
164 
165 	auvia_portc_t		*portc[AUVIA_NUM_PORTC];
166 };
167 
168 #define	AUVIA_KIOP(X)	((kstat_intr_t *)(X->ksp->ks_data))
169 
170 #define	INL(devc, reg)		ddi_get32(devc->regsh, (void *)(reg))
171 
172 #define	INB(devc, reg)		ddi_get8(devc->regsh, (void *)(reg))
173 
174 #define	OUTL(devc, reg, val)	ddi_put32(devc->regsh, (void *)(reg), (val))
175 
176 #define	OUTB(devc, reg, val)	ddi_put8(devc->regsh, (void *)(reg), (val))
177 
178 #endif /* AUDIOVIA823X_H */
179