1 /*-
2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by BAE Systems, the University of Cambridge
6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
8 * (TC) research program.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <machine/bus.h>
39
40 #include <arm64/coresight/coresight.h>
41 #include <arm64/coresight/coresight_etm4x.h>
42
43 #include "coresight_if.h"
44
45 #define ETM_DEBUG
46 #undef ETM_DEBUG
47
48 #ifdef ETM_DEBUG
49 #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
50 #else
51 #define dprintf(fmt, ...)
52 #endif
53
54 /*
55 * Typical trace flow:
56 *
57 * CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
58 * CPU1 -> ETM1 -> funnel1 -^
59 * CPU2 -> ETM2 -> funnel1 -^
60 * CPU3 -> ETM3 -> funnel1 -^
61 */
62
63 static struct resource_spec etm_spec[] = {
64 { SYS_RES_MEMORY, 0, RF_ACTIVE },
65 { -1, 0 }
66 };
67
68 static int
etm_prepare(device_t dev,struct coresight_event * event)69 etm_prepare(device_t dev, struct coresight_event *event)
70 {
71 struct etm_softc *sc;
72 uint32_t reg;
73 int i;
74
75 sc = device_get_softc(dev);
76
77 /* Configure ETM */
78
79 /*
80 * Enable the return stack, global timestamping,
81 * Context ID, and Virtual context identifier tracing.
82 */
83 reg = TRCCONFIGR_RS | TRCCONFIGR_TS;
84 reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID;
85 reg |= TRCCONFIGR_INSTP0_LDRSTR;
86 reg |= TRCCONFIGR_COND_ALL;
87 bus_write_4(sc->res, TRCCONFIGR, reg);
88
89 /* Disable all event tracing. */
90 bus_write_4(sc->res, TRCEVENTCTL0R, 0);
91 bus_write_4(sc->res, TRCEVENTCTL1R, 0);
92
93 /* Disable stalling, if implemented. */
94 bus_write_4(sc->res, TRCSTALLCTLR, 0);
95
96 /* Enable trace synchronization every 4096 bytes of trace. */
97 bus_write_4(sc->res, TRCSYNCPR, TRCSYNCPR_4K);
98
99 /* Set a value for the trace ID */
100 bus_write_4(sc->res, TRCTRACEIDR, event->etm.trace_id);
101
102 /*
103 * Disable the timestamp event. The trace unit still generates
104 * timestamps due to other reasons such as trace synchronization.
105 */
106 bus_write_4(sc->res, TRCTSCTLR, 0);
107
108 /*
109 * Enable ViewInst to trace everything, with the start/stop
110 * logic started.
111 */
112 reg = TRCVICTLR_SSSTATUS;
113
114 /* The number of the single resource used to activate the event. */
115 reg |= (1 << EVENT_SEL_S);
116
117 if (event->excp_level > 2)
118 return (-1);
119
120 reg |= TRCVICTLR_EXLEVEL_NS_M;
121 reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level);
122 reg |= TRCVICTLR_EXLEVEL_S_M;
123 reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level);
124 bus_write_4(sc->res, TRCVICTLR, reg);
125
126 for (i = 0; i < event->naddr * 2; i++) {
127 dprintf("configure range %d, address %lx\n",
128 i, event->addr[i]);
129 bus_write_8(sc->res, TRCACVR(i), event->addr[i]);
130
131 reg = 0;
132 /* Secure state */
133 reg |= TRCACATR_EXLEVEL_S_M;
134 reg &= ~TRCACATR_EXLEVEL_S(event->excp_level);
135 /* Non-secure state */
136 reg |= TRCACATR_EXLEVEL_NS_M;
137 reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level);
138 bus_write_4(sc->res, TRCACATR(i), reg);
139
140 /* Address range is included */
141 reg = bus_read_4(sc->res, TRCVIIECTLR);
142 reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2));
143 bus_write_4(sc->res, TRCVIIECTLR, reg);
144 }
145
146 /* No address filtering for ViewData. */
147 bus_write_4(sc->res, TRCVDARCCTLR, 0);
148
149 /* Clear the STATUS bit to zero */
150 bus_write_4(sc->res, TRCSSCSR(0), 0);
151
152 if (event->naddr == 0) {
153 /* No address range filtering for ViewInst. */
154 bus_write_4(sc->res, TRCVIIECTLR, 0);
155 }
156
157 /* No start or stop points for ViewInst. */
158 bus_write_4(sc->res, TRCVISSCTLR, 0);
159
160 /* Disable ViewData */
161 bus_write_4(sc->res, TRCVDCTLR, 0);
162
163 /* No address filtering for ViewData. */
164 bus_write_4(sc->res, TRCVDSACCTLR, 0);
165
166 return (0);
167 }
168
169 static int
etm_init(device_t dev)170 etm_init(device_t dev)
171 {
172 struct etm_softc *sc;
173 uint32_t reg __unused;
174
175 sc = device_get_softc(dev);
176
177 /* Unlocking Coresight */
178 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
179
180 /* Unlocking ETM */
181 bus_write_4(sc->res, TRCOSLAR, 0);
182
183 reg = bus_read_4(sc->res, TRCIDR(1));
184 dprintf("ETM Version: %d.%d\n",
185 (reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S,
186 (reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S);
187
188 return (0);
189 }
190
191 static int
etm_enable(device_t dev,struct endpoint * endp,struct coresight_event * event)192 etm_enable(device_t dev, struct endpoint *endp,
193 struct coresight_event *event)
194 {
195 struct etm_softc *sc;
196 uint32_t reg;
197
198 sc = device_get_softc(dev);
199
200 etm_prepare(dev, event);
201
202 /* Enable the trace unit */
203 bus_write_4(sc->res, TRCPRGCTLR, TRCPRGCTLR_EN);
204
205 /* Wait for an IDLE bit to be LOW */
206 do {
207 reg = bus_read_4(sc->res, TRCSTATR);
208 } while ((reg & TRCSTATR_IDLE) == 1);
209
210 if ((bus_read_4(sc->res, TRCPRGCTLR) & TRCPRGCTLR_EN) == 0)
211 panic("etm is not enabled\n");
212
213 return (0);
214 }
215
216 static void
etm_disable(device_t dev,struct endpoint * endp,struct coresight_event * event)217 etm_disable(device_t dev, struct endpoint *endp,
218 struct coresight_event *event)
219 {
220 struct etm_softc *sc;
221 uint32_t reg;
222
223 sc = device_get_softc(dev);
224
225 /* Disable the trace unit */
226 bus_write_4(sc->res, TRCPRGCTLR, 0);
227
228 /* Wait for an IDLE bit */
229 do {
230 reg = bus_read_4(sc->res, TRCSTATR);
231 } while ((reg & TRCSTATR_IDLE) == 0);
232 }
233
234 int
etm_attach(device_t dev)235 etm_attach(device_t dev)
236 {
237 struct coresight_desc desc;
238 struct etm_softc *sc;
239
240 sc = device_get_softc(dev);
241
242 if (bus_alloc_resources(dev, etm_spec, &sc->res) != 0) {
243 device_printf(dev, "cannot allocate resources for device\n");
244 return (ENXIO);
245 }
246
247 desc.pdata = sc->pdata;
248 desc.dev = dev;
249 desc.dev_type = CORESIGHT_ETMV4;
250 coresight_register(&desc);
251
252 return (0);
253 }
254
255 static device_method_t etm_methods[] = {
256 /* Coresight interface */
257 DEVMETHOD(coresight_init, etm_init),
258 DEVMETHOD(coresight_enable, etm_enable),
259 DEVMETHOD(coresight_disable, etm_disable),
260 DEVMETHOD_END
261 };
262
263 DEFINE_CLASS_0(etm, etm_driver, etm_methods, sizeof(struct etm_softc));
264