1 /*-
2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by BAE Systems, the University of Cambridge
6 * Computer Laboratory, and Memorial University under DARPA/AFRL contract
7 * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing
8 * (TC) research program.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/bus.h>
35 #include <sys/rman.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <machine/bus.h>
39
40 #include <dev/ofw/ofw_bus.h>
41 #include <dev/ofw/ofw_bus_subr.h>
42
43 #include <arm64/coresight/coresight.h>
44
45 #include "coresight_if.h"
46
47 #define EDPCSR 0x0a0
48 #define EDCIDSR 0x0a4
49 #define EDVIDSR 0x0a8
50 #define EDPCSR_HI 0x0ac
51 #define EDOSLAR 0x300
52 #define EDPRCR 0x310
53 #define EDPRCR_COREPURQ (1 << 3)
54 #define EDPRCR_CORENPDRQ (1 << 0)
55 #define EDPRSR 0x314
56 #define EDDEVID1 0xfc4
57 #define EDDEVID 0xfc8
58
59 static struct ofw_compat_data compat_data[] = {
60 { "arm,coresight-cpu-debug", 1 },
61 { NULL, 0 }
62 };
63
64 struct debug_softc {
65 struct resource *res;
66 struct coresight_platform_data *pdata;
67 };
68
69 static struct resource_spec debug_spec[] = {
70 { SYS_RES_MEMORY, 0, RF_ACTIVE },
71 { -1, 0 }
72 };
73
74 static int
debug_init(device_t dev)75 debug_init(device_t dev)
76 {
77 struct debug_softc *sc;
78 uint32_t reg;
79
80 sc = device_get_softc(dev);
81
82 /* Unlock Coresight */
83 bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK);
84
85 /* Unlock Debug */
86 bus_write_4(sc->res, EDOSLAR, 0);
87
88 /* Already initialized? */
89 reg = bus_read_4(sc->res, EDPRCR);
90 if (reg & EDPRCR_CORENPDRQ)
91 return (0);
92
93 /* Enable power */
94 reg |= EDPRCR_COREPURQ;
95 bus_write_4(sc->res, EDPRCR, reg);
96
97 do {
98 reg = bus_read_4(sc->res, EDPRSR);
99 } while ((reg & EDPRCR_CORENPDRQ) == 0);
100
101 return (0);
102 }
103
104 static int
debug_probe(device_t dev)105 debug_probe(device_t dev)
106 {
107
108 if (!ofw_bus_status_okay(dev))
109 return (ENXIO);
110
111 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
112 return (ENXIO);
113
114 device_set_desc(dev, "Coresight CPU Debug");
115
116 return (BUS_PROBE_DEFAULT);
117 }
118
119 static int
debug_attach(device_t dev)120 debug_attach(device_t dev)
121 {
122 struct coresight_desc desc;
123 struct debug_softc *sc;
124
125 sc = device_get_softc(dev);
126
127 if (bus_alloc_resources(dev, debug_spec, &sc->res) != 0) {
128 device_printf(dev, "cannot allocate resources for device\n");
129 return (ENXIO);
130 }
131
132 sc->pdata = coresight_fdt_get_platform_data(dev);
133 desc.pdata = sc->pdata;
134 desc.dev = dev;
135 desc.dev_type = CORESIGHT_CPU_DEBUG;
136 coresight_register(&desc);
137
138 return (0);
139 }
140
141 static device_method_t debug_methods[] = {
142 /* Device interface */
143 DEVMETHOD(device_probe, debug_probe),
144 DEVMETHOD(device_attach, debug_attach),
145
146 /* Coresight interface */
147 DEVMETHOD(coresight_init, debug_init),
148 DEVMETHOD_END
149 };
150
151 static driver_t debug_driver = {
152 "debug",
153 debug_methods,
154 sizeof(struct debug_softc),
155 };
156
157 EARLY_DRIVER_MODULE(debug, simplebus, debug_driver, 0, 0,
158 BUS_PASS_BUS + BUS_PASS_ORDER_LATE);
159 MODULE_VERSION(debug, 1);
160