1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate)
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 */
28 #include <sys/cdefs.h>
29 /*
30 * Driver for Armada 37x0 i2c controller.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/bus.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
42 #include <sys/rman.h>
43 #include <sys/sysctl.h>
44
45 #include <dev/iicbus/iicbus.h>
46 #include <dev/iicbus/iiconf.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <arm/mv/a37x0_iicreg.h>
51
52 #include "iicbus_if.h"
53
54 struct a37x0_iic_softc {
55 boolean_t sc_fast_mode;
56 bus_space_tag_t sc_bst;
57 bus_space_handle_t sc_bsh;
58 device_t sc_dev;
59 device_t sc_iicbus;
60 struct mtx sc_mtx;
61 struct resource *sc_mem_res;
62 struct resource *sc_irq_res;
63 void *sc_intrhand;
64 };
65
66 #define A37X0_IIC_WRITE(_sc, _off, _val) \
67 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
68 #define A37X0_IIC_READ(_sc, _off) \
69 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
70 #define A37X0_IIC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
71 #define A37X0_IIC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
72
73 static struct ofw_compat_data compat_data[] = {
74 { "marvell,armada-3700-i2c", 1 },
75 { NULL, 0 }
76 };
77
78 #undef A37x0_IIC_DEBUG
79
80 static void a37x0_iic_intr(void *);
81 static int a37x0_iic_detach(device_t);
82
83 static void
a37x0_iic_rmw(struct a37x0_iic_softc * sc,uint32_t off,uint32_t mask,uint32_t value)84 a37x0_iic_rmw(struct a37x0_iic_softc *sc, uint32_t off, uint32_t mask,
85 uint32_t value)
86 {
87 uint32_t reg;
88
89 mtx_assert(&sc->sc_mtx, MA_OWNED);
90 reg = A37X0_IIC_READ(sc, off);
91 reg &= ~mask;
92 reg |= value;
93 A37X0_IIC_WRITE(sc, off, reg);
94 }
95
96 static int
a37x0_iic_wait_clear(struct a37x0_iic_softc * sc,uint32_t mask)97 a37x0_iic_wait_clear(struct a37x0_iic_softc *sc, uint32_t mask)
98 {
99 int timeout;
100 uint32_t status;
101
102 mtx_assert(&sc->sc_mtx, MA_OWNED);
103 timeout = 1000;
104 do {
105 DELAY(10);
106 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
107 if (--timeout == 0)
108 return (0);
109 } while ((status & mask) != 0);
110
111 return (1);
112 }
113
114 static int
a37x0_iic_wait_set(struct a37x0_iic_softc * sc,uint32_t mask)115 a37x0_iic_wait_set(struct a37x0_iic_softc *sc, uint32_t mask)
116 {
117 int timeout;
118 uint32_t status;
119
120 mtx_assert(&sc->sc_mtx, MA_OWNED);
121 timeout = 1000;
122 do {
123 DELAY(10);
124 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
125 if (--timeout == 0)
126 return (0);
127 } while ((status & mask) != mask);
128
129 return (1);
130 }
131
132 #ifdef A37x0_IIC_DEBUG
133 static void
a37x0_iic_regdump(struct a37x0_iic_softc * sc)134 a37x0_iic_regdump(struct a37x0_iic_softc *sc)
135 {
136
137 mtx_assert(&sc->sc_mtx, MA_OWNED);
138 printf("%s: IBMR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_IBMR));
139 printf("%s: ICR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ICR));
140 printf("%s: ISR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ISR));
141 }
142 #endif
143
144 static void
a37x0_iic_reset(struct a37x0_iic_softc * sc)145 a37x0_iic_reset(struct a37x0_iic_softc *sc)
146 {
147 uint32_t mode, reg;
148
149 mtx_assert(&sc->sc_mtx, MA_OWNED);
150
151 /* Disable the controller. */
152 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
153 mode = reg & ICR_MODE_MASK;
154 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
155 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_UR);
156 DELAY(100);
157 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
158
159 /* Enable the controller. */
160 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
161 reg |= mode | ICR_IUE | ICR_GCD | ICR_SCLE;
162 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
163 #ifdef A37x0_IIC_DEBUG
164 a37x0_iic_regdump(sc);
165 #endif
166 }
167
168 static int
a37x0_iic_probe(device_t dev)169 a37x0_iic_probe(device_t dev)
170 {
171
172 if (!ofw_bus_status_okay(dev))
173 return (ENXIO);
174
175 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
176 return (ENXIO);
177
178 device_set_desc(dev, "Marvell Armada 37x0 IIC controller");
179
180 return (BUS_PROBE_DEFAULT);
181 }
182
183 static int
a37x0_iic_attach(device_t dev)184 a37x0_iic_attach(device_t dev)
185 {
186 int rid;
187 phandle_t node;
188 struct a37x0_iic_softc *sc;
189
190 sc = device_get_softc(dev);
191 sc->sc_dev = dev;
192
193 rid = 0;
194 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
195 RF_ACTIVE);
196 if (!sc->sc_mem_res) {
197 device_printf(dev, "cannot allocate memory window\n");
198 return (ENXIO);
199 }
200
201 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
202 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
203
204 rid = 0;
205 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
206 RF_ACTIVE | RF_SHAREABLE);
207 if (!sc->sc_irq_res) {
208 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
209 device_printf(dev, "cannot allocate interrupt\n");
210 return (ENXIO);
211 }
212
213 /* Hook up our interrupt handler. */
214 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
215 NULL, a37x0_iic_intr, sc, &sc->sc_intrhand)) {
216 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
217 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
218 device_printf(dev, "cannot setup the interrupt handler\n");
219 return (ENXIO);
220 }
221
222 mtx_init(&sc->sc_mtx, "a37x0_iic", NULL, MTX_DEF);
223
224 node = ofw_bus_get_node(dev);
225 if (OF_hasprop(node, "mrvl,i2c-fast-mode"))
226 sc->sc_fast_mode = true;
227
228 /* Enable the controller. */
229 A37X0_IIC_LOCK(sc);
230 a37x0_iic_reset(sc);
231 A37X0_IIC_UNLOCK(sc);
232
233 sc->sc_iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
234 if (sc->sc_iicbus == NULL) {
235 a37x0_iic_detach(dev);
236 return (ENXIO);
237 }
238
239 /* Probe and attach the iicbus. */
240 bus_attach_children(dev);
241 return (0);
242 }
243
244 static int
a37x0_iic_detach(device_t dev)245 a37x0_iic_detach(device_t dev)
246 {
247 struct a37x0_iic_softc *sc;
248
249 bus_generic_detach(dev);
250
251 sc = device_get_softc(dev);
252 mtx_destroy(&sc->sc_mtx);
253 if (sc->sc_intrhand)
254 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
255 if (sc->sc_irq_res)
256 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
257 if (sc->sc_mem_res)
258 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
259
260 return (0);
261 }
262
263 static void
a37x0_iic_intr(void * arg)264 a37x0_iic_intr(void *arg)
265 {
266 struct a37x0_iic_softc *sc;
267 uint32_t status;
268
269 /* Not used, the interrupts are not enabled. */
270 sc = (struct a37x0_iic_softc *)arg;
271 A37X0_IIC_LOCK(sc);
272 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
273 #ifdef A37x0_IIC_DEBUG
274 a37x0_iic_regdump(sc);
275 #endif
276
277 /* Clear pending interrrupts. */
278 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status);
279 A37X0_IIC_UNLOCK(sc);
280 }
281
282 static int
a37x0_iic_stop(device_t dev)283 a37x0_iic_stop(device_t dev)
284 {
285 struct a37x0_iic_softc *sc;
286 uint32_t reg;
287
288 sc = device_get_softc(dev);
289 A37X0_IIC_LOCK(sc);
290 /* Clear the STOP condition. */
291 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
292 if (reg & (ICR_ACKNAK | ICR_STOP)) {
293 reg &= ~(ICR_START | ICR_ACKNAK | ICR_STOP);
294 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
295 }
296 /* Clear interrupts. */
297 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
298 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, reg);
299 A37X0_IIC_UNLOCK(sc);
300
301 return (IIC_NOERR);
302 }
303
304 static int
a37x0_iic_start(device_t dev,u_char slave,int timeout)305 a37x0_iic_start(device_t dev, u_char slave, int timeout)
306 {
307 int rv;
308 struct a37x0_iic_softc *sc;
309 uint32_t reg, status;
310
311 sc = device_get_softc(dev);
312 A37X0_IIC_LOCK(sc);
313
314 /* Wait for the bus to be free before start a transaction. */
315 if (a37x0_iic_wait_clear(sc, ISR_IBB) == 0) {
316 A37X0_IIC_UNLOCK(sc);
317 return (IIC_ETIMEOUT);
318 }
319
320 /* Write the slave address. */
321 A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, slave);
322
323 /* Send Start condition (with slave address). */
324 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
325 reg &= ~(ICR_STOP | ICR_ACKNAK);
326 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_START | ICR_TB);
327
328 rv = IIC_NOERR;
329 if (a37x0_iic_wait_set(sc, ISR_ITE) == 0)
330 rv = IIC_ETIMEOUT;
331 if (rv == IIC_NOERR) {
332 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
333 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
334 if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0)
335 rv = IIC_ENOACK;
336 }
337
338 A37X0_IIC_UNLOCK(sc);
339 if (rv != IIC_NOERR)
340 a37x0_iic_stop(dev);
341
342 return (rv);
343 }
344
345 static int
a37x0_iic_bus_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)346 a37x0_iic_bus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
347 {
348 struct a37x0_iic_softc *sc;
349 uint32_t busfreq;
350
351 sc = device_get_softc(dev);
352 A37X0_IIC_LOCK(sc);
353 a37x0_iic_reset(sc);
354 if (sc->sc_iicbus == NULL)
355 busfreq = 100000;
356 else
357 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
358 a37x0_iic_rmw(sc, A37X0_IIC_ICR, ICR_MODE_MASK,
359 (busfreq > 100000) ? ICR_FAST_MODE : 0);
360 A37X0_IIC_UNLOCK(sc);
361
362 return (IIC_ENOADDR);
363 }
364
365 static int
a37x0_iic_read(device_t dev,char * buf,int len,int * read,int last,int delay)366 a37x0_iic_read(device_t dev, char *buf, int len, int *read, int last, int delay)
367 {
368 int rv;
369 struct a37x0_iic_softc *sc;
370 uint32_t reg, status;
371
372 sc = device_get_softc(dev);
373 A37X0_IIC_LOCK(sc);
374 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
375 if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
376 A37X0_IIC_UNLOCK(sc);
377 return (IIC_EBUSERR);
378 }
379
380 *read = 0;
381 rv = IIC_NOERR;
382 while (*read < len) {
383 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
384 reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
385 if (*read == len - 1)
386 reg |= ICR_ACKNAK | ICR_STOP;
387 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
388 if (a37x0_iic_wait_set(sc, ISR_IRF) == 0) {
389 rv = IIC_ETIMEOUT;
390 break;
391 }
392 *buf++ = A37X0_IIC_READ(sc, A37X0_IIC_IDBR);
393 (*read)++;
394 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
395 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_IRF);
396 }
397 A37X0_IIC_UNLOCK(sc);
398
399 return (rv);
400 }
401
402 static int
a37x0_iic_write(device_t dev,const char * buf,int len,int * sent,int timeout)403 a37x0_iic_write(device_t dev, const char *buf, int len, int *sent, int timeout)
404 {
405 int rv;
406 struct a37x0_iic_softc *sc;
407 uint32_t reg, status;
408
409 sc = device_get_softc(dev);
410 A37X0_IIC_LOCK(sc);
411 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
412 if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
413 A37X0_IIC_UNLOCK(sc);
414 return (IIC_EBUSERR);
415 }
416
417 rv = IIC_NOERR;
418 *sent = 0;
419 while (*sent < len) {
420 A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, *buf++);
421 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
422 reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
423 if (*sent == len - 1)
424 reg |= ICR_STOP;
425 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
426 if (a37x0_iic_wait_set(sc, ISR_ITE) == 0) {
427 rv = IIC_ETIMEOUT;
428 break;
429 }
430 (*sent)++;
431 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
432 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
433 if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0) {
434 rv = IIC_ENOACK;
435 break;
436 }
437 }
438 A37X0_IIC_UNLOCK(sc);
439
440 return (rv);
441 }
442
443 static phandle_t
a37x0_iic_get_node(device_t bus,device_t dev)444 a37x0_iic_get_node(device_t bus, device_t dev)
445 {
446
447 return (ofw_bus_get_node(bus));
448 }
449
450 static device_method_t a37x0_iic_methods[] = {
451 /* Device interface */
452 DEVMETHOD(device_probe, a37x0_iic_probe),
453 DEVMETHOD(device_attach, a37x0_iic_attach),
454 DEVMETHOD(device_detach, a37x0_iic_detach),
455
456 /* iicbus interface */
457 DEVMETHOD(iicbus_reset, a37x0_iic_bus_reset),
458 DEVMETHOD(iicbus_callback, iicbus_null_callback),
459 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
460 DEVMETHOD(iicbus_repeated_start, a37x0_iic_start),
461 DEVMETHOD(iicbus_start, a37x0_iic_start),
462 DEVMETHOD(iicbus_stop, a37x0_iic_stop),
463 DEVMETHOD(iicbus_read, a37x0_iic_read),
464 DEVMETHOD(iicbus_write, a37x0_iic_write),
465
466 /* ofw_bus interface */
467 DEVMETHOD(ofw_bus_get_node, a37x0_iic_get_node),
468
469 DEVMETHOD_END
470 };
471
472 static driver_t a37x0_iic_driver = {
473 "iichb",
474 a37x0_iic_methods,
475 sizeof(struct a37x0_iic_softc),
476 };
477
478 DRIVER_MODULE(iicbus, a37x0_iic, iicbus_driver, 0, 0);
479 DRIVER_MODULE(a37x0_iic, simplebus, a37x0_iic_driver, 0, 0);
480