1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
5 * Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/rman.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sysctl.h>
41
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <machine/intr.h>
45
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
48
49 #include <dev/spibus/spi.h>
50 #include <dev/spibus/spibusvar.h>
51
52 #include <arm/broadcom/bcm2835/bcm2835_spireg.h>
53 #include <arm/broadcom/bcm2835/bcm2835_spivar.h>
54
55 #include "spibus_if.h"
56
57 static struct ofw_compat_data compat_data[] = {
58 {"broadcom,bcm2835-spi", 1},
59 {"brcm,bcm2835-spi", 1},
60 {NULL, 0}
61 };
62
63 static void bcm_spi_intr(void *);
64
65 #ifdef BCM_SPI_DEBUG
66 static void
bcm_spi_printr(device_t dev)67 bcm_spi_printr(device_t dev)
68 {
69 struct bcm_spi_softc *sc;
70 uint32_t reg;
71
72 sc = device_get_softc(dev);
73 reg = BCM_SPI_READ(sc, SPI_CS);
74 device_printf(dev, "CS=%b\n", reg,
75 "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL"
76 "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN"
77 "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1"
78 "\30CSPOL2\31DMA_LEN\32LEN_LONG");
79 reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
80 if (reg % 2)
81 reg--;
82 if (reg == 0)
83 reg = 65536;
84 device_printf(dev, "CLK=%uMhz/%d=%luhz\n",
85 SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
86 reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;
87 device_printf(dev, "DLEN=%d\n", reg);
88 reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;
89 device_printf(dev, "LTOH=%d\n", reg);
90 reg = BCM_SPI_READ(sc, SPI_DC);
91 device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n",
92 (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,
93 (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,
94 (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,
95 (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);
96 }
97 #endif
98
99 static void
bcm_spi_modifyreg(struct bcm_spi_softc * sc,uint32_t off,uint32_t mask,uint32_t value)100 bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask,
101 uint32_t value)
102 {
103 uint32_t reg;
104
105 mtx_assert(&sc->sc_mtx, MA_OWNED);
106 reg = BCM_SPI_READ(sc, off);
107 reg &= ~mask;
108 reg |= value;
109 BCM_SPI_WRITE(sc, off, reg);
110 }
111
112 static int
bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)113 bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)
114 {
115 struct bcm_spi_softc *sc;
116 uint32_t clk;
117 int error;
118
119 sc = (struct bcm_spi_softc *)arg1;
120
121 BCM_SPI_LOCK(sc);
122 clk = BCM_SPI_READ(sc, SPI_CLK);
123 BCM_SPI_UNLOCK(sc);
124 clk &= 0xffff;
125 if (clk == 0)
126 clk = 65536;
127 clk = SPI_CORE_CLK / clk;
128
129 error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
130 if (error != 0 || req->newptr == NULL)
131 return (error);
132
133 return (0);
134 }
135
136 static int
bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS,uint32_t bit)137 bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit)
138 {
139 struct bcm_spi_softc *sc;
140 uint32_t reg;
141 int error;
142
143 sc = (struct bcm_spi_softc *)arg1;
144 BCM_SPI_LOCK(sc);
145 reg = BCM_SPI_READ(sc, SPI_CS);
146 BCM_SPI_UNLOCK(sc);
147 reg = (reg & bit) ? 1 : 0;
148
149 error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
150 if (error != 0 || req->newptr == NULL)
151 return (error);
152
153 return (0);
154 }
155
156 static int
bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)157 bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)
158 {
159
160 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL));
161 }
162
163 static int
bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)164 bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)
165 {
166
167 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA));
168 }
169
170 static int
bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)171 bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)
172 {
173
174 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0));
175 }
176
177 static int
bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)178 bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)
179 {
180
181 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1));
182 }
183
184 static int
bcm_spi_cspol2_proc(SYSCTL_HANDLER_ARGS)185 bcm_spi_cspol2_proc(SYSCTL_HANDLER_ARGS)
186 {
187
188 return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL2));
189 }
190
191 static void
bcm_spi_sysctl_init(struct bcm_spi_softc * sc)192 bcm_spi_sysctl_init(struct bcm_spi_softc *sc)
193 {
194 struct sysctl_ctx_list *ctx;
195 struct sysctl_oid *tree_node;
196 struct sysctl_oid_list *tree;
197
198 /*
199 * Add system sysctl tree/handlers.
200 */
201 ctx = device_get_sysctl_ctx(sc->sc_dev);
202 tree_node = device_get_sysctl_tree(sc->sc_dev);
203 tree = SYSCTL_CHILDREN(tree_node);
204 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
205 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
206 bcm_spi_clock_proc, "IU", "SPI BUS clock frequency");
207 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol",
208 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
209 bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity");
210 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha",
211 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
212 bcm_spi_cpha_proc, "IU", "SPI BUS clock phase");
213 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0",
214 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
215 bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity");
216 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1",
217 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
218 bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity");
219 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol2",
220 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, sc, sizeof(*sc),
221 bcm_spi_cspol2_proc, "IU", "SPI BUS chip select 2 polarity");
222 }
223
224 static int
bcm_spi_probe(device_t dev)225 bcm_spi_probe(device_t dev)
226 {
227
228 if (!ofw_bus_status_okay(dev))
229 return (ENXIO);
230
231 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
232 return (ENXIO);
233
234 device_set_desc(dev, "BCM2708/2835 SPI controller");
235
236 return (BUS_PROBE_DEFAULT);
237 }
238
239 static int
bcm_spi_attach(device_t dev)240 bcm_spi_attach(device_t dev)
241 {
242 struct bcm_spi_softc *sc;
243 int rid;
244
245 if (device_get_unit(dev) != 0) {
246 device_printf(dev, "only one SPI controller supported\n");
247 return (ENXIO);
248 }
249
250 sc = device_get_softc(dev);
251 sc->sc_dev = dev;
252
253 rid = 0;
254 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
255 RF_ACTIVE);
256 if (!sc->sc_mem_res) {
257 device_printf(dev, "cannot allocate memory window\n");
258 return (ENXIO);
259 }
260
261 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
262 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
263
264 rid = 0;
265 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
266 RF_ACTIVE);
267 if (!sc->sc_irq_res) {
268 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
269 device_printf(dev, "cannot allocate interrupt\n");
270 return (ENXIO);
271 }
272
273 /* Hook up our interrupt handler. */
274 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
275 NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) {
276 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
277 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
278 device_printf(dev, "cannot setup the interrupt handler\n");
279 return (ENXIO);
280 }
281
282 mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF);
283
284 /* Add sysctl nodes. */
285 bcm_spi_sysctl_init(sc);
286
287 #ifdef BCM_SPI_DEBUG
288 bcm_spi_printr(dev);
289 #endif
290
291 /*
292 * Enable the SPI controller. Clear the rx and tx FIFO.
293 * Defaults to SPI mode 0.
294 */
295 BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
296
297 #ifdef BCM_SPI_DEBUG
298 bcm_spi_printr(dev);
299 #endif
300
301 device_add_child(dev, "spibus", DEVICE_UNIT_ANY);
302 bus_attach_children(dev);
303
304 return (0);
305 }
306
307 static int
bcm_spi_detach(device_t dev)308 bcm_spi_detach(device_t dev)
309 {
310 struct bcm_spi_softc *sc;
311
312 bus_generic_detach(dev);
313
314 sc = device_get_softc(dev);
315 mtx_destroy(&sc->sc_mtx);
316 if (sc->sc_intrhand)
317 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
318 if (sc->sc_irq_res)
319 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
320 if (sc->sc_mem_res)
321 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
322
323 return (0);
324 }
325
326 static void
bcm_spi_fill_fifo(struct bcm_spi_softc * sc)327 bcm_spi_fill_fifo(struct bcm_spi_softc *sc)
328 {
329 struct spi_command *cmd;
330 uint32_t cs, written;
331 uint8_t *data;
332
333 cmd = sc->sc_cmd;
334 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
335 while (sc->sc_written < sc->sc_len &&
336 cs == (SPI_CS_TA | SPI_CS_TXD)) {
337 data = (uint8_t *)cmd->tx_cmd;
338 written = sc->sc_written++;
339 if (written >= cmd->tx_cmd_sz) {
340 data = (uint8_t *)cmd->tx_data;
341 written -= cmd->tx_cmd_sz;
342 }
343 BCM_SPI_WRITE(sc, SPI_FIFO, data[written]);
344 cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
345 }
346 }
347
348 static void
bcm_spi_drain_fifo(struct bcm_spi_softc * sc)349 bcm_spi_drain_fifo(struct bcm_spi_softc *sc)
350 {
351 struct spi_command *cmd;
352 uint32_t cs, read;
353 uint8_t *data;
354
355 cmd = sc->sc_cmd;
356 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
357 while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) {
358 data = (uint8_t *)cmd->rx_cmd;
359 read = sc->sc_read++;
360 if (read >= cmd->rx_cmd_sz) {
361 data = (uint8_t *)cmd->rx_data;
362 read -= cmd->rx_cmd_sz;
363 }
364 data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff;
365 cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
366 }
367 }
368
369 static void
bcm_spi_intr(void * arg)370 bcm_spi_intr(void *arg)
371 {
372 struct bcm_spi_softc *sc;
373
374 sc = (struct bcm_spi_softc *)arg;
375 BCM_SPI_LOCK(sc);
376
377 /* Filter stray interrupts. */
378 if ((sc->sc_flags & BCM_SPI_BUSY) == 0) {
379 BCM_SPI_UNLOCK(sc);
380 return;
381 }
382
383 /* TX - Fill up the FIFO. */
384 bcm_spi_fill_fifo(sc);
385
386 /* RX - Drain the FIFO. */
387 bcm_spi_drain_fifo(sc);
388
389 /* Check for end of transfer. */
390 if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
391 /* Disable interrupts and the SPI engine. */
392 if ((sc->sc_flags & BCM_SPI_KEEP_CS) == 0) {
393 bcm_spi_modifyreg(sc, SPI_CS,
394 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
395 }
396 wakeup(sc->sc_dev);
397 }
398
399 BCM_SPI_UNLOCK(sc);
400 }
401
402 static int
bcm_spi_transfer(device_t dev,device_t child,struct spi_command * cmd)403 bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
404 {
405 struct bcm_spi_softc *sc;
406 uint32_t cs, mode, clock;
407 int err;
408
409 sc = device_get_softc(dev);
410
411 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
412 ("TX/RX command sizes should be equal"));
413 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
414 ("TX/RX data sizes should be equal"));
415
416 /* Get the bus speed, mode, and chip select for this child. */
417
418 spibus_get_cs(child, &cs);
419 if ((cs & (~SPIBUS_CS_HIGH)) > 2) {
420 device_printf(dev,
421 "Invalid chip select %u requested by %s\n", cs,
422 device_get_nameunit(child));
423 return (EINVAL);
424 }
425
426 spibus_get_clock(child, &clock);
427 if (clock == 0) {
428 device_printf(dev,
429 "Invalid clock %uHz requested by %s\n", clock,
430 device_get_nameunit(child));
431 return (EINVAL);
432 }
433
434 spibus_get_mode(child, &mode);
435 if (mode > 3) {
436 device_printf(dev,
437 "Invalid mode %u requested by %s\n", mode,
438 device_get_nameunit(child));
439 return (EINVAL);
440 }
441
442 /* If the controller is in use wait until it is available. */
443 BCM_SPI_LOCK(sc);
444 if (sc->sc_thread != curthread)
445 while (sc->sc_flags & BCM_SPI_BUSY)
446 mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0);
447
448 /* Now we have control over SPI controller. */
449 sc->sc_flags = BCM_SPI_BUSY;
450
451 if ((cmd->flags & SPI_FLAG_KEEP_CS) != 0)
452 sc->sc_flags |= BCM_SPI_KEEP_CS;
453
454 /* Clear the FIFO. */
455 if (sc->sc_thread != curthread)
456 bcm_spi_modifyreg(sc, SPI_CS,
457 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO,
458 SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
459
460 sc->sc_thread = curthread;
461
462 /* Save a pointer to the SPI command. */
463 sc->sc_cmd = cmd;
464 sc->sc_read = 0;
465 sc->sc_written = 0;
466 sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
467
468 #ifdef BCM2835_SPI_USE_CS_HIGH /* TODO: for when behavior is correct */
469 /*
470 * Assign CS polarity first, while the CS indicates 'inactive'.
471 * This will need to set the correct polarity bit based on the 'cs', and
472 * the polarity bit will remain in this state, even after the transaction
473 * is complete.
474 */
475 if((cs & ~SPIBUS_CS_HIGH) == 0) {
476 bcm_spi_modifyreg(sc, SPI_CS,
477 SPI_CS_CSPOL0,
478 ((cs & (SPIBUS_CS_HIGH)) ? SPI_CS_CSPOL0 : 0));
479 }
480 else if((cs & ~SPIBUS_CS_HIGH) == 1) {
481 bcm_spi_modifyreg(sc, SPI_CS,
482 SPI_CS_CSPOL1,
483 ((cs & (SPIBUS_CS_HIGH)) ? SPI_CS_CSPOL1 : 0));
484 }
485 else if((cs & ~SPIBUS_CS_HIGH) == 2) {
486 bcm_spi_modifyreg(sc, SPI_CS,
487 SPI_CS_CSPOL2,
488 ((cs & (SPIBUS_CS_HIGH)) ? SPI_CS_CSPOL2 : 0));
489 }
490 #endif
491
492 /*
493 * Set the mode in 'SPI_CS' (clock phase and polarity bits).
494 * This must happen before CS output pin is active.
495 * Otherwise, you might glitch and drop the first bit.
496 */
497 bcm_spi_modifyreg(sc, SPI_CS,
498 SPI_CS_CPOL | SPI_CS_CPHA,
499 ((mode & SPIBUS_MODE_CPHA) ? SPI_CS_CPHA : 0) |
500 ((mode & SPIBUS_MODE_CPOL) ? SPI_CS_CPOL : 0));
501
502 /*
503 * Set the clock divider in 'SPI_CLK - see 'bcm_spi_clock_proc()'.
504 */
505
506 /* calculate 'clock' as a divider value from freq */
507 clock = SPI_CORE_CLK / clock;
508 if (clock <= 1)
509 clock = 2;
510 else if (clock % 2)
511 clock--;
512 if (clock > 0xffff)
513 clock = 0;
514
515 BCM_SPI_WRITE(sc, SPI_CLK, clock);
516
517 /*
518 * Set the CS for this transaction, enable interrupts and announce
519 * we're ready to tx. This will kick off the first interrupt.
520 */
521 bcm_spi_modifyreg(sc, SPI_CS,
522 SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD,
523 (cs & (~SPIBUS_CS_HIGH)) | /* cs is the lower 2 bits of the reg */
524 SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD);
525
526 /* Wait for the transaction to complete. */
527 err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2);
528
529 /* Make sure the SPI engine and interrupts are disabled. */
530 if (!(cmd->flags & SPI_FLAG_KEEP_CS)) {
531 bcm_spi_modifyreg(sc,
532 SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
533 sc->sc_thread = 0;
534 }
535
536 wakeup_one(dev);
537 sc->sc_flags &= ~BCM_SPI_BUSY;
538 /* Release the controller and wakeup the next thread waiting for it. */
539 BCM_SPI_UNLOCK(sc);
540
541 /*
542 * Check for transfer timeout. The SPI controller doesn't
543 * return errors.
544 */
545 if (err == EWOULDBLOCK) {
546 device_printf(sc->sc_dev, "SPI error (timeout)\n");
547 err = EIO;
548 }
549
550 return (err);
551 }
552
553 static phandle_t
bcm_spi_get_node(device_t bus,device_t dev)554 bcm_spi_get_node(device_t bus, device_t dev)
555 {
556
557 /* We only have one child, the SPI bus, which needs our own node. */
558 return (ofw_bus_get_node(bus));
559 }
560
561 static device_method_t bcm_spi_methods[] = {
562 /* Device interface */
563 DEVMETHOD(device_probe, bcm_spi_probe),
564 DEVMETHOD(device_attach, bcm_spi_attach),
565 DEVMETHOD(device_detach, bcm_spi_detach),
566
567 /* SPI interface */
568 DEVMETHOD(spibus_transfer, bcm_spi_transfer),
569
570 /* ofw_bus interface */
571 DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node),
572
573 DEVMETHOD_END
574 };
575
576 static driver_t bcm_spi_driver = {
577 "spi",
578 bcm_spi_methods,
579 sizeof(struct bcm_spi_softc),
580 };
581
582 DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, 0, 0);
583