1/* 2 * Copyright (C) 2015 Mihai Carabas <mihai.carabas@gmail.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include "assym.inc" 28#include <sys/syscall.h> 29#include <machine/asm.h> 30#include <machine/asmacros.h> 31#include <machine/armreg.h> 32#include <machine/sysreg.h> 33#if defined(__ARM_ARCH_7VE__) || defined(__clang__) 34.arch_extension virt 35#endif 36 37ASENTRY_NP(hypervisor_stub_vect_install) 38 39 /* Install hypervisor stub vectors. */ 40 adr r0, hypervisor_stub_vect 41 mcr CP15_HVBAR(r0) 42 43 /* Disable all the traps in the hypervisor. */ 44 mov r0, #0 45 mcr CP15_HCR(r0) 46 mcr CP15_HCPTR(r0) 47 mcr CP15_HSTR(r0) 48 mcr CP15_HSCTLR(r0) 49 50 /* Don't disable access to perf-mon from PL0,1 and preserve HPMN. */ 51 mrc CP15_HDCR(r0) 52 and r0, #(ARM_CP15_HDCR_HPMN) 53 /* Caller implicit instruction barrier in the ERET. */ 54 mcr CP15_HDCR(r0) 55 56 RET 57 58END(hypervisor_stub_vect_install) 59 60ASENTRY_NP(hypervisor_stub_trap) 61 /* 62 * If the first parameter is -1 than return the 63 * exception vector (HVBAR), otherwise set it to 64 * the value of it. 65 */ 66 cmp r0, #-1 67 mrceq CP15_HVBAR(r0) 68 mcrne CP15_HVBAR(r0) 69 ERET 70END(hypervisor_stub_trap) 71 72 .globl hypervisor_stub_vect 73 .align 5 74_C_LABEL(hypervisor_stub_vect): 75 .word 0 /* Reset */ 76 .word 0 /* undev */ 77 .word 0 /* SMC */ 78 .word 0 /* PABT */ 79 .word 0 /* DABT */ 80 b hypervisor_stub_trap /* HYP-Mode */ 81 .word 0 /* FIQ */ 82 .word 0 /* IRQ */ 83 84