1 /*-
2 * Copyright (c) 2015,2016 Annapurna Labs Ltd. and affiliates
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Alpine PCI/PCI-Express controller driver.
31 */
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/bus.h>
38 #include <sys/rman.h>
39 #include <sys/intr.h>
40
41 #include <dev/ofw/openfirm.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
44 #include <dev/pci/pci_host_generic.h>
45 #include <dev/pci/pci_host_generic_fdt.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48
49 #include "pcib_if.h"
50
51 #include "contrib/alpine-hal/al_hal_unit_adapter_regs.h"
52 #include "contrib/alpine-hal/al_hal_pcie.h"
53 #include "contrib/alpine-hal/al_hal_pcie_axi_reg.h"
54
55 #define ANNAPURNA_VENDOR_ID 0x1c36
56
57 /* Forward prototypes */
58 static int al_pcib_probe(device_t);
59 static int al_pcib_attach(device_t);
60 static void al_pcib_fixup(device_t);
61
62 static struct ofw_compat_data compat_data[] = {
63 {"annapurna-labs,al-internal-pcie", true},
64 {"annapurna-labs,alpine-internal-pcie", true},
65 {NULL, false}
66 };
67
68 /*
69 * Bus interface definitions.
70 */
71 static device_method_t al_pcib_methods[] = {
72 /* Device interface */
73 DEVMETHOD(device_probe, al_pcib_probe),
74 DEVMETHOD(device_attach, al_pcib_attach),
75
76 DEVMETHOD_END
77 };
78
79 DEFINE_CLASS_1(pcib, al_pcib_driver, al_pcib_methods,
80 sizeof(struct generic_pcie_fdt_softc), generic_pcie_fdt_driver);
81
82 DRIVER_MODULE(alpine_pcib, simplebus, al_pcib_driver, 0, 0);
83 DRIVER_MODULE(alpine_pcib, ofwbus, al_pcib_driver, 0, 0);
84
85 static int
al_pcib_probe(device_t dev)86 al_pcib_probe(device_t dev)
87 {
88
89 if (!ofw_bus_status_okay(dev))
90 return (ENXIO);
91
92 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
93 return (ENXIO);
94
95 device_set_desc(dev,
96 "Annapurna-Labs Integrated Internal PCI-E Controller");
97 return (BUS_PROBE_DEFAULT);
98 }
99
100 static int
al_pcib_attach(device_t dev)101 al_pcib_attach(device_t dev)
102 {
103 int rv;
104
105 rv = pci_host_generic_fdt_attach(dev);
106
107 /* Annapurna quirk: configure vendor-specific registers */
108 if (rv == 0)
109 al_pcib_fixup(dev);
110
111 return (rv);
112 }
113
114 static void
al_pcib_fixup(device_t dev)115 al_pcib_fixup(device_t dev)
116 {
117 uint32_t val;
118 uint16_t vid;
119 uint8_t hdrtype;
120 int bus, slot, func, maxfunc;
121
122 /* Fixup is only needed on bus 0 */
123 bus = 0;
124 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
125 maxfunc = 0;
126 for (func = 0; func <= maxfunc; func++) {
127 hdrtype = PCIB_READ_CONFIG(dev, bus, slot, func,
128 PCIR_HDRTYPE, 1);
129
130 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
131 continue;
132
133 if (func == 0 && (hdrtype & PCIM_MFDEV) != 0)
134 maxfunc = PCI_FUNCMAX;
135
136 vid = PCIB_READ_CONFIG(dev, bus, slot, func,
137 PCIR_VENDOR, 2);
138 if (vid == ANNAPURNA_VENDOR_ID) {
139 val = PCIB_READ_CONFIG(dev, bus, slot, func,
140 AL_PCI_AXI_CFG_AND_CTR_0, 4);
141 val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_2_PF_VEC_PH_VEC_OVRD_FROM_AXUSER_MASK;
142 PCIB_WRITE_CONFIG(dev, bus, slot, func,
143 AL_PCI_AXI_CFG_AND_CTR_0, val, 4);
144
145 val = PCIB_READ_CONFIG(dev, bus, slot, func,
146 AL_PCI_APP_CONTROL, 4);
147 val &= ~0xffff;
148 val |= PCIE_AXI_PF_AXI_ATTR_OVRD_FUNC_CTRL_4_PF_VEC_MEM_ADDR54_63_SEL_TGTID_MASK;
149 PCIB_WRITE_CONFIG(dev, bus, slot, func,
150 AL_PCI_APP_CONTROL, val, 4);
151 }
152 }
153 }
154 }
155