1 /*-
2 * Copyright (c) 2019 Emmanuel Vadot <manu@FreeBSD.Org>
3 * Copyright (c) 2016 Vladimir Belian <fate10@gmail.com>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/param.h>
29 #include <sys/bus.h>
30 #include <sys/time.h>
31 #include <sys/rman.h>
32 #include <sys/clock.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/module.h>
36 #include <sys/resource.h>
37
38 #include <machine/bus.h>
39 #include <machine/resource.h>
40
41 #include <dev/ofw/ofw_bus.h>
42 #include <dev/ofw/ofw_bus_subr.h>
43
44 #include <dev/clk/clk_fixed.h>
45
46 #include <arm/allwinner/aw_machdep.h>
47
48 #include "clock_if.h"
49
50 #define LOSC_CTRL_REG 0x00
51 #define A10_RTC_DATE_REG 0x04
52 #define A10_RTC_TIME_REG 0x08
53 #define A31_LOSC_AUTO_SWT_STA 0x04
54 #define A31_RTC_DATE_REG 0x10
55 #define A31_RTC_TIME_REG 0x14
56
57 #define TIME_MASK 0x001f3f3f
58
59 #define LOSC_OSC_SRC (1 << 0)
60 #define LOSC_GSM (1 << 3)
61 #define LOSC_AUTO_SW_EN (1 << 14)
62 #define LOSC_MAGIC 0x16aa0000
63 #define LOSC_BUSY_MASK 0x00000380
64
65 #define IS_SUN7I (sc->conf->is_a20 == true)
66
67 #define YEAR_MIN (IS_SUN7I ? 1970 : 2010)
68 #define YEAR_MAX (IS_SUN7I ? 2100 : 2073)
69 #define YEAR_OFFSET (IS_SUN7I ? 1900 : 2010)
70 #define YEAR_MASK (IS_SUN7I ? 0xff : 0x3f)
71 #define LEAP_BIT (IS_SUN7I ? 24 : 22)
72
73 #define GET_SEC_VALUE(x) ((x) & 0x0000003f)
74 #define GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
75 #define GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
76 #define GET_DAY_VALUE(x) ((x) & 0x0000001f)
77 #define GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
78 #define GET_YEAR_VALUE(x) (((x) >> 16) & YEAR_MASK)
79
80 #define SET_DAY_VALUE(x) GET_DAY_VALUE(x)
81 #define SET_MON_VALUE(x) (((x) & 0x0000000f) << 8)
82 #define SET_YEAR_VALUE(x) (((x) & YEAR_MASK) << 16)
83 #define SET_LEAP_VALUE(x) (((x) & 0x00000001) << LEAP_BIT)
84 #define SET_SEC_VALUE(x) GET_SEC_VALUE(x)
85 #define SET_MIN_VALUE(x) (((x) & 0x0000003f) << 8)
86 #define SET_HOUR_VALUE(x) (((x) & 0x0000001f) << 16)
87
88 #define HALF_OF_SEC_NS 500000000
89 #define RTC_RES_US 1000000
90 #define RTC_TIMEOUT 70
91
92 #define RTC_READ(sc, reg) bus_read_4((sc)->res, (reg))
93 #define RTC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
94
95 #define IS_LEAP_YEAR(y) (((y) % 400) == 0 || (((y) % 100) != 0 && ((y) % 4) == 0))
96
97 struct aw_rtc_conf {
98 uint64_t iosc_freq;
99 bus_size_t rtc_date;
100 bus_size_t rtc_time;
101 bus_size_t rtc_losc_sta;
102 bool is_a20;
103 };
104
105 struct aw_rtc_conf a10_conf = {
106 .rtc_date = A10_RTC_DATE_REG,
107 .rtc_time = A10_RTC_TIME_REG,
108 .rtc_losc_sta = LOSC_CTRL_REG,
109 };
110
111 struct aw_rtc_conf a20_conf = {
112 .rtc_date = A10_RTC_DATE_REG,
113 .rtc_time = A10_RTC_TIME_REG,
114 .rtc_losc_sta = LOSC_CTRL_REG,
115 .is_a20 = true,
116 };
117
118 struct aw_rtc_conf a31_conf = {
119 .iosc_freq = 650000, /* between 600 and 700 Khz */
120 .rtc_date = A31_RTC_DATE_REG,
121 .rtc_time = A31_RTC_TIME_REG,
122 .rtc_losc_sta = A31_LOSC_AUTO_SWT_STA,
123 };
124
125 struct aw_rtc_conf h3_conf = {
126 .iosc_freq = 16000000,
127 .rtc_date = A31_RTC_DATE_REG,
128 .rtc_time = A31_RTC_TIME_REG,
129 .rtc_losc_sta = A31_LOSC_AUTO_SWT_STA,
130 };
131
132 static struct ofw_compat_data compat_data[] = {
133 { "allwinner,sun4i-a10-rtc", (uintptr_t) &a10_conf },
134 { "allwinner,sun7i-a20-rtc", (uintptr_t) &a20_conf },
135 { "allwinner,sun6i-a31-rtc", (uintptr_t) &a31_conf },
136 { "allwinner,sun8i-h3-rtc", (uintptr_t) &h3_conf },
137 { "allwinner,sun20i-d1-rtc", (uintptr_t) &h3_conf },
138 { "allwinner,sun50i-h5-rtc", (uintptr_t) &h3_conf },
139 { "allwinner,sun50i-h6-rtc", (uintptr_t) &h3_conf },
140 { NULL, 0 }
141 };
142
143 struct aw_rtc_softc {
144 struct resource *res;
145 struct aw_rtc_conf *conf;
146 int type;
147 };
148
149 static struct clk_fixed_def aw_rtc_osc32k = {
150 .clkdef.id = 0,
151 .clkdef.name = "osc32k",
152 .freq = 32768,
153 };
154
155 static struct clk_fixed_def aw_rtc_iosc = {
156 .clkdef.id = 2,
157 .clkdef.name = "iosc",
158 };
159
160 static void aw_rtc_install_clocks(struct aw_rtc_softc *sc, device_t dev);
161
162 static int aw_rtc_probe(device_t dev);
163 static int aw_rtc_attach(device_t dev);
164 static int aw_rtc_detach(device_t dev);
165
166 static int aw_rtc_gettime(device_t dev, struct timespec *ts);
167 static int aw_rtc_settime(device_t dev, struct timespec *ts);
168
169 static device_method_t aw_rtc_methods[] = {
170 DEVMETHOD(device_probe, aw_rtc_probe),
171 DEVMETHOD(device_attach, aw_rtc_attach),
172 DEVMETHOD(device_detach, aw_rtc_detach),
173
174 DEVMETHOD(clock_gettime, aw_rtc_gettime),
175 DEVMETHOD(clock_settime, aw_rtc_settime),
176
177 DEVMETHOD_END
178 };
179
180 static driver_t aw_rtc_driver = {
181 "rtc",
182 aw_rtc_methods,
183 sizeof(struct aw_rtc_softc),
184 };
185
186 EARLY_DRIVER_MODULE(aw_rtc, simplebus, aw_rtc_driver, 0, 0,
187 BUS_PASS_RESOURCE + BUS_PASS_ORDER_FIRST);
188 MODULE_VERSION(aw_rtc, 1);
189 SIMPLEBUS_PNP_INFO(compat_data);
190
191 static int
aw_rtc_probe(device_t dev)192 aw_rtc_probe(device_t dev)
193 {
194 if (!ofw_bus_status_okay(dev))
195 return (ENXIO);
196
197 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
198 return (ENXIO);
199
200 device_set_desc(dev, "Allwinner RTC");
201
202 return (BUS_PROBE_DEFAULT);
203 }
204
205 static int
aw_rtc_attach(device_t dev)206 aw_rtc_attach(device_t dev)
207 {
208 struct aw_rtc_softc *sc = device_get_softc(dev);
209 uint32_t val;
210 int rid = 0;
211
212 sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
213 if (!sc->res) {
214 device_printf(dev, "could not allocate resources\n");
215 return (ENXIO);
216 }
217
218 sc->conf = (struct aw_rtc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
219 val = RTC_READ(sc, LOSC_CTRL_REG);
220 val |= LOSC_AUTO_SW_EN;
221 val |= LOSC_MAGIC | LOSC_GSM | LOSC_OSC_SRC;
222 RTC_WRITE(sc, LOSC_CTRL_REG, val);
223
224 DELAY(100);
225
226 if (bootverbose) {
227 val = RTC_READ(sc, sc->conf->rtc_losc_sta);
228 if ((val & LOSC_OSC_SRC) == 0)
229 device_printf(dev, "Using internal oscillator\n");
230 else
231 device_printf(dev, "Using external oscillator\n");
232 }
233
234 aw_rtc_install_clocks(sc, dev);
235
236 clock_register(dev, RTC_RES_US);
237
238 return (0);
239 }
240
241 static int
aw_rtc_detach(device_t dev)242 aw_rtc_detach(device_t dev)
243 {
244 /* can't support detach, since there's no clock_unregister function */
245 return (EBUSY);
246 }
247
248 static void
aw_rtc_install_clocks(struct aw_rtc_softc * sc,device_t dev)249 aw_rtc_install_clocks(struct aw_rtc_softc *sc, device_t dev) {
250 struct clkdom *clkdom;
251 const char **clknames;
252 phandle_t node;
253 int nclocks;
254
255 /*
256 * If the device tree gives us specific output names for the clocks,
257 * use them.
258 */
259 node = ofw_bus_get_node(dev);
260 nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", &clknames);
261 if (nclocks > 0) {
262 if (nclocks != 3) {
263 device_printf(dev,
264 "Found %d clocks instead of 3, aborting\n",
265 nclocks);
266 return;
267 }
268
269 aw_rtc_osc32k.clkdef.name = clknames[0];
270 aw_rtc_iosc.clkdef.name = clknames[2];
271 }
272
273 clkdom = clkdom_create(dev);
274
275 if (clknode_fixed_register(clkdom, &aw_rtc_osc32k) != 0)
276 device_printf(dev, "Cannot register osc32k clock\n");
277
278 aw_rtc_iosc.freq = sc->conf->iosc_freq;
279 if (clknode_fixed_register(clkdom, &aw_rtc_iosc) != 0)
280 device_printf(dev, "Cannot register iosc clock\n");
281
282 clkdom_finit(clkdom);
283
284 if (bootverbose)
285 clkdom_dump(clkdom);
286 }
287
288 static int
aw_rtc_gettime(device_t dev,struct timespec * ts)289 aw_rtc_gettime(device_t dev, struct timespec *ts)
290 {
291 struct aw_rtc_softc *sc = device_get_softc(dev);
292 struct clocktime ct;
293 uint32_t rdate, rtime;
294
295 rdate = RTC_READ(sc, sc->conf->rtc_date);
296 rtime = RTC_READ(sc, sc->conf->rtc_time);
297
298 if ((rtime & TIME_MASK) == 0)
299 rdate = RTC_READ(sc, sc->conf->rtc_date);
300
301 ct.sec = GET_SEC_VALUE(rtime);
302 ct.min = GET_MIN_VALUE(rtime);
303 ct.hour = GET_HOUR_VALUE(rtime);
304 ct.day = GET_DAY_VALUE(rdate);
305 ct.mon = GET_MON_VALUE(rdate);
306 ct.year = GET_YEAR_VALUE(rdate) + YEAR_OFFSET;
307 ct.dow = -1;
308 /* RTC resolution is 1 sec */
309 ct.nsec = 0;
310
311 return (clock_ct_to_ts(&ct, ts));
312 }
313
314 static int
aw_rtc_settime(device_t dev,struct timespec * ts)315 aw_rtc_settime(device_t dev, struct timespec *ts)
316 {
317 struct aw_rtc_softc *sc = device_get_softc(dev);
318 struct clocktime ct;
319 uint32_t clk, rdate, rtime;
320
321 /* RTC resolution is 1 sec */
322 if (ts->tv_nsec >= HALF_OF_SEC_NS)
323 ts->tv_sec++;
324 ts->tv_nsec = 0;
325
326 clock_ts_to_ct(ts, &ct);
327
328 if ((ct.year < YEAR_MIN) || (ct.year > YEAR_MAX)) {
329 device_printf(dev, "could not set time, year out of range\n");
330 return (EINVAL);
331 }
332
333 for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) {
334 if (clk > RTC_TIMEOUT) {
335 device_printf(dev, "could not set time, RTC busy\n");
336 return (EINVAL);
337 }
338 DELAY(1);
339 }
340 /* reset time register to avoid unexpected date increment */
341 RTC_WRITE(sc, sc->conf->rtc_time, 0);
342
343 rdate = SET_DAY_VALUE(ct.day) | SET_MON_VALUE(ct.mon) |
344 SET_YEAR_VALUE(ct.year - YEAR_OFFSET) |
345 SET_LEAP_VALUE(IS_LEAP_YEAR(ct.year));
346
347 rtime = SET_SEC_VALUE(ct.sec) | SET_MIN_VALUE(ct.min) |
348 SET_HOUR_VALUE(ct.hour);
349
350 for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) {
351 if (clk > RTC_TIMEOUT) {
352 device_printf(dev, "could not set date, RTC busy\n");
353 return (EINVAL);
354 }
355 DELAY(1);
356 }
357 RTC_WRITE(sc, sc->conf->rtc_date, rdate);
358
359 for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) {
360 if (clk > RTC_TIMEOUT) {
361 device_printf(dev, "could not set time, RTC busy\n");
362 return (EINVAL);
363 }
364 DELAY(1);
365 }
366 RTC_WRITE(sc, sc->conf->rtc_time, rtime);
367
368 DELAY(RTC_TIMEOUT);
369
370 return (0);
371 }
372