xref: /freebsd/sys/contrib/device-tree/src/arm/ti/omap/am33xx-clocks.dtsi (revision f126890ac5386406dadf7c4cfa9566cbb56537c5)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM33xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&scm_clocks {
8	sys_clkin_ck: clock-sys-clkin-22@40 {
9		#clock-cells = <0>;
10		compatible = "ti,mux-clock";
11		clock-output-names = "sys_clkin_ck";
12		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
13		ti,bit-shift = <22>;
14		reg = <0x0040>;
15	};
16
17	adc_tsc_fck: clock-adc-tsc-fck {
18		#clock-cells = <0>;
19		compatible = "fixed-factor-clock";
20		clock-output-names = "adc_tsc_fck";
21		clocks = <&sys_clkin_ck>;
22		clock-mult = <1>;
23		clock-div = <1>;
24	};
25
26	dcan0_fck: clock-dcan0-fck {
27		#clock-cells = <0>;
28		compatible = "fixed-factor-clock";
29		clock-output-names = "dcan0_fck";
30		clocks = <&sys_clkin_ck>;
31		clock-mult = <1>;
32		clock-div = <1>;
33	};
34
35	dcan1_fck: clock-dcan1-fck {
36		#clock-cells = <0>;
37		compatible = "fixed-factor-clock";
38		clock-output-names = "dcan1_fck";
39		clocks = <&sys_clkin_ck>;
40		clock-mult = <1>;
41		clock-div = <1>;
42	};
43
44	mcasp0_fck: clock-mcasp0-fck {
45		#clock-cells = <0>;
46		compatible = "fixed-factor-clock";
47		clock-output-names = "mcasp0_fck";
48		clocks = <&sys_clkin_ck>;
49		clock-mult = <1>;
50		clock-div = <1>;
51	};
52
53	mcasp1_fck: clock-mcasp1-fck {
54		#clock-cells = <0>;
55		compatible = "fixed-factor-clock";
56		clock-output-names = "mcasp1_fck";
57		clocks = <&sys_clkin_ck>;
58		clock-mult = <1>;
59		clock-div = <1>;
60	};
61
62	smartreflex0_fck: clock-smartreflex0-fck {
63		#clock-cells = <0>;
64		compatible = "fixed-factor-clock";
65		clock-output-names = "smartreflex0_fck";
66		clocks = <&sys_clkin_ck>;
67		clock-mult = <1>;
68		clock-div = <1>;
69	};
70
71	smartreflex1_fck: clock-smartreflex1-fck {
72		#clock-cells = <0>;
73		compatible = "fixed-factor-clock";
74		clock-output-names = "smartreflex1_fck";
75		clocks = <&sys_clkin_ck>;
76		clock-mult = <1>;
77		clock-div = <1>;
78	};
79
80	sha0_fck: clock-sha0-fck {
81		#clock-cells = <0>;
82		compatible = "fixed-factor-clock";
83		clock-output-names = "sha0_fck";
84		clocks = <&sys_clkin_ck>;
85		clock-mult = <1>;
86		clock-div = <1>;
87	};
88
89	aes0_fck: clock-aes0-fck {
90		#clock-cells = <0>;
91		compatible = "fixed-factor-clock";
92		clock-output-names = "aes0_fck";
93		clocks = <&sys_clkin_ck>;
94		clock-mult = <1>;
95		clock-div = <1>;
96	};
97
98	rng_fck: clock-rng-fck {
99		#clock-cells = <0>;
100		compatible = "fixed-factor-clock";
101		clock-output-names = "rng_fck";
102		clocks = <&sys_clkin_ck>;
103		clock-mult = <1>;
104		clock-div = <1>;
105	};
106
107	clock@664 {
108		compatible = "ti,clksel";
109		reg = <0x664>;
110		#clock-cells = <2>;
111		#address-cells = <0>;
112
113		ehrpwm0_tbclk: clock-ehrpwm0-tbclk {
114			#clock-cells = <0>;
115			compatible = "ti,gate-clock";
116			clock-output-names = "ehrpwm0_tbclk";
117			clocks = <&l4ls_gclk>;
118			ti,bit-shift = <0>;
119		};
120
121		ehrpwm1_tbclk: clock-ehrpwm1-tbclk {
122			#clock-cells = <0>;
123			compatible = "ti,gate-clock";
124			clock-output-names = "ehrpwm1_tbclk";
125			clocks = <&l4ls_gclk>;
126			ti,bit-shift = <1>;
127		};
128
129		ehrpwm2_tbclk: clock-ehrpwm2-tbclk {
130			#clock-cells = <0>;
131			compatible = "ti,gate-clock";
132			clock-output-names = "ehrpwm2_tbclk";
133			clocks = <&l4ls_gclk>;
134			ti,bit-shift = <2>;
135		};
136	};
137};
138&prcm_clocks {
139	clk_32768_ck: clock-clk-32768 {
140		#clock-cells = <0>;
141		compatible = "fixed-clock";
142		clock-output-names = "clk_32768_ck";
143		clock-frequency = <32768>;
144	};
145
146	clk_rc32k_ck: clock-clk-rc32k {
147		#clock-cells = <0>;
148		compatible = "fixed-clock";
149		clock-output-names = "clk_rc32k_ck";
150		clock-frequency = <32000>;
151	};
152
153	virt_19200000_ck: clock-virt-19200000 {
154		#clock-cells = <0>;
155		compatible = "fixed-clock";
156		clock-output-names = "virt_19200000_ck";
157		clock-frequency = <19200000>;
158	};
159
160	virt_24000000_ck: clock-virt-24000000 {
161		#clock-cells = <0>;
162		compatible = "fixed-clock";
163		clock-output-names = "virt_24000000_ck";
164		clock-frequency = <24000000>;
165	};
166
167	virt_25000000_ck: clock-virt-25000000 {
168		#clock-cells = <0>;
169		compatible = "fixed-clock";
170		clock-output-names = "virt_25000000_ck";
171		clock-frequency = <25000000>;
172	};
173
174	virt_26000000_ck: clock-virt-26000000 {
175		#clock-cells = <0>;
176		compatible = "fixed-clock";
177		clock-output-names = "virt_26000000_ck";
178		clock-frequency = <26000000>;
179	};
180
181	tclkin_ck: clock-tclkin {
182		#clock-cells = <0>;
183		compatible = "fixed-clock";
184		clock-output-names = "tclkin_ck";
185		clock-frequency = <12000000>;
186	};
187
188	dpll_core_ck: clock@490 {
189		#clock-cells = <0>;
190		compatible = "ti,am3-dpll-core-clock";
191		clock-output-names = "dpll_core_ck";
192		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
193		reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
194	};
195
196	dpll_core_x2_ck: clock-dpll-core-x2 {
197		#clock-cells = <0>;
198		compatible = "ti,am3-dpll-x2-clock";
199		clock-output-names = "dpll_core_x2_ck";
200		clocks = <&dpll_core_ck>;
201	};
202
203	dpll_core_m4_ck: clock-dpll-core-m4@480 {
204		#clock-cells = <0>;
205		compatible = "ti,divider-clock";
206		clock-output-names = "dpll_core_m4_ck";
207		clocks = <&dpll_core_x2_ck>;
208		ti,max-div = <31>;
209		reg = <0x0480>;
210		ti,index-starts-at-one;
211	};
212
213	dpll_core_m5_ck: clock-dpll-core-m5@484 {
214		#clock-cells = <0>;
215		compatible = "ti,divider-clock";
216		clock-output-names = "dpll_core_m5_ck";
217		clocks = <&dpll_core_x2_ck>;
218		ti,max-div = <31>;
219		reg = <0x0484>;
220		ti,index-starts-at-one;
221	};
222
223	dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
224		#clock-cells = <0>;
225		compatible = "ti,divider-clock";
226		clock-output-names = "dpll_core_m6_ck";
227		clocks = <&dpll_core_x2_ck>;
228		ti,max-div = <31>;
229		reg = <0x04d8>;
230		ti,index-starts-at-one;
231	};
232
233	dpll_mpu_ck: clock@488 {
234		#clock-cells = <0>;
235		compatible = "ti,am3-dpll-clock";
236		clock-output-names = "dpll_mpu_ck";
237		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
238		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
239	};
240
241	dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
242		#clock-cells = <0>;
243		compatible = "ti,divider-clock";
244		clock-output-names = "dpll_mpu_m2_ck";
245		clocks = <&dpll_mpu_ck>;
246		ti,max-div = <31>;
247		reg = <0x04a8>;
248		ti,index-starts-at-one;
249	};
250
251	dpll_ddr_ck: clock@494 {
252		#clock-cells = <0>;
253		compatible = "ti,am3-dpll-no-gate-clock";
254		clock-output-names = "dpll_ddr_ck";
255		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
256		reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
257	};
258
259	dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
260		#clock-cells = <0>;
261		compatible = "ti,divider-clock";
262		clock-output-names = "dpll_ddr_m2_ck";
263		clocks = <&dpll_ddr_ck>;
264		ti,max-div = <31>;
265		reg = <0x04a0>;
266		ti,index-starts-at-one;
267	};
268
269	dpll_ddr_m2_div2_ck: clock-dpll-ddr-m2-div2 {
270		#clock-cells = <0>;
271		compatible = "fixed-factor-clock";
272		clock-output-names = "dpll_ddr_m2_div2_ck";
273		clocks = <&dpll_ddr_m2_ck>;
274		clock-mult = <1>;
275		clock-div = <2>;
276	};
277
278	dpll_disp_ck: clock@498 {
279		#clock-cells = <0>;
280		compatible = "ti,am3-dpll-no-gate-clock";
281		clock-output-names = "dpll_disp_ck";
282		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
283		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
284	};
285
286	dpll_disp_m2_ck: clock-dpll-disp-m2@4a4 {
287		#clock-cells = <0>;
288		compatible = "ti,divider-clock";
289		clock-output-names = "dpll_disp_m2_ck";
290		clocks = <&dpll_disp_ck>;
291		ti,max-div = <31>;
292		reg = <0x04a4>;
293		ti,index-starts-at-one;
294		ti,set-rate-parent;
295	};
296
297	dpll_per_ck: clock@48c {
298		#clock-cells = <0>;
299		compatible = "ti,am3-dpll-no-gate-j-type-clock";
300		clock-output-names = "dpll_per_ck";
301		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
302		reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
303	};
304
305	dpll_per_m2_ck: clock-dpll-per-m2@4ac {
306		#clock-cells = <0>;
307		compatible = "ti,divider-clock";
308		clock-output-names = "dpll_per_m2_ck";
309		clocks = <&dpll_per_ck>;
310		ti,max-div = <31>;
311		reg = <0x04ac>;
312		ti,index-starts-at-one;
313	};
314
315	dpll_per_m2_div4_wkupdm_ck: clock-dpll-per-m2-div4-wkupdm {
316		#clock-cells = <0>;
317		compatible = "fixed-factor-clock";
318		clock-output-names = "dpll_per_m2_div4_wkupdm_ck";
319		clocks = <&dpll_per_m2_ck>;
320		clock-mult = <1>;
321		clock-div = <4>;
322	};
323
324	dpll_per_m2_div4_ck: clock-dpll-per-m2-div4 {
325		#clock-cells = <0>;
326		compatible = "fixed-factor-clock";
327		clock-output-names = "dpll_per_m2_div4_ck";
328		clocks = <&dpll_per_m2_ck>;
329		clock-mult = <1>;
330		clock-div = <4>;
331	};
332
333	clk_24mhz: clock-clk-24mhz {
334		#clock-cells = <0>;
335		compatible = "fixed-factor-clock";
336		clock-output-names = "clk_24mhz";
337		clocks = <&dpll_per_m2_ck>;
338		clock-mult = <1>;
339		clock-div = <8>;
340	};
341
342	clkdiv32k_ck: clock-clkdiv32k {
343		#clock-cells = <0>;
344		compatible = "fixed-factor-clock";
345		clock-output-names = "clkdiv32k_ck";
346		clocks = <&clk_24mhz>;
347		clock-mult = <1>;
348		clock-div = <732>;
349	};
350
351	l3_gclk: clock-l3-gclk {
352		#clock-cells = <0>;
353		compatible = "fixed-factor-clock";
354		clock-output-names = "l3_gclk";
355		clocks = <&dpll_core_m4_ck>;
356		clock-mult = <1>;
357		clock-div = <1>;
358	};
359
360	pruss_ocp_gclk: clock-pruss-ocp-gclk@530 {
361		#clock-cells = <0>;
362		compatible = "ti,mux-clock";
363		clock-output-names = "pruss_ocp_gclk";
364		clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
365		reg = <0x0530>;
366	};
367
368	mmu_fck: clock-mmu-fck-1@914 {
369		#clock-cells = <0>;
370		compatible = "ti,gate-clock";
371		clock-output-names = "mmu_fck";
372		clocks = <&dpll_core_m4_ck>;
373		ti,bit-shift = <1>;
374		reg = <0x0914>;
375	};
376
377	timer1_fck: clock-timer1-fck@528 {
378		#clock-cells = <0>;
379		compatible = "ti,mux-clock";
380		clock-output-names = "timer1_fck";
381		clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
382		reg = <0x0528>;
383	};
384
385	timer2_fck: clock-timer2-fck@508 {
386		#clock-cells = <0>;
387		compatible = "ti,mux-clock";
388		clock-output-names = "timer2_fck";
389		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
390		reg = <0x0508>;
391	};
392
393	timer3_fck: clock-timer3-fck@50c {
394		#clock-cells = <0>;
395		compatible = "ti,mux-clock";
396		clock-output-names = "timer3_fck";
397		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
398		reg = <0x050c>;
399	};
400
401	timer4_fck: clock-timer4-fck@510 {
402		#clock-cells = <0>;
403		compatible = "ti,mux-clock";
404		clock-output-names = "timer4_fck";
405		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
406		reg = <0x0510>;
407	};
408
409	timer5_fck: clock-timer5-fck@518 {
410		#clock-cells = <0>;
411		compatible = "ti,mux-clock";
412		clock-output-names = "timer5_fck";
413		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
414		reg = <0x0518>;
415	};
416
417	timer6_fck: clock-timer6-fck@51c {
418		#clock-cells = <0>;
419		compatible = "ti,mux-clock";
420		clock-output-names = "timer6_fck";
421		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
422		reg = <0x051c>;
423	};
424
425	timer7_fck: clock-timer7-fck@504 {
426		#clock-cells = <0>;
427		compatible = "ti,mux-clock";
428		clock-output-names = "timer7_fck";
429		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
430		reg = <0x0504>;
431	};
432
433	usbotg_fck: clock-usbotg-fck-8@47c {
434		#clock-cells = <0>;
435		compatible = "ti,gate-clock";
436		clock-output-names = "usbotg_fck";
437		clocks = <&dpll_per_ck>;
438		ti,bit-shift = <8>;
439		reg = <0x047c>;
440	};
441
442	dpll_core_m4_div2_ck: clock-dpll-core-m4-div2 {
443		#clock-cells = <0>;
444		compatible = "fixed-factor-clock";
445		clock-output-names = "dpll_core_m4_div2_ck";
446		clocks = <&dpll_core_m4_ck>;
447		clock-mult = <1>;
448		clock-div = <2>;
449	};
450
451	ieee5000_fck: clock-ieee5000-fck-1@e4 {
452		#clock-cells = <0>;
453		compatible = "ti,gate-clock";
454		clock-output-names = "ieee5000_fck";
455		clocks = <&dpll_core_m4_div2_ck>;
456		ti,bit-shift = <1>;
457		reg = <0x00e4>;
458	};
459
460	wdt1_fck: clock-wdt1-fck@538 {
461		#clock-cells = <0>;
462		compatible = "ti,mux-clock";
463		clock-output-names = "wdt1_fck";
464		clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
465		reg = <0x0538>;
466	};
467
468	l4_rtc_gclk: clock-l4-rtc-gclk {
469		#clock-cells = <0>;
470		compatible = "fixed-factor-clock";
471		clock-output-names = "l4_rtc_gclk";
472		clocks = <&dpll_core_m4_ck>;
473		clock-mult = <1>;
474		clock-div = <2>;
475	};
476
477	l4hs_gclk: clock-l4hs-gclk {
478		#clock-cells = <0>;
479		compatible = "fixed-factor-clock";
480		clock-output-names = "l4hs_gclk";
481		clocks = <&dpll_core_m4_ck>;
482		clock-mult = <1>;
483		clock-div = <1>;
484	};
485
486	l3s_gclk: clock-l3s-gclk {
487		#clock-cells = <0>;
488		compatible = "fixed-factor-clock";
489		clock-output-names = "l3s_gclk";
490		clocks = <&dpll_core_m4_div2_ck>;
491		clock-mult = <1>;
492		clock-div = <1>;
493	};
494
495	l4fw_gclk: clock-l4fw-gclk {
496		#clock-cells = <0>;
497		compatible = "fixed-factor-clock";
498		clock-output-names = "l4fw_gclk";
499		clocks = <&dpll_core_m4_div2_ck>;
500		clock-mult = <1>;
501		clock-div = <1>;
502	};
503
504	l4ls_gclk: clock-l4ls-gclk {
505		#clock-cells = <0>;
506		compatible = "fixed-factor-clock";
507		clock-output-names = "l4ls_gclk";
508		clocks = <&dpll_core_m4_div2_ck>;
509		clock-mult = <1>;
510		clock-div = <1>;
511	};
512
513	sysclk_div_ck: clock-sysclk-div {
514		#clock-cells = <0>;
515		compatible = "fixed-factor-clock";
516		clock-output-names = "sysclk_div_ck";
517		clocks = <&dpll_core_m4_ck>;
518		clock-mult = <1>;
519		clock-div = <1>;
520	};
521
522	cpsw_125mhz_gclk: clock-cpsw-125mhz-gclk {
523		#clock-cells = <0>;
524		compatible = "fixed-factor-clock";
525		clock-output-names = "cpsw_125mhz_gclk";
526		clocks = <&dpll_core_m5_ck>;
527		clock-mult = <1>;
528		clock-div = <2>;
529	};
530
531	cpsw_cpts_rft_clk: clock-cpsw-cpts-rft@520 {
532		#clock-cells = <0>;
533		compatible = "ti,mux-clock";
534		clock-output-names = "cpsw_cpts_rft_clk";
535		clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
536		reg = <0x0520>;
537	};
538
539	gpio0_dbclk_mux_ck: clock-gpio0-dbclk-mux@53c {
540		#clock-cells = <0>;
541		compatible = "ti,mux-clock";
542		clock-output-names = "gpio0_dbclk_mux_ck";
543		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
544		reg = <0x053c>;
545	};
546
547	lcd_gclk: clock-lcd-gclk@534 {
548		#clock-cells = <0>;
549		compatible = "ti,mux-clock";
550		clock-output-names = "lcd_gclk";
551		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
552		reg = <0x0534>;
553		ti,set-rate-parent;
554	};
555
556	mmc_clk: clock-mmc {
557		#clock-cells = <0>;
558		compatible = "fixed-factor-clock";
559		clock-output-names = "mmc_clk";
560		clocks = <&dpll_per_m2_ck>;
561		clock-mult = <1>;
562		clock-div = <2>;
563	};
564
565	clock@52c {
566		compatible = "ti,clksel";
567		reg = <0x52c>;
568		#clock-cells = <2>;
569		#address-cells = <0>;
570
571		gfx_fclk_clksel_ck: clock-gfx-fclk-clksel {
572			#clock-cells = <0>;
573			compatible = "ti,mux-clock";
574			clock-output-names = "gfx_fclk_clksel_ck";
575			clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
576			ti,bit-shift = <1>;
577		};
578
579		gfx_fck_div_ck: clock-gfx-fck-div {
580			#clock-cells = <0>;
581			compatible = "ti,divider-clock";
582			clock-output-names = "gfx_fck_div_ck";
583			clocks = <&gfx_fclk_clksel_ck>;
584			ti,max-div = <2>;
585		};
586	};
587
588	clock@700 {
589		compatible = "ti,clksel";
590		reg = <0x700>;
591		#clock-cells = <2>;
592		#address-cells = <0>;
593
594		sysclkout_pre_ck: clock-sysclkout-pre {
595			#clock-cells = <0>;
596			compatible = "ti,mux-clock";
597			clock-output-names = "sysclkout_pre_ck";
598			clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
599		};
600
601		clkout2_div_ck: clock-clkout2-div {
602			#clock-cells = <0>;
603			compatible = "ti,divider-clock";
604			clock-output-names = "clkout2_div_ck";
605			clocks = <&sysclkout_pre_ck>;
606			ti,bit-shift = <3>;
607			ti,max-div = <8>;
608		};
609
610		clkout2_ck: clock-clkout2 {
611			#clock-cells = <0>;
612			compatible = "ti,gate-clock";
613			clock-output-names = "clkout2_ck";
614			clocks = <&clkout2_div_ck>;
615			ti,bit-shift = <7>;
616		};
617	};
618};
619
620&prcm {
621	per_cm: clock@0 {
622		compatible = "ti,omap4-cm";
623		clock-output-names = "per_cm";
624		reg = <0x0 0x400>;
625		#address-cells = <1>;
626		#size-cells = <1>;
627		ranges = <0 0x0 0x400>;
628
629		l4ls_clkctrl: clock@38 {
630			compatible = "ti,clkctrl";
631			clock-output-names = "l4ls_clkctrl";
632			reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
633			#clock-cells = <2>;
634		};
635
636		l3s_clkctrl: clock@1c {
637			compatible = "ti,clkctrl";
638			clock-output-names = "l3s_clkctrl";
639			reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
640			#clock-cells = <2>;
641		};
642
643		l3_clkctrl: clock@24 {
644			compatible = "ti,clkctrl";
645			clock-output-names = "l3_clkctrl";
646			reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
647			#clock-cells = <2>;
648		};
649
650		l4hs_clkctrl: clock@120 {
651			compatible = "ti,clkctrl";
652			clock-output-names = "l4hs_clkctrl";
653			reg = <0x120 0x4>;
654			#clock-cells = <2>;
655		};
656
657		pruss_ocp_clkctrl: clock@e8 {
658			compatible = "ti,clkctrl";
659			clock-output-names = "pruss_ocp_clkctrl";
660			reg = <0xe8 0x4>;
661			#clock-cells = <2>;
662		};
663
664		cpsw_125mhz_clkctrl: clock@0 {
665			compatible = "ti,clkctrl";
666			clock-output-names = "cpsw_125mhz_clkctrl";
667			reg = <0x0 0x18>;
668			#clock-cells = <2>;
669		};
670
671		lcdc_clkctrl: clock@18 {
672			compatible = "ti,clkctrl";
673			clock-output-names = "lcdc_clkctrl";
674			reg = <0x18 0x4>;
675			#clock-cells = <2>;
676		};
677
678		clk_24mhz_clkctrl: clock@14c {
679			compatible = "ti,clkctrl";
680			clock-output-names = "clk_24mhz_clkctrl";
681			reg = <0x14c 0x4>;
682			#clock-cells = <2>;
683		};
684	};
685
686	wkup_cm: clock@400 {
687		compatible = "ti,omap4-cm";
688		clock-output-names = "wkup_cm";
689		reg = <0x400 0x100>;
690		#address-cells = <1>;
691		#size-cells = <1>;
692		ranges = <0 0x400 0x100>;
693
694		l4_wkup_clkctrl: clock@0 {
695			compatible = "ti,clkctrl";
696			clock-output-names = "l4_wkup_clkctrl";
697			reg = <0x0 0x10>, <0xb4 0x24>;
698			#clock-cells = <2>;
699		};
700
701		l3_aon_clkctrl: clock@14 {
702			compatible = "ti,clkctrl";
703			clock-output-names = "l3_aon_clkctrl";
704			reg = <0x14 0x4>;
705			#clock-cells = <2>;
706		};
707
708		l4_wkup_aon_clkctrl: clock@b0 {
709			compatible = "ti,clkctrl";
710			clock-output-names = "l4_wkup_aon_clkctrl";
711			reg = <0xb0 0x4>;
712			#clock-cells = <2>;
713		};
714	};
715
716	mpu_cm: clock@600 {
717		compatible = "ti,omap4-cm";
718		clock-output-names = "mpu_cm";
719		reg = <0x600 0x100>;
720		#address-cells = <1>;
721		#size-cells = <1>;
722		ranges = <0 0x600 0x100>;
723
724		mpu_clkctrl: clock@0 {
725			compatible = "ti,clkctrl";
726			clock-output-names = "mpu_clkctrl";
727			reg = <0x0 0x8>;
728			#clock-cells = <2>;
729		};
730	};
731
732	l4_rtc_cm: clock@800 {
733		compatible = "ti,omap4-cm";
734		clock-output-names = "l4_rtc_cm";
735		reg = <0x800 0x100>;
736		#address-cells = <1>;
737		#size-cells = <1>;
738		ranges = <0 0x800 0x100>;
739
740		l4_rtc_clkctrl: clock@0 {
741			compatible = "ti,clkctrl";
742			clock-output-names = "l4_rtc_clkctrl";
743			reg = <0x0 0x4>;
744			#clock-cells = <2>;
745		};
746	};
747
748	gfx_l3_cm: clock@900 {
749		compatible = "ti,omap4-cm";
750		clock-output-names = "gfx_l3_cm";
751		reg = <0x900 0x100>;
752		#address-cells = <1>;
753		#size-cells = <1>;
754		ranges = <0 0x900 0x100>;
755
756		gfx_l3_clkctrl: clock@0 {
757			compatible = "ti,clkctrl";
758			clock-output-names = "gfx_l3_clkctrl";
759			reg = <0x0 0x8>;
760			#clock-cells = <2>;
761		};
762	};
763
764	l4_cefuse_cm: clock@a00 {
765		compatible = "ti,omap4-cm";
766		clock-output-names = "l4_cefuse_cm";
767		reg = <0xa00 0x100>;
768		#address-cells = <1>;
769		#size-cells = <1>;
770		ranges = <0 0xa00 0x100>;
771
772		l4_cefuse_clkctrl: clock@0 {
773			compatible = "ti,clkctrl";
774			clock-output-names = "l4_cefuse_clkctrl";
775			reg = <0x0 0x24>;
776			#clock-cells = <2>;
777		};
778	};
779};
780