1 //===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file is part of the XCore Disassembler.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #include "TargetInfo/XCoreTargetInfo.h"
15 #include "XCore.h"
16 #include "XCoreRegisterInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDecoderOps.h"
19 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/MC/TargetRegistry.h"
23 #include "llvm/Support/Compiler.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "xcore-disassembler"
28
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
30
31 namespace {
32
33 /// A disassembler class for XCore.
34 class XCoreDisassembler : public MCDisassembler {
35 public:
XCoreDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)36 XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
37 MCDisassembler(STI, Ctx) {}
38
39 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
40 ArrayRef<uint8_t> Bytes, uint64_t Address,
41 raw_ostream &CStream) const override;
42 };
43 }
44
readInstruction16(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint16_t & Insn)45 static bool readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
46 uint64_t &Size, uint16_t &Insn) {
47 // We want to read exactly 2 Bytes of data.
48 if (Bytes.size() < 2) {
49 Size = 0;
50 return false;
51 }
52 // Encoded as a little-endian 16-bit word in the stream.
53 Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
54 return true;
55 }
56
readInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn)57 static bool readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
58 uint64_t &Size, uint32_t &Insn) {
59 // We want to read exactly 4 Bytes of data.
60 if (Bytes.size() < 4) {
61 Size = 0;
62 return false;
63 }
64 // Encoded as a little-endian 32-bit word in the stream.
65 Insn =
66 (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
67 return true;
68 }
69
getReg(const MCDisassembler * D,unsigned RC,unsigned RegNo)70 static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo) {
71 const MCRegisterInfo *RegInfo = D->getContext().getRegisterInfo();
72 return *(RegInfo->getRegClass(RC).begin() + RegNo);
73 }
74
75 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
76 uint64_t Address,
77 const MCDisassembler *Decoder);
78
79 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
80 uint64_t Address,
81 const MCDisassembler *Decoder);
82
83 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
84 uint64_t Address,
85 const MCDisassembler *Decoder);
86
87 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
88 uint64_t Address,
89 const MCDisassembler *Decoder);
90
91 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
92 uint64_t Address,
93 const MCDisassembler *Decoder);
94
95 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
96 uint64_t Address,
97 const MCDisassembler *Decoder);
98
99 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
100 uint64_t Address,
101 const MCDisassembler *Decoder);
102
103 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
104 uint64_t Address,
105 const MCDisassembler *Decoder);
106
107 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
108 uint64_t Address,
109 const MCDisassembler *Decoder);
110
111 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
112 uint64_t Address,
113 const MCDisassembler *Decoder);
114
115 static DecodeStatus
116 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
117 const MCDisassembler *Decoder);
118
119 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
120 uint64_t Address,
121 const MCDisassembler *Decoder);
122
123 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
124 uint64_t Address,
125 const MCDisassembler *Decoder);
126
127 static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
128 uint64_t Address,
129 const MCDisassembler *Decoder);
130
131 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
132 uint64_t Address,
133 const MCDisassembler *Decoder);
134
135 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
136 uint64_t Address,
137 const MCDisassembler *Decoder);
138
139 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
140 uint64_t Address,
141 const MCDisassembler *Decoder);
142
143 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
144 uint64_t Address,
145 const MCDisassembler *Decoder);
146
147 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
148 uint64_t Address,
149 const MCDisassembler *Decoder);
150
151 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
152 uint64_t Address,
153 const MCDisassembler *Decoder);
154
155 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
156 uint64_t Address,
157 const MCDisassembler *Decoder);
158
159 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
160 uint64_t Address,
161 const MCDisassembler *Decoder);
162
163 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
164 uint64_t Address,
165 const MCDisassembler *Decoder);
166
167 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
168 uint64_t Address,
169 const MCDisassembler *Decoder);
170
171 static DecodeStatus
172 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
173 const MCDisassembler *Decoder);
174
175 #include "XCoreGenDisassemblerTables.inc"
176
DecodeGRRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder)177 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
178 uint64_t Address,
179 const MCDisassembler *Decoder) {
180 if (RegNo > 11)
181 return MCDisassembler::Fail;
182 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
183 Inst.addOperand(MCOperand::createReg(Reg));
184 return MCDisassembler::Success;
185 }
186
DecodeRRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder)187 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
188 uint64_t Address,
189 const MCDisassembler *Decoder) {
190 if (RegNo > 15)
191 return MCDisassembler::Fail;
192 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
193 Inst.addOperand(MCOperand::createReg(Reg));
194 return MCDisassembler::Success;
195 }
196
DecodeBitpOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder)197 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
198 uint64_t Address,
199 const MCDisassembler *Decoder) {
200 if (Val > 11)
201 return MCDisassembler::Fail;
202 static const unsigned Values[] = {
203 32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
204 };
205 Inst.addOperand(MCOperand::createImm(Values[Val]));
206 return MCDisassembler::Success;
207 }
208
DecodeNegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder)209 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
210 uint64_t Address,
211 const MCDisassembler *Decoder) {
212 Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
213 return MCDisassembler::Success;
214 }
215
216 static DecodeStatus
Decode2OpInstruction(unsigned Insn,unsigned & Op1,unsigned & Op2)217 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
218 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
219 if (Combined < 27)
220 return MCDisassembler::Fail;
221 if (fieldFromInstruction(Insn, 5, 1)) {
222 if (Combined == 31)
223 return MCDisassembler::Fail;
224 Combined += 5;
225 }
226 Combined -= 27;
227 unsigned Op1High = Combined % 3;
228 unsigned Op2High = Combined / 3;
229 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
230 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
231 return MCDisassembler::Success;
232 }
233
234 static DecodeStatus
Decode3OpInstruction(unsigned Insn,unsigned & Op1,unsigned & Op2,unsigned & Op3)235 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
236 unsigned &Op3) {
237 unsigned Combined = fieldFromInstruction(Insn, 6, 5);
238 if (Combined >= 27)
239 return MCDisassembler::Fail;
240
241 unsigned Op1High = Combined % 3;
242 unsigned Op2High = (Combined / 3) % 3;
243 unsigned Op3High = Combined / 9;
244 Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
245 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
246 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
247 return MCDisassembler::Success;
248 }
249
Decode2OpInstructionFail(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)250 static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn,
251 uint64_t Address,
252 const MCDisassembler *Decoder) {
253 // Try and decode as a 3R instruction.
254 unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
255 switch (Opcode) {
256 case 0x0:
257 Inst.setOpcode(XCore::STW_2rus);
258 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
259 case 0x1:
260 Inst.setOpcode(XCore::LDW_2rus);
261 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
262 case 0x2:
263 Inst.setOpcode(XCore::ADD_3r);
264 return Decode3RInstruction(Inst, Insn, Address, Decoder);
265 case 0x3:
266 Inst.setOpcode(XCore::SUB_3r);
267 return Decode3RInstruction(Inst, Insn, Address, Decoder);
268 case 0x4:
269 Inst.setOpcode(XCore::SHL_3r);
270 return Decode3RInstruction(Inst, Insn, Address, Decoder);
271 case 0x5:
272 Inst.setOpcode(XCore::SHR_3r);
273 return Decode3RInstruction(Inst, Insn, Address, Decoder);
274 case 0x6:
275 Inst.setOpcode(XCore::EQ_3r);
276 return Decode3RInstruction(Inst, Insn, Address, Decoder);
277 case 0x7:
278 Inst.setOpcode(XCore::AND_3r);
279 return Decode3RInstruction(Inst, Insn, Address, Decoder);
280 case 0x8:
281 Inst.setOpcode(XCore::OR_3r);
282 return Decode3RInstruction(Inst, Insn, Address, Decoder);
283 case 0x9:
284 Inst.setOpcode(XCore::LDW_3r);
285 return Decode3RInstruction(Inst, Insn, Address, Decoder);
286 case 0x10:
287 Inst.setOpcode(XCore::LD16S_3r);
288 return Decode3RInstruction(Inst, Insn, Address, Decoder);
289 case 0x11:
290 Inst.setOpcode(XCore::LD8U_3r);
291 return Decode3RInstruction(Inst, Insn, Address, Decoder);
292 case 0x12:
293 Inst.setOpcode(XCore::ADD_2rus);
294 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
295 case 0x13:
296 Inst.setOpcode(XCore::SUB_2rus);
297 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
298 case 0x14:
299 Inst.setOpcode(XCore::SHL_2rus);
300 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
301 case 0x15:
302 Inst.setOpcode(XCore::SHR_2rus);
303 return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
304 case 0x16:
305 Inst.setOpcode(XCore::EQ_2rus);
306 return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
307 case 0x17:
308 Inst.setOpcode(XCore::TSETR_3r);
309 return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
310 case 0x18:
311 Inst.setOpcode(XCore::LSS_3r);
312 return Decode3RInstruction(Inst, Insn, Address, Decoder);
313 case 0x19:
314 Inst.setOpcode(XCore::LSU_3r);
315 return Decode3RInstruction(Inst, Insn, Address, Decoder);
316 }
317 return MCDisassembler::Fail;
318 }
319
Decode2RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)320 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn,
321 uint64_t Address,
322 const MCDisassembler *Decoder) {
323 unsigned Op1, Op2;
324 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
325 if (S != MCDisassembler::Success)
326 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
327
328 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
329 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
330 return S;
331 }
332
Decode2RImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)333 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn,
334 uint64_t Address,
335 const MCDisassembler *Decoder) {
336 unsigned Op1, Op2;
337 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
338 if (S != MCDisassembler::Success)
339 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
340
341 Inst.addOperand(MCOperand::createImm(Op1));
342 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
343 return S;
344 }
345
DecodeR2RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)346 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn,
347 uint64_t Address,
348 const MCDisassembler *Decoder) {
349 unsigned Op1, Op2;
350 DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
351 if (S != MCDisassembler::Success)
352 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
353
354 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
355 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
356 return S;
357 }
358
Decode2RSrcDstInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)359 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn,
360 uint64_t Address,
361 const MCDisassembler *Decoder) {
362 unsigned Op1, Op2;
363 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
364 if (S != MCDisassembler::Success)
365 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
366
367 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
368 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
369 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
370 return S;
371 }
372
DecodeRUSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)373 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn,
374 uint64_t Address,
375 const MCDisassembler *Decoder) {
376 unsigned Op1, Op2;
377 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
378 if (S != MCDisassembler::Success)
379 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
380
381 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
382 Inst.addOperand(MCOperand::createImm(Op2));
383 return S;
384 }
385
DecodeRUSBitpInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)386 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn,
387 uint64_t Address,
388 const MCDisassembler *Decoder) {
389 unsigned Op1, Op2;
390 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
391 if (S != MCDisassembler::Success)
392 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
393
394 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
395 DecodeBitpOperand(Inst, Op2, Address, Decoder);
396 return S;
397 }
398
399 static DecodeStatus
DecodeRUSSrcDstBitpInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)400 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
401 const MCDisassembler *Decoder) {
402 unsigned Op1, Op2;
403 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
404 if (S != MCDisassembler::Success)
405 return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
406
407 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
408 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
409 DecodeBitpOperand(Inst, Op2, Address, Decoder);
410 return S;
411 }
412
DecodeL2OpInstructionFail(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)413 static DecodeStatus DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn,
414 uint64_t Address,
415 const MCDisassembler *Decoder) {
416 // Try and decode as a L3R / L2RUS instruction.
417 unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
418 fieldFromInstruction(Insn, 27, 5) << 4;
419 switch (Opcode) {
420 case 0x0c:
421 Inst.setOpcode(XCore::STW_l3r);
422 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
423 case 0x1c:
424 Inst.setOpcode(XCore::XOR_l3r);
425 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
426 case 0x2c:
427 Inst.setOpcode(XCore::ASHR_l3r);
428 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
429 case 0x3c:
430 Inst.setOpcode(XCore::LDAWF_l3r);
431 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
432 case 0x4c:
433 Inst.setOpcode(XCore::LDAWB_l3r);
434 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
435 case 0x5c:
436 Inst.setOpcode(XCore::LDA16F_l3r);
437 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
438 case 0x6c:
439 Inst.setOpcode(XCore::LDA16B_l3r);
440 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
441 case 0x7c:
442 Inst.setOpcode(XCore::MUL_l3r);
443 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
444 case 0x8c:
445 Inst.setOpcode(XCore::DIVS_l3r);
446 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
447 case 0x9c:
448 Inst.setOpcode(XCore::DIVU_l3r);
449 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
450 case 0x10c:
451 Inst.setOpcode(XCore::ST16_l3r);
452 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
453 case 0x11c:
454 Inst.setOpcode(XCore::ST8_l3r);
455 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
456 case 0x12c:
457 Inst.setOpcode(XCore::ASHR_l2rus);
458 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
459 case 0x12d:
460 Inst.setOpcode(XCore::OUTPW_l2rus);
461 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
462 case 0x12e:
463 Inst.setOpcode(XCore::INPW_l2rus);
464 return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
465 case 0x13c:
466 Inst.setOpcode(XCore::LDAWF_l2rus);
467 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
468 case 0x14c:
469 Inst.setOpcode(XCore::LDAWB_l2rus);
470 return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
471 case 0x15c:
472 Inst.setOpcode(XCore::CRC_l3r);
473 return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
474 case 0x18c:
475 Inst.setOpcode(XCore::REMS_l3r);
476 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
477 case 0x19c:
478 Inst.setOpcode(XCore::REMU_l3r);
479 return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
480 }
481 return MCDisassembler::Fail;
482 }
483
DecodeL2RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)484 static DecodeStatus DecodeL2RInstruction(MCInst &Inst, unsigned Insn,
485 uint64_t Address,
486 const MCDisassembler *Decoder) {
487 unsigned Op1, Op2;
488 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
489 Op1, Op2);
490 if (S != MCDisassembler::Success)
491 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
492
493 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
494 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
495 return S;
496 }
497
DecodeLR2RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)498 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst, unsigned Insn,
499 uint64_t Address,
500 const MCDisassembler *Decoder) {
501 unsigned Op1, Op2;
502 DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
503 Op1, Op2);
504 if (S != MCDisassembler::Success)
505 return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
506
507 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
508 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
509 return S;
510 }
511
Decode3RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)512 static DecodeStatus Decode3RInstruction(MCInst &Inst, unsigned Insn,
513 uint64_t Address,
514 const MCDisassembler *Decoder) {
515 unsigned Op1, Op2, Op3;
516 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
517 if (S == MCDisassembler::Success) {
518 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
519 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
520 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
521 }
522 return S;
523 }
524
Decode3RImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)525 static DecodeStatus Decode3RImmInstruction(MCInst &Inst, unsigned Insn,
526 uint64_t Address,
527 const MCDisassembler *Decoder) {
528 unsigned Op1, Op2, Op3;
529 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
530 if (S == MCDisassembler::Success) {
531 Inst.addOperand(MCOperand::createImm(Op1));
532 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
533 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
534 }
535 return S;
536 }
537
Decode2RUSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)538 static DecodeStatus Decode2RUSInstruction(MCInst &Inst, unsigned Insn,
539 uint64_t Address,
540 const MCDisassembler *Decoder) {
541 unsigned Op1, Op2, Op3;
542 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
543 if (S == MCDisassembler::Success) {
544 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
545 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
546 Inst.addOperand(MCOperand::createImm(Op3));
547 }
548 return S;
549 }
550
Decode2RUSBitpInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)551 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
552 uint64_t Address,
553 const MCDisassembler *Decoder) {
554 unsigned Op1, Op2, Op3;
555 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
556 if (S == MCDisassembler::Success) {
557 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
558 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
559 DecodeBitpOperand(Inst, Op3, Address, Decoder);
560 }
561 return S;
562 }
563
DecodeL3RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)564 static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
565 uint64_t Address,
566 const MCDisassembler *Decoder) {
567 unsigned Op1, Op2, Op3;
568 DecodeStatus S =
569 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
570 if (S == MCDisassembler::Success) {
571 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
572 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
573 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
574 }
575 return S;
576 }
577
DecodeL3RSrcDstInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)578 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
579 uint64_t Address,
580 const MCDisassembler *Decoder) {
581 unsigned Op1, Op2, Op3;
582 DecodeStatus S =
583 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
584 if (S == MCDisassembler::Success) {
585 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
586 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
587 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
588 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
589 }
590 return S;
591 }
592
DecodeL2RUSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)593 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
594 uint64_t Address,
595 const MCDisassembler *Decoder) {
596 unsigned Op1, Op2, Op3;
597 DecodeStatus S =
598 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
599 if (S == MCDisassembler::Success) {
600 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
601 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
602 Inst.addOperand(MCOperand::createImm(Op3));
603 }
604 return S;
605 }
606
DecodeL2RUSBitpInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)607 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
608 uint64_t Address,
609 const MCDisassembler *Decoder) {
610 unsigned Op1, Op2, Op3;
611 DecodeStatus S =
612 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
613 if (S == MCDisassembler::Success) {
614 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
615 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
616 DecodeBitpOperand(Inst, Op3, Address, Decoder);
617 }
618 return S;
619 }
620
DecodeL6RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)621 static DecodeStatus DecodeL6RInstruction(MCInst &Inst, unsigned Insn,
622 uint64_t Address,
623 const MCDisassembler *Decoder) {
624 unsigned Op1, Op2, Op3, Op4, Op5, Op6;
625 DecodeStatus S =
626 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
627 if (S != MCDisassembler::Success)
628 return S;
629 S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
630 if (S != MCDisassembler::Success)
631 return S;
632 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
633 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
634 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
635 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
636 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
637 DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
638 return S;
639 }
640
DecodeL5RInstructionFail(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)641 static DecodeStatus DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn,
642 uint64_t Address,
643 const MCDisassembler *Decoder) {
644 // Try and decode as a L6R instruction.
645 Inst.clear();
646 unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
647 switch (Opcode) {
648 case 0x00:
649 Inst.setOpcode(XCore::LMUL_l6r);
650 return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
651 }
652 return MCDisassembler::Fail;
653 }
654
DecodeL5RInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)655 static DecodeStatus DecodeL5RInstruction(MCInst &Inst, unsigned Insn,
656 uint64_t Address,
657 const MCDisassembler *Decoder) {
658 unsigned Op1, Op2, Op3, Op4, Op5;
659 DecodeStatus S =
660 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
661 if (S != MCDisassembler::Success)
662 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
663 S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
664 if (S != MCDisassembler::Success)
665 return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
666
667 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
668 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
669 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
670 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
671 DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
672 return S;
673 }
674
DecodeL4RSrcDstInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)675 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn,
676 uint64_t Address,
677 const MCDisassembler *Decoder) {
678 unsigned Op1, Op2, Op3;
679 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
680 DecodeStatus S =
681 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
682 if (S == MCDisassembler::Success) {
683 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
684 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
685 }
686 if (S == MCDisassembler::Success) {
687 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
688 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
689 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
690 }
691 return S;
692 }
693
694 static DecodeStatus
DecodeL4RSrcDstSrcDstInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder)695 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
696 const MCDisassembler *Decoder) {
697 unsigned Op1, Op2, Op3;
698 unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
699 DecodeStatus S =
700 Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
701 if (S == MCDisassembler::Success) {
702 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
703 S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
704 }
705 if (S == MCDisassembler::Success) {
706 DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
707 DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
708 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
709 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
710 }
711 return S;
712 }
713
714 MCDisassembler::DecodeStatus
getInstruction(MCInst & instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & cStream) const715 XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size,
716 ArrayRef<uint8_t> Bytes, uint64_t Address,
717 raw_ostream &cStream) const {
718 uint16_t insn16;
719
720 if (!readInstruction16(Bytes, Address, Size, insn16)) {
721 return Fail;
722 }
723
724 // Calling the auto-generated decoder function.
725 DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
726 Address, this, STI);
727 if (Result != Fail) {
728 Size = 2;
729 return Result;
730 }
731
732 uint32_t insn32;
733
734 if (!readInstruction32(Bytes, Address, Size, insn32)) {
735 return Fail;
736 }
737
738 // Calling the auto-generated decoder function.
739 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
740 if (Result != Fail) {
741 Size = 4;
742 return Result;
743 }
744
745 return Fail;
746 }
747
createXCoreDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)748 static MCDisassembler *createXCoreDisassembler(const Target &T,
749 const MCSubtargetInfo &STI,
750 MCContext &Ctx) {
751 return new XCoreDisassembler(STI, Ctx);
752 }
753
754 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeXCoreDisassembler()755 LLVMInitializeXCoreDisassembler() {
756 // Register the disassembler.
757 TargetRegistry::RegisterMCDisassembler(getTheXCoreTarget(),
758 createXCoreDisassembler);
759 }
760