1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5, int LoadUOps = 1> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ReleaseAtCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ReleaseAtCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, LoadUOps); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteMULX32, [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>; 126defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 128defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 129defm : SKLWriteResPair<WriteMULX64, [SKLPort1,SKLPort5], 3, [1,1], 2>; 130defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 131defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 132def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 133def : WriteRes<WriteIMulHLd, []> { 134 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency); 135} 136 137defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 138defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 139defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 140defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 141defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 142 143// TODO: Why isn't the SKLDivider used? 144defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 145defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 146defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 147defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 148defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 149defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 150defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 151 152defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 153defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 154defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 155defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 156defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 157defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 158defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 159defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 160 161defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 162 163def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 164 165defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 166defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 167def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 168def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 169 let Latency = 2; 170 let NumMicroOps = 3; 171} 172 173defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 174defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 176defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 177defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 178defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 179defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 180 181// Bit counts. 182defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 183defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 184defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 185defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 186defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 187 188// Integer shifts and rotates. 189defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 190defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 191defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 192defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 193 194// SHLD/SHRD. 195defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 196defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 197defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 198defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 199 200// BMI1 BEXTR/BLS, BMI2 BZHI 201defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 202defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 203defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 204 205// Loads, stores, and moves, not folded with other operations. 206defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 207defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 209defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 210 211// Model the effect of clobbering the read-write mask operand of the GATHER operation. 212// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 213defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 214 215// Idioms that clear a register, like xorps %xmm0, %xmm0. 216// These can often bypass execution ports completely. 217def : WriteRes<WriteZero, []>; 218 219// Branches don't produce values, so they have no latency, but they still 220// consume resources. Indirect branches can fold loads. 221defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 222 223// Floating point. This covers both scalar and vector operations. 224defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 225defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 226defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 227defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 228defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 229defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 230defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 232defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 235defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 236defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 237defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 240defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 241defm : X86WriteRes<WriteFMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 242defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 243 244defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 245defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 246defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 247defm : X86WriteResUnsupported<WriteFMoveZ>; 248defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 249 250defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 251defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 252defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 253defm : X86WriteResPairUnsupported<WriteFAddZ>; 254defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 255defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 256defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 257defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 258 259defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 260defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 261defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 262defm : X86WriteResPairUnsupported<WriteFCmpZ>; 263defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 264defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 265defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 266defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 267 268defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). 269defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). 270 271defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 272defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 273defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 274defm : X86WriteResPairUnsupported<WriteFMulZ>; 275defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 276defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 277defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 278defm : X86WriteResPairUnsupported<WriteFMul64Z>; 279 280defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 281defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 282defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 283defm : X86WriteResPairUnsupported<WriteFDivZ>; 284defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 5>; // Floating point double division. 285defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 6>; 286defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,8], 1, 7>; 287defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 288 289defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 290defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 291defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 292defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 293defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 294defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 295defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 296defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 297defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 298 299defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 300defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 301defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 302defm : X86WriteResPairUnsupported<WriteFRcpZ>; 303 304defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 305defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 306defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 307defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 308 309defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 310defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 311defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 312defm : X86WriteResPairUnsupported<WriteFMAZ>; 313defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 314defm : X86WriteRes<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4>; 315defm : X86WriteRes<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4>; 316defm : X86WriteRes<WriteDPPSLd, [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 19, [1,3,1,1], 6>; 317defm : X86WriteRes<WriteDPPSYLd, [SKLPort5,SKLPort01,SKLPort06,SKLPort23], 20, [1,3,1,1], 6>; 318defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 319defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 320defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 321defm : X86WriteResPairUnsupported<WriteFRndZ>; 322defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 323defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 324defm : X86WriteResPairUnsupported<WriteFLogicZ>; 325defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 326defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 327defm : X86WriteResPairUnsupported<WriteFTestZ>; 328defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 329defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 330defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 331defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 332defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 333defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 334defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 335defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 336defm : X86WriteResPairUnsupported<WriteFBlendZ>; 337defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 338defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 339defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 340 341// FMA Scheduling helper class. 342// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 343 344// Vector integer operations. 345defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 346defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 347defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 348defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 349defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 350defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 351defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 352defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 353defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 354defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 356defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 359defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 360defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 361defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 362defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 363defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 364defm : X86WriteResUnsupported<WriteVecMoveZ>; 365defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 366defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 367 368defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 369defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 370defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 371defm : X86WriteResPairUnsupported<WriteVecALUZ>; 372defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 373defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 374defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 375defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 376defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 377defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 378defm : X86WriteResPairUnsupported<WriteVecTestZ>; 379defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. 380defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; 381defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; 382defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 383defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 384defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 385defm : X86WriteResPairUnsupported<WritePMULLDZ>; 386defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 387defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 388defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 389defm : X86WriteResPairUnsupported<WriteShuffleZ>; 390defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 391defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 392defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 393defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 394defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 395defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 396defm : X86WriteResPairUnsupported<WriteBlendZ>; 397defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 398defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 399defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 400defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 401defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 402defm : X86WriteResPairUnsupported<WriteMPSADZ>; 403defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 404defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 405defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 406defm : X86WriteResPairUnsupported<WritePSADBWZ>; 407defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 408 409// Vector integer shifts. 410defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 411defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 412defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 413defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 414defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 415defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 416 417defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 418defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 419defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 420defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 421defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 422defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 423defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 424 425// Vector insert/extract operations. 426def : WriteRes<WriteVecInsert, [SKLPort5]> { 427 let Latency = 2; 428 let NumMicroOps = 2; 429 let ReleaseAtCycles = [2]; 430} 431def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 432 let Latency = 6; 433 let NumMicroOps = 2; 434} 435def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 436 437def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 438 let Latency = 3; 439 let NumMicroOps = 2; 440} 441def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 442 let Latency = 2; 443 let NumMicroOps = 3; 444} 445 446// Conversion between integer and float. 447defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>; 448defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort01], 4, [1], 1, 6>; 449defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort01], 4, [1], 1, 7>; 450defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 451defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>; 452defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>; 453defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>; 454defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 455 456defm : X86WriteRes<WriteCvtI2SS, [SKLPort5,SKLPort01], 5, [1,1], 2>; 457defm : X86WriteRes<WriteCvtI2SSLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 458defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort01], 4, [1], 1, 6>; 459defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort01], 4, [1], 1, 7>; 460defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 461defm : X86WriteRes<WriteCvtI2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 462defm : X86WriteRes<WriteCvtI2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 463defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort0,SKLPort5], 5, [1,1], 2, 6>; 464defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort0,SKLPort5], 7, [1,1], 2, 6>; 465defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 466 467defm : X86WriteRes<WriteCvtSS2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 468defm : X86WriteRes<WriteCvtSS2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 469defm : X86WriteRes<WriteCvtPS2PD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPS2PDLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 471defm : X86WriteRes<WriteCvtPS2PDY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 472defm : X86WriteRes<WriteCvtPS2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>; 473defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 474defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort5,SKLPort01], 5, [1,1], 2, 5>; 475defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>; 476defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>; 477defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 478 479defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort01], 5, [1,1], 2>; 480defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 481defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 482defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 484defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 485 486defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort01], 5, [1,1], 2>; 487defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 488defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 489defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 490defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 491defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 492 493// Strings instructions. 494 495// Packed Compare Implicit Length Strings, Return Mask 496def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 497 let Latency = 10; 498 let NumMicroOps = 3; 499 let ReleaseAtCycles = [3]; 500} 501def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 502 let Latency = 16; 503 let NumMicroOps = 4; 504 let ReleaseAtCycles = [3,1]; 505} 506 507// Packed Compare Explicit Length Strings, Return Mask 508def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 509 let Latency = 19; 510 let NumMicroOps = 9; 511 let ReleaseAtCycles = [4,3,1,1]; 512} 513def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 514 let Latency = 25; 515 let NumMicroOps = 10; 516 let ReleaseAtCycles = [4,3,1,1,1]; 517} 518 519// Packed Compare Implicit Length Strings, Return Index 520def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 521 let Latency = 10; 522 let NumMicroOps = 3; 523 let ReleaseAtCycles = [3]; 524} 525def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 526 let Latency = 16; 527 let NumMicroOps = 4; 528 let ReleaseAtCycles = [3,1]; 529} 530 531// Packed Compare Explicit Length Strings, Return Index 532def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 533 let Latency = 18; 534 let NumMicroOps = 8; 535 let ReleaseAtCycles = [4,3,1]; 536} 537def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 538 let Latency = 24; 539 let NumMicroOps = 9; 540 let ReleaseAtCycles = [4,3,1,1]; 541} 542 543// MOVMSK Instructions. 544def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 545def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 546def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 547def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 548 549// AES instructions. 550def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 551 let Latency = 4; 552 let NumMicroOps = 1; 553 let ReleaseAtCycles = [1]; 554} 555def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 556 let Latency = 10; 557 let NumMicroOps = 2; 558 let ReleaseAtCycles = [1,1]; 559} 560 561def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 562 let Latency = 8; 563 let NumMicroOps = 2; 564 let ReleaseAtCycles = [2]; 565} 566def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 567 let Latency = 14; 568 let NumMicroOps = 3; 569 let ReleaseAtCycles = [2,1]; 570} 571 572def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 573 let Latency = 20; 574 let NumMicroOps = 11; 575 let ReleaseAtCycles = [3,6,2]; 576} 577def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 578 let Latency = 25; 579 let NumMicroOps = 11; 580 let ReleaseAtCycles = [3,6,1,1]; 581} 582 583// Carry-less multiplication instructions. 584def : WriteRes<WriteCLMul, [SKLPort5]> { 585 let Latency = 6; 586 let NumMicroOps = 1; 587 let ReleaseAtCycles = [1]; 588} 589def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 590 let Latency = 12; 591 let NumMicroOps = 2; 592 let ReleaseAtCycles = [1,1]; 593} 594 595// Catch-all for expensive system instructions. 596def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 597 598// AVX2. 599defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 600defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 601defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 602defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 603defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 604 605// Old microcoded instructions that nobody use. 606def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 607 608// Fence instructions. 609def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 610 611// Load/store MXCSR. 612def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 613def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 614 615// Nop, not very useful expect it provides a model for nops! 616def : WriteRes<WriteNop, []>; 617 618//////////////////////////////////////////////////////////////////////////////// 619// Horizontal add/sub instructions. 620//////////////////////////////////////////////////////////////////////////////// 621 622defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 623defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 624defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 625defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 626defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 627 628// Remaining instrs. 629 630def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 631 let Latency = 1; 632 let NumMicroOps = 1; 633 let ReleaseAtCycles = [1]; 634} 635def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr", 636 "MMX_PADDUS(B|W)rr", 637 "MMX_PAVG(B|W)rr", 638 "MMX_PCMPEQ(B|D|W)rr", 639 "MMX_PCMPGT(B|D|W)rr", 640 "MMX_P(MAX|MIN)SWrr", 641 "MMX_P(MAX|MIN)UBrr", 642 "MMX_PSUBS(B|W)rr", 643 "MMX_PSUBUS(B|W)rr")>; 644 645def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 646 let Latency = 1; 647 let NumMicroOps = 1; 648 let ReleaseAtCycles = [1]; 649} 650def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 651 "UCOM_F(P?)r")>; 652 653def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 654 let Latency = 1; 655 let NumMicroOps = 1; 656 let ReleaseAtCycles = [1]; 657} 658def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 659 660def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 661 let Latency = 1; 662 let NumMicroOps = 1; 663 let ReleaseAtCycles = [1]; 664} 665def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 666 667def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 668 let Latency = 1; 669 let NumMicroOps = 1; 670 let ReleaseAtCycles = [1]; 671} 672def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 673 674def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 675 let Latency = 1; 676 let NumMicroOps = 1; 677 let ReleaseAtCycles = [1]; 678} 679def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 680 681def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 682 let Latency = 1; 683 let NumMicroOps = 1; 684 let ReleaseAtCycles = [1]; 685} 686def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 687 "VPBLENDD(Y?)rri")>; 688 689def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 690 let Latency = 1; 691 let NumMicroOps = 1; 692 let ReleaseAtCycles = [1]; 693} 694def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m, 695 SIDT64m, 696 SMSW16m, 697 STRm, 698 SYSCALL)>; 699 700def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 701 let Latency = 1; 702 let NumMicroOps = 2; 703 let ReleaseAtCycles = [1,1]; 704} 705def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 706def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 707 708def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 709 let Latency = 2; 710 let NumMicroOps = 2; 711 let ReleaseAtCycles = [2]; 712} 713def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 714 715def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 716 let Latency = 2; 717 let NumMicroOps = 2; 718 let ReleaseAtCycles = [2]; 719} 720def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 721 MMX_MOVDQ2Qrr)>; 722 723def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 724 let Latency = 2; 725 let NumMicroOps = 2; 726 let ReleaseAtCycles = [2]; 727} 728def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 729 WAIT, 730 XGETBV)>; 731 732def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 733 let Latency = 2; 734 let NumMicroOps = 2; 735 let ReleaseAtCycles = [1,1]; 736} 737def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 738 739def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 740 let Latency = 2; 741 let NumMicroOps = 2; 742 let ReleaseAtCycles = [1,1]; 743} 744def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 745 746def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 747 let Latency = 2; 748 let NumMicroOps = 2; 749 let ReleaseAtCycles = [1,1]; 750} 751def: InstRW<[SKLWriteResGroup23], (instrs CWD, 752 JCXZ, JECXZ, JRCXZ, 753 ADC8i8, SBB8i8, 754 ADC16i16, SBB16i16, 755 ADC32i32, SBB32i32, 756 ADC64i32, SBB64i32)>; 757 758def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 759 let Latency = 2; 760 let NumMicroOps = 3; 761 let ReleaseAtCycles = [1,1,1]; 762} 763def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 764 765def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 766 let Latency = 2; 767 let NumMicroOps = 3; 768 let ReleaseAtCycles = [1,1,1]; 769} 770def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 771 772def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 773 let Latency = 2; 774 let NumMicroOps = 3; 775 let ReleaseAtCycles = [1,1,1]; 776} 777def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 778 STOSB, STOSL, STOSQ, STOSW)>; 779def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 780 781def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 782 let Latency = 3; 783 let NumMicroOps = 1; 784 let ReleaseAtCycles = [1]; 785} 786def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 787 "PEXT(32|64)rr")>; 788 789def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 790 let Latency = 3; 791 let NumMicroOps = 1; 792 let ReleaseAtCycles = [1]; 793} 794def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 795 "VPBROADCAST(B|W)rr")>; 796 797def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 798 let Latency = 3; 799 let NumMicroOps = 2; 800 let ReleaseAtCycles = [1,1]; 801} 802def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 803 804def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 805 let Latency = 3; 806 let NumMicroOps = 3; 807 let ReleaseAtCycles = [1,2]; 808} 809def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 810 811def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 812 let Latency = 3; 813 let NumMicroOps = 3; 814 let ReleaseAtCycles = [2,1]; 815} 816def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 817 "(V?)PHSUBSW(Y?)rr")>; 818 819def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 820 let Latency = 3; 821 let NumMicroOps = 3; 822 let ReleaseAtCycles = [2,1]; 823} 824def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr, 825 MMX_PACKSSWBrr, 826 MMX_PACKUSWBrr)>; 827 828def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 829 let Latency = 3; 830 let NumMicroOps = 3; 831 let ReleaseAtCycles = [1,2]; 832} 833def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 834 835def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 836 let Latency = 3; 837 let NumMicroOps = 3; 838 let ReleaseAtCycles = [1,2]; 839} 840def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 841 842def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 843 let Latency = 2; 844 let NumMicroOps = 3; 845 let ReleaseAtCycles = [1,2]; 846} 847def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 848 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 849 850def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 851 let Latency = 5; 852 let NumMicroOps = 8; 853 let ReleaseAtCycles = [2,4,2]; 854} 855def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 856 857def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 858 let Latency = 6; 859 let NumMicroOps = 8; 860 let ReleaseAtCycles = [2,4,2]; 861} 862def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 863 864def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 865 let Latency = 3; 866 let NumMicroOps = 3; 867 let ReleaseAtCycles = [1,1,1]; 868} 869def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 870 871def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 872 let Latency = 3; 873 let NumMicroOps = 4; 874 let ReleaseAtCycles = [1,1,1,1]; 875} 876def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 877 878def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 879 let Latency = 3; 880 let NumMicroOps = 4; 881 let ReleaseAtCycles = [1,1,1,1]; 882} 883def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 884 885def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 886 let Latency = 4; 887 let NumMicroOps = 1; 888 let ReleaseAtCycles = [1]; 889} 890def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 891 892def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 893 let Latency = 4; 894 let NumMicroOps = 3; 895 let ReleaseAtCycles = [1,1,1]; 896} 897def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 898 "IST_F(16|32)m")>; 899 900def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 901 let Latency = 4; 902 let NumMicroOps = 4; 903 let ReleaseAtCycles = [4]; 904} 905def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 906 907def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 908 let Latency = 4; 909 let NumMicroOps = 4; 910 let ReleaseAtCycles = [1,3]; 911} 912def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 913 914def SKLWriteResGroup56 : SchedWriteRes<[]> { 915 let Latency = 0; 916 let NumMicroOps = 4; 917 let ReleaseAtCycles = []; 918} 919def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 920 921def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 922 let Latency = 4; 923 let NumMicroOps = 4; 924 let ReleaseAtCycles = [1,1,2]; 925} 926def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 927 928def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> { 929 let Latency = 5; 930 let NumMicroOps = 2; 931 let ReleaseAtCycles = [1,1]; 932} 933def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>; 934 935def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 936 let Latency = 5; 937 let NumMicroOps = 3; 938 let ReleaseAtCycles = [1,1,1]; 939} 940def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 941 942def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 943 let Latency = 5; 944 let NumMicroOps = 5; 945 let ReleaseAtCycles = [1,4]; 946} 947def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 948 949def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 950 let Latency = 5; 951 let NumMicroOps = 6; 952 let ReleaseAtCycles = [1,1,4]; 953} 954def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 955 956def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 957 let Latency = 6; 958 let NumMicroOps = 1; 959 let ReleaseAtCycles = [1]; 960} 961def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 962 VPBROADCASTDrm, 963 VPBROADCASTQrm)>; 964def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 965 "(V?)MOVSLDUPrm", 966 "(V?)MOVDDUPrm")>; 967 968def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 969 let Latency = 6; 970 let NumMicroOps = 2; 971 let ReleaseAtCycles = [2]; 972} 973def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>; 974 975def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 976 let Latency = 6; 977 let NumMicroOps = 2; 978 let ReleaseAtCycles = [1,1]; 979} 980def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm, 981 MMX_PADDSWrm, 982 MMX_PADDUSBrm, 983 MMX_PADDUSWrm, 984 MMX_PAVGBrm, 985 MMX_PAVGWrm, 986 MMX_PCMPEQBrm, 987 MMX_PCMPEQDrm, 988 MMX_PCMPEQWrm, 989 MMX_PCMPGTBrm, 990 MMX_PCMPGTDrm, 991 MMX_PCMPGTWrm, 992 MMX_PMAXSWrm, 993 MMX_PMAXUBrm, 994 MMX_PMINSWrm, 995 MMX_PMINUBrm, 996 MMX_PSUBSBrm, 997 MMX_PSUBSWrm, 998 MMX_PSUBUSBrm, 999 MMX_PSUBUSWrm)>; 1000 1001def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1002 let Latency = 6; 1003 let NumMicroOps = 2; 1004 let ReleaseAtCycles = [1,1]; 1005} 1006def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; 1007def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1008 1009def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1010 let Latency = 6; 1011 let NumMicroOps = 2; 1012 let ReleaseAtCycles = [1,1]; 1013} 1014def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1015 "MOVBE(16|32|64)rm")>; 1016 1017def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1018 let Latency = 6; 1019 let NumMicroOps = 2; 1020 let ReleaseAtCycles = [1,1]; 1021} 1022def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1023def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1024 1025def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1026 let Latency = 6; 1027 let NumMicroOps = 3; 1028 let ReleaseAtCycles = [2,1]; 1029} 1030def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1031 1032def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1033 let Latency = 6; 1034 let NumMicroOps = 4; 1035 let ReleaseAtCycles = [1,1,1,1]; 1036} 1037def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1038 1039def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1040 let Latency = 6; 1041 let NumMicroOps = 4; 1042 let ReleaseAtCycles = [1,1,1,1]; 1043} 1044def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1045 "SHL(8|16|32|64)m(1|i)", 1046 "SHR(8|16|32|64)m(1|i)")>; 1047 1048def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1049 let Latency = 6; 1050 let NumMicroOps = 4; 1051 let ReleaseAtCycles = [1,1,1,1]; 1052} 1053def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1054 "PUSH(16|32|64)rmm")>; 1055 1056def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1057 let Latency = 6; 1058 let NumMicroOps = 6; 1059 let ReleaseAtCycles = [1,5]; 1060} 1061def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1062 1063def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1064 let Latency = 7; 1065 let NumMicroOps = 1; 1066 let ReleaseAtCycles = [1]; 1067} 1068def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1069def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm, 1070 VBROADCASTI128rm, 1071 VBROADCASTSDYrm, 1072 VBROADCASTSSYrm, 1073 VMOVDDUPYrm, 1074 VMOVSHDUPYrm, 1075 VMOVSLDUPYrm, 1076 VPBROADCASTDYrm, 1077 VPBROADCASTQYrm)>; 1078 1079def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1080 let Latency = 6; 1081 let NumMicroOps = 2; 1082 let ReleaseAtCycles = [1,1]; 1083} 1084def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1085 "(V?)PMOV(SX|ZX)BQrm", 1086 "(V?)PMOV(SX|ZX)BWrm", 1087 "(V?)PMOV(SX|ZX)DQrm", 1088 "(V?)PMOV(SX|ZX)WDrm", 1089 "(V?)PMOV(SX|ZX)WQrm")>; 1090 1091def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1092 let Latency = 7; 1093 let NumMicroOps = 2; 1094 let ReleaseAtCycles = [1,1]; 1095} 1096def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1097 VINSERTI128rm, 1098 VPBLENDDrmi)>; 1099def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1100 (instregex "(V?)PADD(B|D|Q|W)rm", 1101 "(V?)PSUB(B|D|Q|W)rm")>; 1102 1103def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1104 let Latency = 7; 1105 let NumMicroOps = 3; 1106 let ReleaseAtCycles = [2,1]; 1107} 1108def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm, 1109 MMX_PACKSSWBrm, 1110 MMX_PACKUSWBrm)>; 1111 1112def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1113 let Latency = 7; 1114 let NumMicroOps = 3; 1115 let ReleaseAtCycles = [1,2]; 1116} 1117def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1118 SCASB, SCASL, SCASQ, SCASW)>; 1119 1120def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1121 let Latency = 7; 1122 let NumMicroOps = 3; 1123 let ReleaseAtCycles = [1,1,1]; 1124} 1125def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>; 1126 1127def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1128 let Latency = 7; 1129 let NumMicroOps = 3; 1130 let ReleaseAtCycles = [1,1,1]; 1131} 1132def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1133 1134def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1135 let Latency = 7; 1136 let NumMicroOps = 3; 1137 let ReleaseAtCycles = [1,1,1]; 1138} 1139def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>; 1140 1141def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1142 let Latency = 7; 1143 let NumMicroOps = 5; 1144 let ReleaseAtCycles = [1,1,1,2]; 1145} 1146def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1147 "ROR(8|16|32|64)m(1|i)")>; 1148 1149def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1150 let Latency = 2; 1151 let NumMicroOps = 2; 1152 let ReleaseAtCycles = [2]; 1153} 1154def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1155 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1156 1157def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1158 let Latency = 7; 1159 let NumMicroOps = 5; 1160 let ReleaseAtCycles = [1,1,1,2]; 1161} 1162def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1163 1164def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1165 let Latency = 7; 1166 let NumMicroOps = 5; 1167 let ReleaseAtCycles = [1,1,1,1,1]; 1168} 1169def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1170def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; 1171 1172def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1173 let Latency = 7; 1174 let NumMicroOps = 7; 1175 let ReleaseAtCycles = [1,3,1,2]; 1176} 1177def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1178 1179def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1180 let Latency = 8; 1181 let NumMicroOps = 2; 1182 let ReleaseAtCycles = [1,1]; 1183} 1184def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1185 "PEXT(32|64)rm")>; 1186 1187def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1188 let Latency = 8; 1189 let NumMicroOps = 2; 1190 let ReleaseAtCycles = [1,1]; 1191} 1192def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1193def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1194 VPBROADCASTWYrm, 1195 VPMOVSXBDYrm, 1196 VPMOVSXBQYrm, 1197 VPMOVSXWQYrm)>; 1198 1199def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1200 let Latency = 8; 1201 let NumMicroOps = 2; 1202 let ReleaseAtCycles = [1,1]; 1203} 1204def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1205def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1206 (instregex "VPADD(B|D|Q|W)Yrm", 1207 "VPSUB(B|D|Q|W)Yrm")>; 1208 1209def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1210 let Latency = 8; 1211 let NumMicroOps = 4; 1212 let ReleaseAtCycles = [1,2,1]; 1213} 1214def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1215 1216def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1217 let Latency = 8; 1218 let NumMicroOps = 5; 1219 let ReleaseAtCycles = [1,1,1,2]; 1220} 1221def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1222 "RCR(8|16|32|64)m(1|i)")>; 1223 1224def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1225 let Latency = 8; 1226 let NumMicroOps = 6; 1227 let ReleaseAtCycles = [1,1,1,3]; 1228} 1229def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1230 "ROR(8|16|32|64)mCL", 1231 "SAR(8|16|32|64)mCL", 1232 "SHL(8|16|32|64)mCL", 1233 "SHR(8|16|32|64)mCL")>; 1234 1235def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1236 let Latency = 8; 1237 let NumMicroOps = 6; 1238 let ReleaseAtCycles = [1,1,1,2,1]; 1239} 1240def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1241 1242def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1243 let Latency = 9; 1244 let NumMicroOps = 2; 1245 let ReleaseAtCycles = [1,1]; 1246} 1247def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>; 1248 1249def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1250 let Latency = 9; 1251 let NumMicroOps = 2; 1252 let ReleaseAtCycles = [1,1]; 1253} 1254def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1255 VPCMPGTQrm, 1256 VPMOVSXBWYrm, 1257 VPMOVSXDQYrm, 1258 VPMOVSXWDYrm, 1259 VPMOVZXWDYrm)>; 1260 1261def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1262 let Latency = 9; 1263 let NumMicroOps = 2; 1264 let ReleaseAtCycles = [1,1]; 1265} 1266def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>; 1267 1268def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1269 let Latency = 9; 1270 let NumMicroOps = 4; 1271 let ReleaseAtCycles = [2,1,1]; 1272} 1273def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1274 "(V?)PHSUBSWrm")>; 1275 1276def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1277 let Latency = 9; 1278 let NumMicroOps = 5; 1279 let ReleaseAtCycles = [1,2,1,1]; 1280} 1281def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1282 "LSL(16|32|64)rm")>; 1283 1284def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1285 let Latency = 10; 1286 let NumMicroOps = 2; 1287 let ReleaseAtCycles = [1,1]; 1288} 1289def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1290 "ILD_F(16|32|64)m")>; 1291def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1292 1293def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1294 let Latency = 10; 1295 let NumMicroOps = 3; 1296 let ReleaseAtCycles = [1,1,1]; 1297} 1298def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>; 1299 1300def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1301 let Latency = 10; 1302 let NumMicroOps = 4; 1303 let ReleaseAtCycles = [2,1,1]; 1304} 1305def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1306 VPHSUBSWYrm)>; 1307 1308def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1309 let Latency = 10; 1310 let NumMicroOps = 8; 1311 let ReleaseAtCycles = [1,1,1,1,1,3]; 1312} 1313def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1314 1315def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1316 let Latency = 11; 1317 let NumMicroOps = 2; 1318 let ReleaseAtCycles = [1,1]; 1319} 1320def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1321 1322def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1323 let Latency = 11; 1324 let NumMicroOps = 3; 1325 let ReleaseAtCycles = [2,1]; 1326} 1327def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1328 1329def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1330 let Latency = 11; 1331 let NumMicroOps = 7; 1332 let ReleaseAtCycles = [2,3,2]; 1333} 1334def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1335 "RCR(16|32|64)rCL")>; 1336 1337def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1338 let Latency = 11; 1339 let NumMicroOps = 9; 1340 let ReleaseAtCycles = [1,5,1,2]; 1341} 1342def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1343 1344def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1345 let Latency = 11; 1346 let NumMicroOps = 11; 1347 let ReleaseAtCycles = [2,9]; 1348} 1349def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1350 1351def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1352 let Latency = 13; 1353 let NumMicroOps = 3; 1354 let ReleaseAtCycles = [2,1]; 1355} 1356def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1357 1358def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1359 let Latency = 14; 1360 let NumMicroOps = 3; 1361 let ReleaseAtCycles = [1,1,1]; 1362} 1363def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1364 1365def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1366 let Latency = 14; 1367 let NumMicroOps = 10; 1368 let ReleaseAtCycles = [2,4,1,3]; 1369} 1370def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1371 1372def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1373 let Latency = 15; 1374 let NumMicroOps = 1; 1375 let ReleaseAtCycles = [1]; 1376} 1377def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1378 1379def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1380 let Latency = 15; 1381 let NumMicroOps = 10; 1382 let ReleaseAtCycles = [1,1,1,5,1,1]; 1383} 1384def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1385 1386def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1387 let Latency = 16; 1388 let NumMicroOps = 14; 1389 let ReleaseAtCycles = [1,1,1,4,2,5]; 1390} 1391def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1392 1393def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1394 let Latency = 16; 1395 let NumMicroOps = 16; 1396 let ReleaseAtCycles = [16]; 1397} 1398def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1399 1400def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1401 let Latency = 17; 1402 let NumMicroOps = 15; 1403 let ReleaseAtCycles = [2,1,2,4,2,4]; 1404} 1405def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1406 1407def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1408 let Latency = 18; 1409 let NumMicroOps = 8; 1410 let ReleaseAtCycles = [1,1,1,5]; 1411} 1412def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1413 1414def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1415 let Latency = 18; 1416 let NumMicroOps = 11; 1417 let ReleaseAtCycles = [2,1,1,4,1,2]; 1418} 1419def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1420 1421def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1422 let Latency = 20; 1423 let NumMicroOps = 1; 1424 let ReleaseAtCycles = [1]; 1425} 1426def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1427 1428def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1429 let Latency = 20; 1430 let NumMicroOps = 8; 1431 let ReleaseAtCycles = [1,1,1,1,1,1,2]; 1432} 1433def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1434 1435def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1436 let Latency = 20; 1437 let NumMicroOps = 10; 1438 let ReleaseAtCycles = [1,2,7]; 1439} 1440def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1441 1442def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1443 let Latency = 22; 1444 let NumMicroOps = 2; 1445 let ReleaseAtCycles = [1,1]; 1446} 1447def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1448 1449def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1450 let Latency = 18; 1451 let NumMicroOps = 5; // 2 uops perform multiple loads 1452 let ReleaseAtCycles = [1,2,1,1]; 1453} 1454def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 1455 VGATHERQPDrm, VPGATHERQQrm, 1456 VGATHERQPSrm, VPGATHERQDrm)>; 1457 1458def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1459 let Latency = 20; 1460 let NumMicroOps = 5; // 2 uops peform multiple loads 1461 let ReleaseAtCycles = [1,4,1,1]; 1462} 1463def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1464 VGATHERDPSrm, VPGATHERDDrm, 1465 VGATHERQPDYrm, VPGATHERQQYrm, 1466 VGATHERQPSYrm, VPGATHERQDYrm)>; 1467 1468def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1469 let Latency = 22; 1470 let NumMicroOps = 5; // 2 uops perform multiple loads 1471 let ReleaseAtCycles = [1,8,1,1]; 1472} 1473def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1474 1475def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1476 let Latency = 23; 1477 let NumMicroOps = 19; 1478 let ReleaseAtCycles = [2,1,4,1,1,4,6]; 1479} 1480def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1481 1482def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1483 let Latency = 25; 1484 let NumMicroOps = 3; 1485 let ReleaseAtCycles = [1,1,1]; 1486} 1487def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1488 1489def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1490 let Latency = 27; 1491 let NumMicroOps = 2; 1492 let ReleaseAtCycles = [1,1]; 1493} 1494def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1495 1496def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1497 let Latency = 30; 1498 let NumMicroOps = 3; 1499 let ReleaseAtCycles = [1,1,1]; 1500} 1501def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1502 1503def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1504 let Latency = 35; 1505 let NumMicroOps = 23; 1506 let ReleaseAtCycles = [1,5,3,4,10]; 1507} 1508def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1509 "IN(8|16|32)rr")>; 1510 1511def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1512 let Latency = 35; 1513 let NumMicroOps = 23; 1514 let ReleaseAtCycles = [1,5,2,1,4,10]; 1515} 1516def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1517 "OUT(8|16|32)rr")>; 1518 1519def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1520 let Latency = 37; 1521 let NumMicroOps = 31; 1522 let ReleaseAtCycles = [1,8,1,21]; 1523} 1524def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1525 1526def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1527 let Latency = 40; 1528 let NumMicroOps = 18; 1529 let ReleaseAtCycles = [1,1,2,3,1,1,1,8]; 1530} 1531def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1532 1533def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1534 let Latency = 41; 1535 let NumMicroOps = 39; 1536 let ReleaseAtCycles = [1,10,1,1,26]; 1537} 1538def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1539 1540def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1541 let Latency = 42; 1542 let NumMicroOps = 22; 1543 let ReleaseAtCycles = [2,20]; 1544} 1545def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1546 1547def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1548 let Latency = 42; 1549 let NumMicroOps = 40; 1550 let ReleaseAtCycles = [1,11,1,1,26]; 1551} 1552def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1553def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1554 1555def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1556 let Latency = 46; 1557 let NumMicroOps = 44; 1558 let ReleaseAtCycles = [1,11,1,1,30]; 1559} 1560def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1561 1562def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1563 let Latency = 62; 1564 let NumMicroOps = 64; 1565 let ReleaseAtCycles = [2,8,5,10,39]; 1566} 1567def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1568 1569def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1570 let Latency = 63; 1571 let NumMicroOps = 88; 1572 let ReleaseAtCycles = [4,4,31,1,2,1,45]; 1573} 1574def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1575 1576def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1577 let Latency = 63; 1578 let NumMicroOps = 90; 1579 let ReleaseAtCycles = [4,2,33,1,2,1,47]; 1580} 1581def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1582 1583def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1584 let Latency = 75; 1585 let NumMicroOps = 15; 1586 let ReleaseAtCycles = [6,3,6]; 1587} 1588def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1589 1590def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1591 let Latency = 106; 1592 let NumMicroOps = 100; 1593 let ReleaseAtCycles = [9,1,11,16,1,11,21,30]; 1594} 1595def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1596 1597def: InstRW<[WriteZero], (instrs CLC)>; 1598 1599 1600// Instruction variants handled by the renamer. These might not need execution 1601// ports in certain conditions. 1602// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1603// section "Skylake Pipeline" > "Register allocation and renaming". 1604// These can be investigated with llvm-exegesis, e.g. 1605// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1606// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1607 1608def SKLWriteZeroLatency : SchedWriteRes<[]> { 1609 let Latency = 0; 1610} 1611 1612def SKLWriteZeroIdiom : SchedWriteVariant<[ 1613 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1614 SchedVar<NoSchedPred, [WriteALU]> 1615]>; 1616def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1617 XOR32rr, XOR64rr)>; 1618 1619def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1620 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1621 SchedVar<NoSchedPred, [WriteFLogic]> 1622]>; 1623def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1624 VXORPDrr)>; 1625 1626def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1627 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1628 SchedVar<NoSchedPred, [WriteFLogicY]> 1629]>; 1630def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1631 1632def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1633 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1634 SchedVar<NoSchedPred, [WriteVecLogicX]> 1635]>; 1636def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1637 1638def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1639 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1640 SchedVar<NoSchedPred, [WriteVecLogicY]> 1641]>; 1642def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1643 1644def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1645 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1646 SchedVar<NoSchedPred, [WriteVecALUX]> 1647]>; 1648def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1649 PCMPGTDrr, VPCMPGTDrr, 1650 PCMPGTWrr, VPCMPGTWrr)>; 1651 1652def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1653 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1654 SchedVar<NoSchedPred, [WriteVecALUY]> 1655]>; 1656def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1657 VPCMPGTDYrr, 1658 VPCMPGTWYrr)>; 1659 1660def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1661 let Latency = 1; 1662 let NumMicroOps = 1; 1663 let ReleaseAtCycles = [1]; 1664} 1665 1666def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1667 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1668 SchedVar<NoSchedPred, [SKLWritePSUB]> 1669]>; 1670def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1671 PSUBDrr, VPSUBDrr, 1672 PSUBQrr, VPSUBQrr, 1673 PSUBWrr, VPSUBWrr, 1674 VPSUBBYrr, 1675 VPSUBDYrr, 1676 VPSUBQYrr, 1677 VPSUBWYrr)>; 1678 1679def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1680 let Latency = 3; 1681 let NumMicroOps = 1; 1682 let ReleaseAtCycles = [1]; 1683} 1684 1685def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1686 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1687 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1688]>; 1689def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1690 VPCMPGTQYrr)>; 1691 1692 1693// CMOVs that use both Z and C flag require an extra uop. 1694def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1695 let Latency = 2; 1696 let ReleaseAtCycles = [2]; 1697 let NumMicroOps = 2; 1698} 1699 1700def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1701 let Latency = 7; 1702 let ReleaseAtCycles = [1,2]; 1703 let NumMicroOps = 3; 1704} 1705 1706def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1707 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1708 SchedVar<NoSchedPred, [WriteCMOV]> 1709]>; 1710 1711def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1712 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1713 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1714]>; 1715 1716def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1717def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1718 1719// SETCCs that use both Z and C flag require an extra uop. 1720def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1721 let Latency = 2; 1722 let ReleaseAtCycles = [2]; 1723 let NumMicroOps = 2; 1724} 1725 1726def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1727 let Latency = 3; 1728 let ReleaseAtCycles = [1,1,2]; 1729 let NumMicroOps = 4; 1730} 1731 1732def SKLSETA_SETBErr : SchedWriteVariant<[ 1733 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1734 SchedVar<NoSchedPred, [WriteSETCC]> 1735]>; 1736 1737def SKLSETA_SETBErm : SchedWriteVariant<[ 1738 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1739 SchedVar<NoSchedPred, [WriteSETCCStore]> 1740]>; 1741 1742def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1743def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1744 1745/////////////////////////////////////////////////////////////////////////////// 1746// Dependency breaking instructions. 1747/////////////////////////////////////////////////////////////////////////////// 1748 1749def : IsZeroIdiomFunction<[ 1750 // GPR Zero-idioms. 1751 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1752 1753 // SSE Zero-idioms. 1754 DepBreakingClass<[ 1755 // fp variants. 1756 XORPSrr, XORPDrr, 1757 1758 // int variants. 1759 PXORrr, 1760 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1761 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1762 ], ZeroIdiomPredicate>, 1763 1764 // AVX Zero-idioms. 1765 DepBreakingClass<[ 1766 // xmm fp variants. 1767 VXORPSrr, VXORPDrr, 1768 1769 // xmm int variants. 1770 VPXORrr, 1771 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1772 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1773 1774 // ymm variants. 1775 VXORPSYrr, VXORPDYrr, VPXORYrr, 1776 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 1777 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr 1778 ], ZeroIdiomPredicate>, 1779]>; 1780 1781} // SchedModel 1782