1//===----------X86InstrFragments - X86 Pattern fragments. --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// X86-specific DAG node. 10def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 11 SDTCisSameAs<1, 2>]>; 12def SDTX86FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>, 13 SDTCisSameAs<1, 2>]>; 14 15def SDTX86Ccmp : SDTypeProfile<1, 5, 16 [SDTCisVT<3, i8>, SDTCisVT<4, i8>, SDTCisVT<5, i32>]>; 17 18// RES = op PTR, PASSTHRU, COND, EFLAGS 19def SDTX86Cload : SDTypeProfile<1, 4, 20 [SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisSameAs<0, 2>, 21 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 22// op VAL, PTR, COND, EFLAGS 23def SDTX86Cstore : SDTypeProfile<0, 4, 24 [SDTCisInt<0>, SDTCisPtrTy<1>, 25 SDTCisVT<2, i8>, SDTCisVT<3, i32>]>; 26 27def SDTX86Cmov : SDTypeProfile<1, 4, 28 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 29 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 30 31// Unary and binary operator instructions that set EFLAGS as a side-effect. 32def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 33 [SDTCisSameAs<0, 2>, 34 SDTCisInt<0>, SDTCisVT<1, i32>]>; 35 36def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 37 [SDTCisSameAs<0, 2>, 38 SDTCisSameAs<0, 3>, 39 SDTCisInt<0>, SDTCisVT<1, i32>]>; 40 41// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 42def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 43 [SDTCisSameAs<0, 2>, 44 SDTCisSameAs<0, 3>, 45 SDTCisInt<0>, 46 SDTCisVT<1, i32>, 47 SDTCisVT<4, i32>]>; 48// RES1, RES2, FLAGS = op LHS, RHS 49def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 50 [SDTCisSameAs<0, 1>, 51 SDTCisSameAs<0, 2>, 52 SDTCisSameAs<0, 3>, 53 SDTCisInt<0>, SDTCisVT<1, i32>]>; 54def SDTX86BrCond : SDTypeProfile<0, 3, 55 [SDTCisVT<0, OtherVT>, 56 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 57 58def SDTX86SetCC : SDTypeProfile<1, 2, 59 [SDTCisVT<0, i8>, 60 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 61def SDTX86SetCC_C : SDTypeProfile<1, 2, 62 [SDTCisInt<0>, 63 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 64 65def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 66 67def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 68 69def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 70def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 71 SDTCisVT<2, i32>]>; 72 73def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 74 SDTCisVT<2, i8>]>; 75def SDTX86cas8pair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 76def SDTX86cas16pair : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i64>]>; 77 78def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 79 SDTCisPtrTy<1>, 80 SDTCisInt<2>]>; 81 82def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 83 SDTCisPtrTy<1>]>; 84 85def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 86 87def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 88 SDTCisVT<1, i32>]>; 89def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 90 SDTCisVT<1, i32>]>; 91 92def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 93 94def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 95 96def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 97 SDTCisPtrTy<1>]>; 98 99def SDT_X86VAARG : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 100 SDTCisPtrTy<1>, 101 SDTCisVT<2, i32>, 102 SDTCisVT<3, i8>, 103 SDTCisVT<4, i32>]>; 104 105def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 106 107def SDTX86Void : SDTypeProfile<0, 0, []>; 108 109def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 110 111def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 112 113def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 114 115def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 116 117def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 118 119def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 120 121def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 122 123def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 124 125def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 126 127def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 128 SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; 129 130def SDT_X86AESENCDECKL : SDTypeProfile<2, 2, [SDTCisVT<0, v2i64>, 131 SDTCisVT<1, i32>, 132 SDTCisVT<2, v2i64>, 133 SDTCisPtrTy<3>]>; 134 135def SDTX86Cmpccxadd : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, 136 SDTCisPtrTy<1>, SDTCisSameAs<2, 3>, 137 SDTCisVT<4, i8>]>; 138 139def X86MFence : SDNode<"X86ISD::MFENCE", SDTNone, [SDNPHasChain]>; 140 141 142def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 143def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 144def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>; 145def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>; 146 147def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 148def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>; 149def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>; 150def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>; 151def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 152 153def X86ccmp : SDNode<"X86ISD::CCMP", SDTX86Ccmp>; 154def X86ctest : SDNode<"X86ISD::CTEST", SDTX86Ccmp>; 155 156def X86cload : SDNode<"X86ISD::CLOAD", SDTX86Cload, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 157def X86cstore : SDNode<"X86ISD::CSTORE", SDTX86Cstore, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 158 159def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 160def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 161 [SDNPHasChain]>; 162def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 163def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 164 165def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 166 [SDNPHasChain, SDNPSideEffect]>; 167 168def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 169 [SDNPHasChain, SDNPSideEffect]>; 170 171def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, 172 [SDNPHasChain, SDNPSideEffect]>; 173def X86wrpkru : SDNode<"X86ISD::WRPKRU", SDTX86wrpkru, 174 [SDNPHasChain, SDNPSideEffect]>; 175 176def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 177 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 178 SDNPMayLoad, SDNPMemOperand]>; 179def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86cas8pair, 180 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 181 SDNPMayLoad, SDNPMemOperand]>; 182def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86cas16pair, 183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 184 SDNPMayLoad, SDNPMemOperand]>; 185 186def X86retglue : SDNode<"X86ISD::RET_GLUE", SDTX86Ret, 187 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 188def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 189 [SDNPHasChain, SDNPOptInGlue]>; 190 191def X86vastart_save_xmm_regs : 192 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 193 SDT_X86VASTART_SAVE_XMM_REGS, 194 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPVariadic]>; 195def X86vaarg64 : 196 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG, 197 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 198 SDNPMemOperand]>; 199def X86vaargx32 : 200 SDNode<"X86ISD::VAARG_X32", SDT_X86VAARG, 201 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 202 SDNPMemOperand]>; 203def X86callseq_start : 204 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 205 [SDNPHasChain, SDNPOutGlue]>; 206def X86callseq_end : 207 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 208 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 209 210def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 211 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 212 SDNPVariadic]>; 213 214def X86call_rvmarker : SDNode<"X86ISD::CALL_RVMARKER", SDT_X86Call, 215 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 216 SDNPVariadic]>; 217 218 219def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, 220 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 221 SDNPVariadic]>; 222def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, 223 [SDNPHasChain]>; 224 225def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 226 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 227def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 228 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 229 SDNPMayLoad]>; 230 231def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 232def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 233 234def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 235 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 236 SDTCisInt<1>]>>; 237 238def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 239 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 240 241def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 242 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 243 244def X86tlsdesc : SDNode<"X86ISD::TLSDESC", SDT_X86TLSADDR, 245 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 246 247def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 248 [SDNPHasChain]>; 249 250def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 251 SDTypeProfile<1, 1, [SDTCisInt<0>, 252 SDTCisPtrTy<1>]>, 253 [SDNPHasChain, SDNPSideEffect]>; 254def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 255 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 256 [SDNPHasChain, SDNPSideEffect]>; 257def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", 258 SDTypeProfile<0, 0, []>, 259 [SDNPHasChain, SDNPSideEffect]>; 260 261def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 262 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 263 264def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 265 [SDNPCommutative]>; 266def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 267def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 268 [SDNPCommutative]>; 269def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 270 [SDNPCommutative]>; 271def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 272def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 273 274def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 275 [SDNPCommutative]>; 276def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 277 [SDNPCommutative]>; 278def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 279 [SDNPCommutative]>; 280 281def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, 282 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 283 SDNPMemOperand]>; 284def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, 285 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 286 SDNPMemOperand]>; 287def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, 288 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 289 SDNPMemOperand]>; 290def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, 291 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 292 SDNPMemOperand]>; 293def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, 294 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 295 SDNPMemOperand]>; 296 297def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 298def X86bextri : SDNode<"X86ISD::BEXTRI", SDTIntBinOp>; 299 300def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; 301 302def X86pdep : SDNode<"X86ISD::PDEP", SDTIntBinOp>; 303def X86pext : SDNode<"X86ISD::PEXT", SDTIntBinOp>; 304 305def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 306 307def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA, 308 [SDNPHasChain, SDNPOutGlue]>; 309 310def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 311 [SDNPHasChain]>; 312 313def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA, 314 [SDNPHasChain]>; 315 316def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 317 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 318 319def X86lwpins : SDNode<"X86ISD::LWPINS", 320 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 321 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 322 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; 323 324def X86umwait : SDNode<"X86ISD::UMWAIT", 325 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 326 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 327 [SDNPHasChain, SDNPSideEffect]>; 328 329def X86tpause : SDNode<"X86ISD::TPAUSE", 330 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 331 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 332 [SDNPHasChain, SDNPSideEffect]>; 333 334def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD, 335 [SDNPHasChain, SDNPSideEffect]>; 336def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD, 337 [SDNPHasChain, SDNPSideEffect]>; 338def X86testui : SDNode<"X86ISD::TESTUI", 339 SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>, 340 [SDNPHasChain, SDNPSideEffect]>; 341 342def X86aesenc128kl : SDNode<"X86ISD::AESENC128KL", SDT_X86AESENCDECKL, 343 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 344 SDNPMemOperand]>; 345def X86aesdec128kl : SDNode<"X86ISD::AESDEC128KL", SDT_X86AESENCDECKL, 346 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 347 SDNPMemOperand]>; 348def X86aesenc256kl : SDNode<"X86ISD::AESENC256KL", SDT_X86AESENCDECKL, 349 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 350 SDNPMemOperand]>; 351def X86aesdec256kl : SDNode<"X86ISD::AESDEC256KL", SDT_X86AESENCDECKL, 352 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 353 SDNPMemOperand]>; 354 355def X86cmpccxadd : SDNode<"X86ISD::CMPCCXADD", SDTX86Cmpccxadd, 356 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 357 SDNPMemOperand]>; 358 359// Define X86-specific addressing mode. 360def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 361def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 362 [add, sub, mul, X86mul_imm, shl, or, xor, frameindex], 363 []>; 364// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 365def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 366 [add, sub, mul, X86mul_imm, shl, or, xor, 367 frameindex, X86WrapperRIP], 368 []>; 369 370def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 371 [tglobaltlsaddr], []>; 372 373def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 374 [tglobaltlsaddr], []>; 375 376def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 377 [add, sub, mul, X86mul_imm, shl, or, xor, frameindex, 378 X86WrapperRIP], []>; 379 380def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 381 [tglobaltlsaddr], []>; 382 383def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 384 [tglobaltlsaddr], []>; 385 386def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 387 388// A relocatable immediate is an operand that can be relocated by the linker to 389// an immediate, such as a regular symbol in non-PIC code. 390def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", 391 [X86Wrapper], [], 0>; 392 393// X86 specific condition code. These correspond to CondCode in 394// X86InstrInfo.h. They must be kept in synch. 395def X86_COND_O : PatLeaf<(i8 0)>; 396def X86_COND_NO : PatLeaf<(i8 1)>; 397def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 398def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC 399def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 400def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ 401def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA 402def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE 403def X86_COND_S : PatLeaf<(i8 8)>; 404def X86_COND_NS : PatLeaf<(i8 9)>; 405def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE 406def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 407def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE 408def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL 409def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG 410def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE 411 412def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 413def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 414def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 415def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 416def i64timmSExt32 : TImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 417 418def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{ 419 return isSExtAbsoluteSymbolRef(8, N); 420}]>; 421def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{ 422 return isSExtAbsoluteSymbolRef(8, N); 423}]>; 424def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ 425 return isSExtAbsoluteSymbolRef(8, N); 426}]>; 427def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ 428 return isSExtAbsoluteSymbolRef(32, N); 429}]>; 430 431// If we have multiple users of an immediate, it's much smaller to reuse 432// the register, rather than encode the immediate in every instruction. 433// This has the risk of increasing register pressure from stretched live 434// ranges, however, the immediates should be trivial to rematerialize by 435// the RA in the event of high register pressure. 436// TODO : This is currently enabled for stores and binary ops. There are more 437// cases for which this can be enabled, though this catches the bulk of the 438// issues. 439// TODO2 : This should really also be enabled under O2, but there's currently 440// an issue with RA where we don't pull the constants into their users 441// when we rematerialize them. I'll follow-up on enabling O2 after we fix that 442// issue. 443// TODO3 : This is currently limited to single basic blocks (DAG creation 444// pulls block immediates to the top and merges them if necessary). 445// Eventually, it would be nice to allow ConstantHoisting to merge constants 446// globally for potentially added savings. 447// 448def imm_su : PatLeaf<(imm), [{ 449 return !shouldAvoidImmediateInstFormsForSize(N); 450}]>; 451def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ 452 return !shouldAvoidImmediateInstFormsForSize(N); 453}]>; 454 455def relocImm8_su : PatLeaf<(i8 relocImm), [{ 456 return !shouldAvoidImmediateInstFormsForSize(N); 457}]>; 458def relocImm16_su : PatLeaf<(i16 relocImm), [{ 459 return !shouldAvoidImmediateInstFormsForSize(N); 460}]>; 461def relocImm32_su : PatLeaf<(i32 relocImm), [{ 462 return !shouldAvoidImmediateInstFormsForSize(N); 463}]>; 464 465def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{ 466 return !shouldAvoidImmediateInstFormsForSize(N); 467}]>; 468def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{ 469 return !shouldAvoidImmediateInstFormsForSize(N); 470}]>; 471def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ 472 return !shouldAvoidImmediateInstFormsForSize(N); 473}]>; 474def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ 475 return !shouldAvoidImmediateInstFormsForSize(N); 476}]>; 477 478def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 479 return !shouldAvoidImmediateInstFormsForSize(N); 480}]>; 481def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 482 return !shouldAvoidImmediateInstFormsForSize(N); 483}]>; 484def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ 485 return !shouldAvoidImmediateInstFormsForSize(N); 486}]>; 487 488// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 489// unsigned field. 490def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 491 492def i64immZExt32SExt8 : ImmLeaf<i64, [{ 493 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 494}]>; 495 496// Helper fragments for loads. 497 498// It's safe to fold a zextload/extload from i1 as a regular i8 load. The 499// upper bits are guaranteed to be zero and we were going to emit a MOV8rm 500// which might get folded during peephole anyway. 501def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ 502 LoadSDNode *LD = cast<LoadSDNode>(N); 503 ISD::LoadExtType ExtType = LD->getExtensionType(); 504 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || 505 ExtType == ISD::ZEXTLOAD; 506}]>; 507 508// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 509// known to be 32-bit aligned or better. Ditto for i8 to i16. 510def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 511 LoadSDNode *LD = cast<LoadSDNode>(N); 512 ISD::LoadExtType ExtType = LD->getExtensionType(); 513 if (ExtType == ISD::NON_EXTLOAD) 514 return true; 515 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 516 return LD->getAlign() >= 2 && LD->isSimple(); 517 return false; 518}]>; 519 520def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 521 LoadSDNode *LD = cast<LoadSDNode>(N); 522 ISD::LoadExtType ExtType = LD->getExtensionType(); 523 if (ExtType == ISD::NON_EXTLOAD) 524 return true; 525 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 526 return LD->getAlign() >= 4 && LD->isSimple(); 527 return false; 528}]>; 529 530def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 531def loadf16 : PatFrag<(ops node:$ptr), (f16 (load node:$ptr))>; 532def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 533def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 534def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 535def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 536def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 537 LoadSDNode *Ld = cast<LoadSDNode>(N); 538 return Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); 539}]>; 540def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 541 LoadSDNode *Ld = cast<LoadSDNode>(N); 542 return Subtarget->hasSSEUnalignedMem() || 543 Ld->getAlign() >= Ld->getMemoryVT().getStoreSize(); 544}]>; 545 546def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 547def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 548def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 549def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 550def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 551def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 552 553def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 554def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 555def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 556def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 557def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 558def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 559def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 560def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 561def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 562def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 563 564def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 565def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 566def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 567def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 568def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 569def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 570def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 571def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 572def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 573 574// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known 575// to be 4 byte aligned or better. 576def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{ 577 LoadSDNode *LD = cast<LoadSDNode>(N); 578 ISD::LoadExtType ExtType = LD->getExtensionType(); 579 if (ExtType != ISD::EXTLOAD) 580 return false; 581 if (LD->getMemoryVT() == MVT::i32) 582 return true; 583 584 return LD->getAlign() >= 4 && LD->isSimple(); 585}]>; 586 587// binary op with only one user 588class binop_oneuse<SDPatternOperator operator> 589 : PatFrag<(ops node:$A, node:$B), 590 (operator node:$A, node:$B), [{ 591 return N->hasOneUse(); 592}]>; 593 594def add_su : binop_oneuse<add>; 595def and_su : binop_oneuse<and>; 596def srl_su : binop_oneuse<srl>; 597 598class binop_twouses<SDPatternOperator operator> 599 : PatFrag<(ops node:$A, node:$B), 600 (operator node:$A, node:$B), [{ 601 return N->hasNUsesOfValue(2, 0); 602}]>; 603 604def and_du : binop_twouses<and>; 605 606// unary op with only one user 607class unop_oneuse<SDPatternOperator operator> 608 : PatFrag<(ops node:$A), 609 (operator node:$A), [{ 610 return N->hasOneUse(); 611}]>; 612 613 614def ineg_su : unop_oneuse<ineg>; 615def trunc_su : unop_oneuse<trunc>; 616 617def X86add_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 618 (X86add_flag node:$lhs, node:$rhs), [{ 619 return hasNoCarryFlagUses(SDValue(N, 1)); 620}]>; 621 622def X86sub_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 623 (X86sub_flag node:$lhs, node:$rhs), [{ 624 // Only use DEC if the result is used. 625 return !SDValue(N, 0).use_empty() && hasNoCarryFlagUses(SDValue(N, 1)); 626}]>; 627 628def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), 629 (X86cmp (and_su node:$lhs, node:$rhs), 0)>; 630def X86ctestpat : PatFrag<(ops node:$lhs, node:$rhs, node:$dcf, node:$cond), 631 (X86ctest (and_du node:$lhs, node:$rhs), 632 (and_du node:$lhs, node:$rhs), node:$dcf, 633 node:$cond, EFLAGS)>; 634 635def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), 636 [(X86strict_fcmp node:$lhs, node:$rhs), 637 (X86fcmp node:$lhs, node:$rhs)]>; 638 639def PrefetchWLevel : PatFrag<(ops), (i32 timm), [{ 640 return N->getSExtValue() <= 3; 641}]>; 642 643def X86lock_add_nocf : PatFrag<(ops node:$lhs, node:$rhs), 644 (X86lock_add node:$lhs, node:$rhs), [{ 645 return hasNoCarryFlagUses(SDValue(N, 0)); 646}]>; 647 648def X86lock_sub_nocf : PatFrag<(ops node:$lhs, node:$rhs), 649 (X86lock_sub node:$lhs, node:$rhs), [{ 650 return hasNoCarryFlagUses(SDValue(N, 0)); 651}]>; 652 653def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off), 654 (X86tcret node:$ptr, node:$off), [{ 655 // X86tcret args: (*chain, ptr, imm, regs..., glue) 656 unsigned NumRegs = 0; 657 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 658 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6) 659 return false; 660 return true; 661}]>; 662 663def X86tcret_1reg : PatFrag<(ops node:$ptr, node:$off), 664 (X86tcret node:$ptr, node:$off), [{ 665 // X86tcret args: (*chain, ptr, imm, regs..., glue) 666 unsigned NumRegs = 1; 667 const SDValue& BasePtr = cast<LoadSDNode>(N->getOperand(1))->getBasePtr(); 668 if (isa<FrameIndexSDNode>(BasePtr)) 669 NumRegs = 3; 670 else if (BasePtr->getNumOperands() && isa<GlobalAddressSDNode>(BasePtr->getOperand(0))) 671 NumRegs = 3; 672 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i) 673 if (isa<RegisterSDNode>(N->getOperand(i)) && ( NumRegs-- == 0)) 674 return false; 675 return true; 676}]>; 677 678// If this is an anyext of the remainder of an 8-bit sdivrem, use a MOVSX 679// instead of a MOVZX. The sdivrem lowering will emit emit a MOVSX to move 680// %ah to the lower byte of a register. By using a MOVSX here we allow a 681// post-isel peephole to merge the two MOVSX instructions into one. 682def anyext_sdiv : PatFrag<(ops node:$lhs), (anyext node:$lhs),[{ 683 return (N->getOperand(0).getOpcode() == ISD::SDIVREM && 684 N->getOperand(0).getResNo() == 1); 685}]>; 686 687// Any instruction that defines a 32-bit result leaves the high half of the 688// register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may 689// be copying from a truncate. AssertSext/AssertZext/AssertAlign aren't saying 690// anything about the upper 32 bits, they're probably just qualifying a 691// CopyFromReg. FREEZE may be coming from a a truncate. Any other 32-bit 692// operation will zero-extend up to 64 bits. 693def def32 : PatLeaf<(i32 GR32:$src), [{ 694 return N->getOpcode() != ISD::TRUNCATE && 695 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG && 696 N->getOpcode() != ISD::CopyFromReg && 697 N->getOpcode() != ISD::AssertSext && 698 N->getOpcode() != ISD::AssertZext && 699 N->getOpcode() != ISD::AssertAlign && 700 N->getOpcode() != ISD::FREEZE; 701}]>; 702 703// Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero. 704def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{ 705 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) 706 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); 707 708 KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0); 709 KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0); 710 return (~Known0.Zero & ~Known1.Zero) == 0; 711}]>; 712 713def shiftMask8 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 714 return isUnneededShiftMask(N, 3); 715}]>; 716 717def shiftMask16 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 718 return isUnneededShiftMask(N, 4); 719}]>; 720 721def shiftMask32 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 722 return isUnneededShiftMask(N, 5); 723}]>; 724 725def shiftMask64 : PatFrag<(ops node:$lhs), (and node:$lhs, imm), [{ 726 return isUnneededShiftMask(N, 6); 727}]>; 728 729//===----------------------------------------------------------------------===// 730// Pattern fragments to auto generate BMI instructions. 731//===----------------------------------------------------------------------===// 732 733def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 734 (X86or_flag node:$lhs, node:$rhs), [{ 735 return hasNoCarryFlagUses(SDValue(N, 1)); 736}]>; 737 738def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 739 (X86xor_flag node:$lhs, node:$rhs), [{ 740 return hasNoCarryFlagUses(SDValue(N, 1)); 741}]>; 742 743def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 744 (X86and_flag node:$lhs, node:$rhs), [{ 745 return hasNoCarryFlagUses(SDValue(N, 1)); 746}]>; 747 748//===----------------------------------------------------------------------===// 749// FPStack specific DAG Nodes. 750//===----------------------------------------------------------------------===// 751 752def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>, 753 SDTCisPtrTy<1>]>; 754def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>, 755 SDTCisPtrTy<1>]>; 756def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 757def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>; 758 759def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 760def SDTX86CwdLoad : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 761def SDTX86FPEnv : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 762 763def X86fp80_add : SDNode<"X86ISD::FP80_ADD", SDTFPBinOp, [SDNPCommutative]>; 764def X86strict_fp80_add : SDNode<"X86ISD::STRICT_FP80_ADD", SDTFPBinOp, 765 [SDNPHasChain,SDNPCommutative]>; 766def any_X86fp80_add : PatFrags<(ops node:$lhs, node:$rhs), 767 [(X86strict_fp80_add node:$lhs, node:$rhs), 768 (X86fp80_add node:$lhs, node:$rhs)]>; 769 770def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld, 771 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 772def X86fst : SDNode<"X86ISD::FST", SDTX86Fst, 773 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 774def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild, 775 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 776def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist, 777 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 778def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst, 779 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 780def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore, 781 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 782 SDNPMemOperand]>; 783def X86fp_cwd_set16 : SDNode<"X86ISD::FLDCW16m", SDTX86CwdLoad, 784 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 785 SDNPMemOperand]>; 786def X86fpenv_get : SDNode<"X86ISD::FNSTENVm", SDTX86FPEnv, 787 [SDNPHasChain, SDNPMayStore, SDNPSideEffect, 788 SDNPMemOperand]>; 789def X86fpenv_set : SDNode<"X86ISD::FLDENVm", SDTX86FPEnv, 790 [SDNPHasChain, SDNPMayLoad, SDNPSideEffect, 791 SDNPMemOperand]>; 792 793def X86fstf32 : PatFrag<(ops node:$val, node:$ptr), 794 (X86fst node:$val, node:$ptr), [{ 795 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 796}]>; 797def X86fstf64 : PatFrag<(ops node:$val, node:$ptr), 798 (X86fst node:$val, node:$ptr), [{ 799 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 800}]>; 801def X86fstf80 : PatFrag<(ops node:$val, node:$ptr), 802 (X86fst node:$val, node:$ptr), [{ 803 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 804}]>; 805 806def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 807 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32; 808}]>; 809def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 810 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64; 811}]>; 812def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{ 813 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80; 814}]>; 815 816def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 817 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 818}]>; 819def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 820 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 821}]>; 822def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{ 823 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 824}]>; 825 826def X86fist32 : PatFrag<(ops node:$val, node:$ptr), 827 (X86fist node:$val, node:$ptr), [{ 828 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 829}]>; 830 831def X86fist64 : PatFrag<(ops node:$val, node:$ptr), 832 (X86fist node:$val, node:$ptr), [{ 833 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 834}]>; 835 836def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr), 837 (X86fp_to_mem node:$val, node:$ptr), [{ 838 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16; 839}]>; 840def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr), 841 (X86fp_to_mem node:$val, node:$ptr), [{ 842 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32; 843}]>; 844def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr), 845 (X86fp_to_mem node:$val, node:$ptr), [{ 846 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64; 847}]>; 848 849//===----------------------------------------------------------------------===// 850// FPStack pattern fragments 851//===----------------------------------------------------------------------===// 852 853def fpimm0 : FPImmLeaf<fAny, [{ 854 return Imm.isExactlyValue(+0.0); 855}]>; 856 857def fpimmneg0 : FPImmLeaf<fAny, [{ 858 return Imm.isExactlyValue(-0.0); 859}]>; 860 861def fpimm1 : FPImmLeaf<fAny, [{ 862 return Imm.isExactlyValue(+1.0); 863}]>; 864 865def fpimmneg1 : FPImmLeaf<fAny, [{ 866 return Imm.isExactlyValue(-1.0); 867}]>; 868