1//===-- X86InstrConditionalCompare.td - Conditional Compare --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 conditional compare instructions. 10// 11//===----------------------------------------------------------------------===// 12 13class BinCondOp<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2, string m> 14 : ITy<o, f, t, (outs), (ins op1:$src1, op2:$src2, cflags:$dcf, ccode:$cond), 15 m#"${cond}", "$dcf\t{$src2, $src1|$src1, $src2}" , []>, T_MAP4, EVEX, Requires<[In64BitMode]> { 16 let isCodeGenOnly = 1; 17 let ForceDisassemble = 1; 18 let Uses = [EFLAGS]; 19 let Defs = [EFLAGS]; 20 let hasTwoConditionalOps = 1; 21 let ImmT = !if(!eq(op2, i16i8imm), Imm8, 22 !if(!eq(op2, i32i8imm), Imm8, 23 !if(!eq(op2, i64i8imm), Imm8, 24 !if(!eq(op2, i8imm), Imm8, 25 !if(!eq(op2, i16imm), Imm16, 26 !if(!eq(op2, i32imm), Imm32, 27 !if(!eq(op2, i64i32imm), Imm32S, NoImm))))))); 28} 29 30class Ccmp<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>: 31 BinCondOp<o, f, t, op1, op2, "ccmp">; 32 33class Ctest<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>: 34 BinCondOp<o, f, t, op1, op2, "ctest">; 35 36//===----------------------------------------------------------------------===// 37// CCMP Instructions 38// 39let SchedRW = [WriteALU] in { 40 def CCMP8rr : Ccmp<0x38, MRMDestReg, Xi8, GR8, GR8>; 41 def CCMP16rr: Ccmp<0x39, MRMDestReg, Xi16, GR16, GR16>, PD; 42 def CCMP32rr: Ccmp<0x39, MRMDestReg, Xi32, GR32, GR32>; 43 def CCMP64rr: Ccmp<0x39, MRMDestReg, Xi64, GR64, GR64>; 44 def CCMP8rr_REV : Ccmp<0x3a, MRMSrcReg, Xi8, GR8, GR8>; 45 def CCMP16rr_REV: Ccmp<0x3b, MRMSrcReg, Xi16, GR16, GR16>, PD; 46 def CCMP32rr_REV: Ccmp<0x3b, MRMSrcReg, Xi32, GR32, GR32>; 47 def CCMP64rr_REV: Ccmp<0x3b, MRMSrcReg, Xi64, GR64, GR64>; 48 def CCMP16ri8: Ccmp<0x83, MRM7r, Xi16, GR16, i16i8imm>, PD; 49 def CCMP32ri8: Ccmp<0x83, MRM7r, Xi32, GR32, i32i8imm>; 50 def CCMP64ri8: Ccmp<0x83, MRM7r, Xi64, GR64, i64i8imm>; 51 52 def CCMP8ri : Ccmp<0x80, MRM7r, Xi8, GR8, i8imm>; 53 def CCMP16ri: Ccmp<0x81, MRM7r, Xi16, GR16, i16imm>, PD; 54 def CCMP32ri: Ccmp<0x81, MRM7r, Xi32, GR32, i32imm>; 55 def CCMP64ri32: Ccmp<0x81, MRM7r, Xi64, GR64, i64i32imm>; 56} 57 58let mayLoad = 1 in { 59 let SchedRW = [WriteALU.Folded] in { 60 def CCMP16mi8: Ccmp<0x83, MRM7m, Xi16, i16mem, i16i8imm>, PD; 61 def CCMP32mi8: Ccmp<0x83, MRM7m, Xi32, i32mem, i32i8imm>; 62 def CCMP64mi8: Ccmp<0x83, MRM7m, Xi64, i64mem, i64i8imm>; 63 def CCMP8mi : Ccmp<0x80, MRM7m, Xi8, i8mem, i8imm>; 64 def CCMP16mi: Ccmp<0x81, MRM7m, Xi16, i16mem, i16imm>, PD; 65 def CCMP32mi: Ccmp<0x81, MRM7m, Xi32, i32mem, i32imm>; 66 def CCMP64mi32: Ccmp<0x81, MRM7m, Xi64, i64mem, i64i32imm>; 67 } 68 let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold] in { 69 def CCMP8rm : Ccmp<0x3a, MRMSrcMem, Xi8, GR8, i8mem>; 70 def CCMP16rm: Ccmp<0x3b, MRMSrcMem, Xi16, GR16, i16mem>, PD; 71 def CCMP32rm: Ccmp<0x3b, MRMSrcMem, Xi32, GR32, i32mem>; 72 def CCMP64rm: Ccmp<0x3b, MRMSrcMem, Xi64, GR64, i64mem>; 73 74 def CCMP8mr : Ccmp<0x38, MRMDestMem, Xi8, i8mem, GR8>; 75 def CCMP16mr: Ccmp<0x39, MRMDestMem, Xi16, i16mem, GR16>, PD; 76 def CCMP32mr: Ccmp<0x39, MRMDestMem, Xi32, i32mem, GR32>; 77 def CCMP64mr: Ccmp<0x39, MRMDestMem, Xi64, i64mem, GR64>; 78 } 79} 80 81def : Pat<(X86ccmp GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond, EFLAGS), 82 (CCMP8rr GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond)>; 83def : Pat<(X86ccmp GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond, EFLAGS), 84 (CCMP16rr GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond)>; 85def : Pat<(X86ccmp GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond, EFLAGS), 86 (CCMP32rr GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond)>; 87def : Pat<(X86ccmp GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond, EFLAGS), 88 (CCMP64rr GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond)>; 89 90def : Pat<(X86ccmp GR8:$src1, (i8 imm:$src2), timm:$dcf, timm:$cond, EFLAGS), 91 (CCMP8ri GR8:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 92def : Pat<(X86ccmp GR16:$src1, (i16 imm:$src2), timm:$dcf, timm:$cond, EFLAGS), 93 (CCMP16ri GR16:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 94def : Pat<(X86ccmp GR32:$src1, (i32 imm:$src2), timm:$dcf, timm:$cond, EFLAGS), 95 (CCMP32ri GR32:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 96def : Pat<(X86ccmp GR64:$src1, i64immSExt32_su:$src2, timm:$dcf, timm:$cond, EFLAGS), 97 (CCMP64ri32 GR64:$src1, i64immSExt32_su:$src2, timm:$dcf, timm:$cond)>; 98 99def : Pat<(X86ccmp GR8:$src1, (loadi8 addr:$src2), timm:$dcf, timm:$cond, EFLAGS), 100 (CCMP8rm GR8:$src1, addr:$src2, timm:$dcf, timm:$cond)>; 101def : Pat<(X86ccmp GR16:$src1, (loadi16 addr:$src2), timm:$dcf, timm:$cond, EFLAGS), 102 (CCMP16rm GR16:$src1, addr:$src2, timm:$dcf, timm:$cond)>; 103def : Pat<(X86ccmp GR32:$src1, (loadi32 addr:$src2), timm:$dcf, timm:$cond, EFLAGS), 104 (CCMP32rm GR32:$src1, addr:$src2, timm:$dcf, timm:$cond)>; 105def : Pat<(X86ccmp GR64:$src1, (loadi64 addr:$src2), timm:$dcf, timm:$cond, EFLAGS), 106 (CCMP64rm GR64:$src1, addr:$src2, timm:$dcf, timm:$cond)>; 107 108 109//===----------------------------------------------------------------------===// 110// CTEST Instructions 111// 112let SchedRW = [WriteALU] in { 113 let isCommutable = 1 in { 114 def CTEST8rr : Ctest<0x84, MRMDestReg, Xi8, GR8, GR8>; 115 def CTEST16rr: Ctest<0x85, MRMDestReg, Xi16, GR16, GR16>, PD; 116 def CTEST32rr: Ctest<0x85, MRMDestReg, Xi32, GR32, GR32>; 117 def CTEST64rr: Ctest<0x85, MRMDestReg, Xi64, GR64, GR64>; 118 } 119 def CTEST8ri : Ctest<0xF6, MRM0r, Xi8, GR8, i8imm>; 120 def CTEST16ri: Ctest<0xF7, MRM0r, Xi16, GR16, i16imm>, PD; 121 def CTEST32ri: Ctest<0xF7, MRM0r, Xi32, GR32, i32imm>; 122 def CTEST64ri32: Ctest<0xF7, MRM0r, Xi64, GR64, i64i32imm>; 123} 124 125let mayLoad = 1 in { 126 let SchedRW = [WriteALU.Folded] in { 127 def CTEST8mi : Ctest<0xF6, MRM0m, Xi8, i8mem, i8imm>; 128 def CTEST16mi: Ctest<0xF7, MRM0m, Xi16, i16mem, i16imm>, PD; 129 def CTEST32mi: Ctest<0xF7, MRM0m, Xi32, i32mem, i32imm>; 130 def CTEST64mi32: Ctest<0xF7, MRM0m, Xi64, i64mem, i64i32imm>; 131 } 132 let SchedRW = [WriteALU.Folded, WriteALU.ReadAfterFold] in { 133 def CTEST8mr : Ctest<0x84, MRMDestMem, Xi8, i8mem, GR8>; 134 def CTEST16mr: Ctest<0x85, MRMDestMem, Xi16, i16mem, GR16>, PD; 135 def CTEST32mr: Ctest<0x85, MRMDestMem, Xi32, i32mem, GR32>; 136 def CTEST64mr: Ctest<0x85, MRMDestMem, Xi64, i64mem, GR64>; 137 } 138} 139 140def : Pat<(X86ctest GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond, EFLAGS), 141 (CTEST8rr GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond)>; 142def : Pat<(X86ctest GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond, EFLAGS), 143 (CTEST16rr GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond)>; 144def : Pat<(X86ctest GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond, EFLAGS), 145 (CTEST32rr GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond)>; 146def : Pat<(X86ctest GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond, EFLAGS), 147 (CTEST64rr GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond)>; 148 149def : Pat<(X86ctestpat GR8:$src1, imm:$src2, timm:$dcf, timm:$cond), 150 (CTEST8ri GR8:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 151def : Pat<(X86ctestpat GR16:$src1, imm:$src2, timm:$dcf, timm:$cond), 152 (CTEST16ri GR16:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 153def : Pat<(X86ctestpat GR32:$src1, imm:$src2, timm:$dcf, timm:$cond), 154 (CTEST32ri GR32:$src1, imm:$src2, timm:$dcf, timm:$cond)>; 155def : Pat<(X86ctestpat GR64:$src1, i64immSExt32_su:$src2, timm:$dcf, timm:$cond), 156 (CTEST64ri32 GR64:$src1, i64immSExt32_su:$src2, timm:$dcf, timm:$cond)>; 157