1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern, 10 InstrItinClass itin = NoItinerary> 11 : Instruction { 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15 let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19 20 dag OutOperandList = outs; 21 dag InOperandList = ins; 22 let AsmString = asmstr; 23 let Pattern = pattern; 24 25 let DecoderNamespace = "Sparc"; 26 field bits<32> SoftFail = 0; 27 28 let Itinerary = itin; 29} 30 31//===----------------------------------------------------------------------===// 32// Format #2 instruction classes in the Sparc 33//===----------------------------------------------------------------------===// 34 35// Format 2 instructions 36class F2<dag outs, dag ins, string asmstr, list<dag> pattern, 37 InstrItinClass itin = NoItinerary> 38 : InstSP<outs, ins, asmstr, pattern, itin> { 39 bits<3> op2; 40 bits<22> imm22; 41 let op = 0; // op = 0 42 let Inst{24-22} = op2; 43 let Inst{21-0} = imm22; 44} 45 46// Specific F2 classes: SparcV8 manual, page 44 47// 48class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern, 49 InstrItinClass itin = NoItinerary> 50 : F2<outs, ins, asmstr, pattern, itin> { 51 bits<5> rd; 52 53 let op2 = op2Val; 54 55 let Inst{29-25} = rd; 56} 57 58class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 59 list<dag> pattern, InstrItinClass itin = NoItinerary> 60 : F2<outs, ins, asmstr, pattern, itin> { 61 bits<4> cond; 62 let op2 = op2Val; 63 64 let Inst{29} = annul; 65 let Inst{28-25} = cond; 66} 67 68class F2_3<bits<3> op2Val, bit annul, bit pred, 69 dag outs, dag ins, string asmstr, list<dag> pattern, 70 InstrItinClass itin = NoItinerary> 71 : InstSP<outs, ins, asmstr, pattern, itin> { 72 bits<2> cc; 73 bits<4> cond; 74 bits<19> imm19; 75 76 let op = 0; // op = 0 77 78 let Inst{29} = annul; 79 let Inst{28-25} = cond; 80 let Inst{24-22} = op2Val; 81 let Inst{21-20} = cc; 82 let Inst{19} = pred; 83 let Inst{18-0} = imm19; 84} 85 86class F2_4<bit annul, bit pred, dag outs, dag ins, 87 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 88 : InstSP<outs, ins, asmstr, pattern, itin> { 89 bits<16> imm16; 90 bits<5> rs1; 91 bits<3> rcond; 92 93 let op = 0; // op = 0 94 95 let Inst{29} = annul; 96 let Inst{28} = 0; 97 let Inst{27-25} = rcond; 98 let Inst{24-22} = 0b011; 99 let Inst{21-20} = imm16{15-14}; 100 let Inst{19} = pred; 101 let Inst{18-14} = rs1; 102 let Inst{13-0} = imm16{13-0}; 103} 104 105class F2_5<bit cc, dag outs, dag ins, string asmstr, 106 list<dag> pattern = [], InstrItinClass itin = NoItinerary> 107 : InstSP<outs, ins, asmstr, pattern, itin> { 108 bits<10> imm10; 109 bits<5> rs1; 110 bits<5> rs2; 111 bits<4> cond; 112 113 let op = 0; // op = 0 114 115 let Inst{29} = cond{3}; 116 let Inst{28} = 1; 117 let Inst{27-25} = cond{2-0}; 118 let Inst{24-22} = 0b011; 119 let Inst{21} = cc; 120 let Inst{20-19} = imm10{9-8}; 121 let Inst{18-14} = rs1; 122 let Inst{13} = 0; // i = 0 123 let Inst{12-5} = imm10{7-0}; 124 let Inst{4-0} = rs2; 125} 126 127class F2_6<bit cc, dag outs, dag ins, string asmstr, 128 list<dag> pattern = [], InstrItinClass itin = NoItinerary> 129 : InstSP<outs, ins, asmstr, pattern, itin> { 130 bits<10> imm10; 131 bits<5> rs1; 132 bits<5> simm5; 133 bits<4> cond; 134 135 let op = 0; // op = 0 136 137 let Inst{29} = cond{3}; 138 let Inst{28} = 1; 139 let Inst{27-25} = cond{2-0}; 140 let Inst{24-22} = 0b011; 141 let Inst{21} = cc; 142 let Inst{20-19} = imm10{9-8}; 143 let Inst{18-14} = rs1; 144 let Inst{13} = 1; // i = 1 145 let Inst{12-5} = imm10{7-0}; 146 let Inst{4-0} = simm5; 147} 148 149//===----------------------------------------------------------------------===// 150// Format #3 instruction classes in the Sparc 151//===----------------------------------------------------------------------===// 152 153class F3<dag outs, dag ins, string asmstr, list<dag> pattern, 154 InstrItinClass itin = NoItinerary> 155 : InstSP<outs, ins, asmstr, pattern, itin> { 156 bits<5> rd; 157 bits<6> op3; 158 bits<5> rs1; 159 let op{1} = 1; // Op = 2 or 3 160 let Inst{29-25} = rd; 161 let Inst{24-19} = op3; 162 let Inst{18-14} = rs1; 163} 164 165// Specific F3 classes: SparcV8 manual, page 44 166// 167class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 168 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 169 : F3<outs, ins, asmstr, pattern, itin> { 170 bits<8> asi; 171 bits<5> rs2; 172 173 let op = opVal; 174 let op3 = op3val; 175 176 let Inst{13} = 0; // i field = 0 177 let Inst{12-5} = asi; // address space identifier 178 let Inst{4-0} = rs2; 179} 180 181// CAS instructions does not use an immediate even when i=1 182class F3_1_cas_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 183 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 184 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 185 let asi = 0; 186 let Inst{13} = 1; // i field = 1 187} 188 189class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 190 list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 191 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 192 let asi = 0; 193} 194 195class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 196 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 197 : F3<outs, ins, asmstr, pattern, itin> { 198 bits<13> simm13; 199 200 let op = opVal; 201 let op3 = op3val; 202 203 let Inst{13} = 1; // i field = 1 204 let Inst{12-0} = simm13; 205} 206 207// floating-point 208class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 209 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 210 : F3<outs, ins, asmstr, pattern, itin> { 211 bits<5> rs2; 212 213 let op = opVal; 214 let op3 = op3val; 215 216 let Inst{13-5} = opfval; // fp opcode 217 let Inst{4-0} = rs2; 218} 219 220// floating-point unary operations. 221class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 222 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 223 : F3<outs, ins, asmstr, pattern, itin> { 224 bits<5> rs2; 225 226 let op = opVal; 227 let op3 = op3val; 228 let rs1 = 0; 229 230 let Inst{13-5} = opfval; // fp opcode 231 let Inst{4-0} = rs2; 232} 233 234// floating-point compares. 235class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 236 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 237 : F3<outs, ins, asmstr, pattern, itin> { 238 bits<5> rs2; 239 240 let op = opVal; 241 let op3 = op3val; 242 243 let Inst{13-5} = opfval; // fp opcode 244 let Inst{4-0} = rs2; 245} 246 247// SIAM instruction 248class F3_3_siam<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 249 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 250 : F3<outs, ins, asmstr, pattern, itin> { 251 bits<3> mode; 252 253 let op = opVal; 254 let op3 = op3val; 255 let rd = 0; 256 let rs1 = 0; 257 let Inst{13-5} = opfval; // fp opcode 258 let Inst{4-3} = 0; 259 let Inst{2-0} = mode; 260} 261 262// Shift by register rs2. 263class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 264 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 265 : F3<outs, ins, asmstr, pattern, itin> { 266 bit x = xVal; // 1 for 64-bit shifts. 267 bits<5> rs2; 268 269 let op = opVal; 270 let op3 = op3val; 271 272 let Inst{13} = 0; // i field = 0 273 let Inst{12} = x; // extended registers. 274 let Inst{4-0} = rs2; 275} 276 277// Shift by immediate. 278class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 279 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 280 : F3<outs, ins, asmstr, pattern, itin> { 281 bit x = xVal; // 1 for 64-bit shifts. 282 bits<6> shcnt; // shcnt32 / shcnt64. 283 284 let op = opVal; 285 let op3 = op3val; 286 287 let Inst{13} = 1; // i field = 1 288 let Inst{12} = x; // extended registers. 289 let Inst{5-0} = shcnt; 290} 291 292// Define rr and ri shift instructions with patterns. 293multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 294 ValueType VT, Operand SIT, RegisterClass RC, 295 InstrItinClass itin = IIC_iu_instr> { 296 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 297 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 298 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 299 itin>; 300 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, SIT:$shcnt), 301 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 302 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], 303 itin>; 304} 305 306// 4-operand instructions. 307class F3_4<bits<6> op3val, bits<4> op5val, dag outs, dag ins, 308 string asmstr, list<dag> pattern = [], InstrItinClass itin = NoItinerary> 309 : F3<outs, ins, asmstr, pattern, itin> { 310 bits<4> op5; 311 bits<5> rs3; 312 bits<5> rs2; 313 314 let op = 2; 315 let op3 = op3val; 316 let op5 = op5val; 317 318 let Inst{13-9} = rs3; 319 let Inst{8-5} = op5; 320 let Inst{4-0} = rs2; 321} 322 323class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern, 324 InstrItinClass itin = NoItinerary> 325 : InstSP<outs, ins, asmstr, pattern, itin> { 326 bits<5> rd; 327 328 let op = 2; 329 let Inst{29-25} = rd; 330 let Inst{24-19} = op3; 331} 332 333 334class F4_1<bits<6> op3, dag outs, dag ins, 335 string asmstr, list<dag> pattern, 336 InstrItinClass itin = NoItinerary> 337 : F4<op3, outs, ins, asmstr, pattern, itin> { 338 bit intcc; 339 bits<2> cc; 340 bits<4> cond; 341 bits<5> rs2; 342 343 let Inst{4-0} = rs2; 344 let Inst{12-11} = cc; 345 let Inst{13} = 0; 346 let Inst{17-14} = cond; 347 let Inst{18} = intcc; 348} 349 350class F4_2<bits<6> op3, dag outs, dag ins, 351 string asmstr, list<dag> pattern, 352 InstrItinClass itin = NoItinerary> 353 : F4<op3, outs, ins, asmstr, pattern, itin> { 354 bit intcc; 355 bits<2> cc; 356 bits<4> cond; 357 bits<11> simm11; 358 359 let Inst{10-0} = simm11; 360 let Inst{12-11} = cc; 361 let Inst{13} = 1; 362 let Inst{17-14} = cond; 363 let Inst{18} = intcc; 364} 365 366class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 367 string asmstr, list<dag> pattern, 368 InstrItinClass itin = NoItinerary> 369 : F4<op3, outs, ins, asmstr, pattern, itin> { 370 bits<4> cond; 371 bit intcc; 372 bits<2> opf_cc; 373 bits<5> rs2; 374 375 let Inst{18} = 0; 376 let Inst{17-14} = cond; 377 let Inst{13} = intcc; 378 let Inst{12-11} = opf_cc; 379 let Inst{10-5} = opf_low; 380 let Inst{4-0} = rs2; 381} 382 383class F4_4r<bits<6> op3, bits<5> opf_low, dag outs, dag ins, 384 string asmstr, list<dag> pattern, 385 InstrItinClass itin = NoItinerary> 386 : F4<op3, outs, ins, asmstr, pattern, itin> { 387 bits<5> rs1; 388 bits<5> rs2; 389 bits<3> rcond; 390 let Inst{18-14} = rs1; 391 let Inst{13} = 0; // IsImm 392 let Inst{12-10} = rcond; 393 let Inst{9-5} = opf_low; 394 let Inst{4-0} = rs2; 395} 396 397 398class F4_4i<bits<6> op3, dag outs, dag ins, 399 string asmstr, list<dag> pattern, 400 InstrItinClass itin = NoItinerary> 401 : F4<op3, outs, ins, asmstr, pattern, itin> { 402 bits<5> rs1; 403 bits<10> simm10; 404 bits<3> rcond; 405 let Inst{18-14} = rs1; 406 let Inst{13} = 1; // IsImm 407 let Inst{12-10} = rcond; 408 let Inst{9-0} = simm10; 409} 410 411 412class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, 413 string asmstr, list<dag> pattern, 414 InstrItinClass itin = NoItinerary> 415 : F3<outs, ins, asmstr, pattern, itin> { 416 bits<4> cond; 417 bits<2> cc; 418 419 let op = 0b10; 420 let rd{4} = 0; 421 let rd{3-0} = cond; 422 let op3 = op3Val; 423 let Inst{13} = isimm; 424 let Inst{12-11} = cc; 425 426} 427 428class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, 429 string asmstr, list<dag> pattern, 430 InstrItinClass itin = NoItinerary> 431 : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> { 432 bits<5> rs2; 433 434 let Inst{10-5} = 0; 435 let Inst{4-0} = rs2; 436} 437 438class TRAPSPri<bits<6> op3Val, dag outs, dag ins, 439 string asmstr, list<dag> pattern, 440 InstrItinClass itin = NoItinerary> 441 : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> { 442 bits<8> imm; 443 444 let Inst{10-8} = 0; 445 let Inst{7-0} = imm; 446} 447 448// Pseudo-instructions for alternate assembly syntax (never used by codegen). 449// These are aliases that require C++ handling to convert to the target 450// instruction, while InstAliases can be handled directly by tblgen. 451class AsmPseudoInst<dag outs, dag ins, string asm> 452 : InstSP<outs, ins, asm, []> { 453 let isPseudo = 1; 454} 455