1 //===- RegisterClassInfo.h - Dynamic Register Class Info --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RegisterClassInfo class which provides dynamic 10 // information about target register classes. Callee saved and reserved 11 // registers depends on calling conventions and other dynamic information, so 12 // some things cannot be determined statically. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H 17 #define LLVM_CODEGEN_REGISTERCLASSINFO_H 18 19 #include "llvm/ADT/ArrayRef.h" 20 #include "llvm/ADT/BitVector.h" 21 #include "llvm/ADT/SmallVector.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/MC/MCRegister.h" 24 #include "llvm/Support/Compiler.h" 25 #include <cstdint> 26 #include <memory> 27 28 namespace llvm { 29 30 class RegisterClassInfo { 31 struct RCInfo { 32 unsigned Tag = 0; 33 unsigned NumRegs = 0; 34 bool ProperSubClass = false; 35 uint8_t MinCost = 0; 36 uint16_t LastCostChange = 0; 37 std::unique_ptr<MCPhysReg[]> Order; 38 39 RCInfo() = default; 40 41 operator ArrayRef<MCPhysReg>() const { 42 return ArrayRef(Order.get(), NumRegs); 43 } 44 }; 45 46 // Brief cached information for each register class. 47 std::unique_ptr<RCInfo[]> RegClass; 48 49 // Tag changes whenever cached information needs to be recomputed. An RCInfo 50 // entry is valid when its tag matches. 51 unsigned Tag = 0; 52 53 bool Reverse = false; 54 55 const MachineFunction *MF = nullptr; 56 const TargetRegisterInfo *TRI = nullptr; 57 58 // Callee saved registers of last MF. 59 // Used only to determine if an update for CalleeSavedAliases is necessary. 60 SmallVector<MCPhysReg, 16> LastCalleeSavedRegs; 61 62 // Map regunit to the callee saved Register. 63 SmallVector<MCPhysReg> CalleeSavedAliases; 64 65 // Indicate if a specified callee saved register be in the allocation order 66 // exactly as written in the tablegen descriptions or listed later. 67 BitVector IgnoreCSRForAllocOrder; 68 69 // Reserved registers in the current MF. 70 BitVector Reserved; 71 72 std::unique_ptr<unsigned[]> PSetLimits; 73 74 // The register cost values. 75 ArrayRef<uint8_t> RegCosts; 76 77 // Compute all information about RC. 78 LLVM_ABI void compute(const TargetRegisterClass *RC) const; 79 80 // Return an up-to-date RCInfo for RC. get(const TargetRegisterClass * RC)81 const RCInfo &get(const TargetRegisterClass *RC) const { 82 const RCInfo &RCI = RegClass[RC->getID()]; 83 if (Tag != RCI.Tag) 84 compute(RC); 85 return RCI; 86 } 87 88 public: 89 LLVM_ABI RegisterClassInfo(); 90 91 /// runOnFunction - Prepare to answer questions about MF. Rev indicates to 92 /// use reversed raw order when compute register order. This must be called 93 /// before any other methods are used. 94 LLVM_ABI void runOnMachineFunction(const MachineFunction &MF, 95 bool Rev = false); 96 97 /// getNumAllocatableRegs - Returns the number of actually allocatable 98 /// registers in RC in the current function. getNumAllocatableRegs(const TargetRegisterClass * RC)99 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 100 return get(RC).NumRegs; 101 } 102 103 /// getOrder - Returns the preferred allocation order for RC. The order 104 /// contains no reserved registers, and registers that alias callee saved 105 /// registers come last. getOrder(const TargetRegisterClass * RC)106 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { 107 return get(RC); 108 } 109 110 /// isProperSubClass - Returns true if RC has a legal super-class with more 111 /// allocatable registers. 112 /// 113 /// Register classes like GR32_NOSP are not proper sub-classes because %esp 114 /// is not allocatable. Similarly, tGPR is not a proper sub-class in Thumb 115 /// mode because the GPR super-class is not legal. isProperSubClass(const TargetRegisterClass * RC)116 bool isProperSubClass(const TargetRegisterClass *RC) const { 117 return get(RC).ProperSubClass; 118 } 119 120 /// getLastCalleeSavedAlias - Returns the last callee saved register that 121 /// overlaps PhysReg, or NoRegister if PhysReg doesn't overlap a 122 /// CalleeSavedAliases. getLastCalleeSavedAlias(MCRegister PhysReg)123 MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const { 124 MCRegister CSR; 125 for (MCRegUnit Unit : TRI->regunits(PhysReg)) { 126 CSR = CalleeSavedAliases[Unit]; 127 if (CSR) 128 break; 129 } 130 return CSR; 131 } 132 133 /// Get the minimum register cost in RC's allocation order. 134 /// This is the smallest value in RegCosts[Reg] for all 135 /// the registers in getOrder(RC). getMinCost(const TargetRegisterClass * RC)136 uint8_t getMinCost(const TargetRegisterClass *RC) const { 137 return get(RC).MinCost; 138 } 139 140 /// Get the position of the last cost change in getOrder(RC). 141 /// 142 /// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the 143 /// same cost according to RegCosts[Reg]. getLastCostChange(const TargetRegisterClass * RC)144 unsigned getLastCostChange(const TargetRegisterClass *RC) const { 145 return get(RC).LastCostChange; 146 } 147 148 /// Get the register unit limit for the given pressure set index. 149 /// 150 /// RegisterClassInfo adjusts this limit for reserved registers. getRegPressureSetLimit(unsigned Idx)151 unsigned getRegPressureSetLimit(unsigned Idx) const { 152 if (!PSetLimits[Idx]) 153 PSetLimits[Idx] = computePSetLimit(Idx); 154 return PSetLimits[Idx]; 155 } 156 157 protected: 158 LLVM_ABI unsigned computePSetLimit(unsigned Idx) const; 159 }; 160 161 } // end namespace llvm 162 163 #endif // LLVM_CODEGEN_REGISTERCLASSINFO_H 164