xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSystemOperands.td (revision 700637cbb5e582861067a11aaca4d053546871d2) 
1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the symbolic operands permitted for various kinds of
10// RISC-V system instruction.
11//
12//===----------------------------------------------------------------------===//
13
14include "llvm/TableGen/SearchableTable.td"
15
16//===----------------------------------------------------------------------===//
17// CSR (control and status register read/write) instruction options.
18//===----------------------------------------------------------------------===//
19
20class SysReg<string name, bits<12> op> {
21  string Name = name;
22  // Custom vendor CSRs have a "<vendor>." prefix. Convert these to "<vendor>_"
23  // before passing it to the SysRegEncodings GenericEnum below.
24  string EnumName = !subst(".", "_", name);
25  bits<12> Encoding = op;
26  // FIXME: add these additional fields when needed.
27  // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3.
28  // Privilege Mode: User = 0, System = 1 or Machine = 3.
29  // bits<2> ReadWrite = op{11 - 10};
30  // bits<2> XMode = op{9 - 8};
31  // Check Extra field name and what bits 7-6 correspond to.
32  // bits<2> Extra = op{7 - 6};
33  // Register number without the privilege bits.
34  // bits<6> Number = op{5 - 0};
35  code FeaturesRequired = [{ {} }];
36  bit isRV32Only = 0;
37  bit isAltName = 0;
38  bit isDeprecatedName = 0;
39}
40
41def SysRegsList : GenericTable {
42  let FilterClass = "SysReg";
43  // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed.
44  let Fields = [
45    "Name", "Encoding", "FeaturesRequired",
46    "isRV32Only", "isAltName", "isDeprecatedName"
47  ];
48
49  let PrimaryKey = [ "Encoding" ];
50  let PrimaryKeyName = "lookupSysRegByEncoding";
51  let PrimaryKeyReturnRange = true;
52}
53
54def SysRegEncodings : GenericEnum {
55  let FilterClass = "SysReg";
56  let NameField = "EnumName";
57  let ValueField = "Encoding";
58}
59
60def lookupSysRegByName : SearchIndex {
61  let Table = SysRegsList;
62  let Key = [ "Name" ];
63}
64
65// The following CSR encodings match those given in Tables 2.2,
66// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
67// Volume II: Privileged Architecture.
68
69//===----------------------------------------------------------------------===//
70// Unprivileged Floating-Point CSRs
71//===----------------------------------------------------------------------===//
72
73def SysRegFFLAGS : SysReg<"fflags", 0x001>;
74def SysRegFRM    : SysReg<"frm", 0x002>;
75def SysRegFCSR   : SysReg<"fcsr", 0x003>;
76
77//===----------------------------------------------------------------------===//
78// Unprivileged Vector CSRs
79//===----------------------------------------------------------------------===//
80def : SysReg<"vstart", 0x008>;
81def : SysReg<"vxsat", 0x009>;
82def SysRegVXRM : SysReg<"vxrm", 0x00A>;
83def : SysReg<"vcsr", 0x00F>;
84def SysRegVL : SysReg<"vl", 0xC20>;
85def : SysReg<"vtype", 0xC21>;
86def SysRegVLENB: SysReg<"vlenb", 0xC22>;
87
88//===----------------------------------------------------------------------===//
89// Unprivileged Zicfiss extension CSR
90//===----------------------------------------------------------------------===//
91
92def : SysReg<"ssp", 0x011>;
93
94//===-----------------------------------------------
95// Unprivileged Entropy Source Extension CSR
96//===-----------------------------------------------
97
98def SEED : SysReg<"seed", 0x015>;
99
100//===-----------------------------------------------
101// Unprivileged Zcmt Extension CSR
102//===-----------------------------------------------
103
104def : SysReg<"jvt", 0x017>;
105
106//===----------------------------------------------------------------------===//
107// Unprivileged Counter/Timers
108//===----------------------------------------------------------------------===//
109
110def CYCLE   : SysReg<"cycle", 0xC00>;
111def TIME    : SysReg<"time", 0xC01>;
112def INSTRET : SysReg<"instret", 0xC02>;
113
114// hpmcounter3-hpmcounter31 at 0xC03-0xC1F.
115foreach i = 3...31 in
116  def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>;
117
118let isRV32Only = 1 in {
119def CYCLEH   : SysReg<"cycleh", 0xC80>;
120def TIMEH    : SysReg<"timeh", 0xC81>;
121def INSTRETH : SysReg<"instreth", 0xC82>;
122
123// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F.
124foreach i = 3...31 in
125  def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>;
126}
127
128//===----------------------------------------------------------------------===//
129// Supervisor Trap Setup
130//===----------------------------------------------------------------------===//
131
132def : SysReg<"sstatus", 0x100>;
133def : SysReg<"sie", 0x104>;
134def : SysReg<"stvec", 0x105>;
135def : SysReg<"scounteren", 0x106>;
136
137//===----------------------------------------------------------------------===//
138// Supervisor Configuration
139//===----------------------------------------------------------------------===//
140
141def : SysReg<"senvcfg", 0x10A>;
142
143//===----------------------------------------------------------------------===//
144// Supervisor Counter Setup
145//===----------------------------------------------------------------------===//
146
147def : SysReg<"scountinhibit", 0x120>;
148
149//===----------------------------------------------------------------------===//
150// Supervisor Trap Handling
151//===----------------------------------------------------------------------===//
152
153def : SysReg<"sscratch", 0x140>;
154def : SysReg<"sepc", 0x141>;
155def : SysReg<"scause", 0x142>;
156def : SysReg<"stval", 0x143>;
157let isDeprecatedName = 1 in
158def : SysReg<"sbadaddr", 0x143>;
159def : SysReg<"sip", 0x144>;
160def : SysReg<"scountovf", 0xDA0>;
161
162//===----------------------------------------------------------------------===//
163// Supervisor Protection and Translation
164//===----------------------------------------------------------------------===//
165
166def : SysReg<"satp", 0x180>;
167let isDeprecatedName = 1 in
168def : SysReg<"sptbr", 0x180>;
169
170//===----------------------------------------------------------------------===//
171// Supervisor Timer Compare
172//===----------------------------------------------------------------------===//
173
174def : SysReg<"stimecmp", 0x14D>;
175let isRV32Only = 1 in
176def : SysReg<"stimecmph", 0x15D>;
177
178//===----------------------------------------------------------------------===//
179// Debug/Trace Registers
180//===----------------------------------------------------------------------===//
181
182def : SysReg<"scontext", 0x5A8>;
183
184//===----------------------------------------------------------------------===//
185// Supervisor Resource Management Configuration
186//===----------------------------------------------------------------------===//
187
188def : SysReg<"srmcfg", 0x181>;
189
190//===----------------------------------------------------------------------===//
191// Supervisor State Enable
192//===----------------------------------------------------------------------===//
193
194foreach i = 0...3 in {
195  def : SysReg<"sstateen"#i, !add(0x10C, i)>;
196}
197
198//===----------------------------------------------------------------------===//
199// Hypervisor Trap Setup
200//===----------------------------------------------------------------------===//
201
202def : SysReg<"hstatus", 0x600>;
203def : SysReg<"hedeleg", 0x602>;
204def : SysReg<"hideleg", 0x603>;
205def : SysReg<"hie", 0x604>;
206def : SysReg<"hcounteren", 0x606>;
207def : SysReg<"hgeie", 0x607>;
208let isRV32Only = 1 in
209def : SysReg<"hedelegh", 0x612>;
210
211//===----------------------------------------------------------------------===//
212// Hypervisor Trap Handling
213//===----------------------------------------------------------------------===//
214
215def : SysReg<"htval", 0x643>;
216def : SysReg<"hip", 0x644>;
217def : SysReg<"hvip", 0x645>;
218def : SysReg<"htinst", 0x64A>;
219def : SysReg<"hgeip", 0xE12>;
220
221//===----------------------------------------------------------------------===//
222// Hypervisor Configuration
223//===----------------------------------------------------------------------===//
224
225def : SysReg<"henvcfg", 0x60A>;
226let isRV32Only = 1 in
227def : SysReg<"henvcfgh", 0x61A>;
228
229//===----------------------------------------------------------------------===//
230// Hypervisor Protection and Translation
231//===----------------------------------------------------------------------===//
232
233def : SysReg<"hgatp", 0x680>;
234
235//===----------------------------------------------------------------------===//
236// Debug/Trace Registers
237//===----------------------------------------------------------------------===//
238
239def : SysReg<"hcontext", 0x6A8>;
240
241//===----------------------------------------------------------------------===//
242// Hypervisor Counter/Timer Virtualization Registers
243//===----------------------------------------------------------------------===//
244
245def : SysReg<"htimedelta", 0x605>;
246let isRV32Only = 1 in
247def : SysReg<"htimedeltah", 0x615>;
248
249//===----------------------------------------------------------------------===//
250// Hypervisor State Enable Registers
251//===----------------------------------------------------------------------===//
252
253foreach i = 0...3 in {
254  def : SysReg<"hstateen"#i, !add(0x60C, i)>;
255  let isRV32Only = 1 in
256  def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>;
257}
258
259//===----------------------------------------------------------------------===//
260// Virtual Supervisor Registers
261//===----------------------------------------------------------------------===//
262
263def : SysReg<"vsstatus", 0x200>;
264def : SysReg<"vsie", 0x204>;
265def : SysReg<"vstvec", 0x205>;
266def : SysReg<"vsscratch", 0x240>;
267def : SysReg<"vsepc", 0x241>;
268def : SysReg<"vscause", 0x242>;
269def : SysReg<"vstval", 0x243>;
270def : SysReg<"vsip", 0x244>;
271def : SysReg<"vsatp", 0x280>;
272
273//===----------------------------------------------------------------------===//
274// Virtual Supervisor Timer Compare
275//===----------------------------------------------------------------------===//
276
277def : SysReg<"vstimecmp", 0x24D>;
278let isRV32Only = 1 in
279def : SysReg<"vstimecmph", 0x25D>;
280
281//===----------------------------------------------------------------------===//
282// Machine Information Registers
283//===----------------------------------------------------------------------===//
284
285def : SysReg<"mvendorid", 0xF11>;
286def : SysReg<"marchid", 0xF12>;
287def : SysReg<"mimpid", 0xF13>;
288def : SysReg<"mhartid", 0xF14>;
289def : SysReg<"mconfigptr", 0xF15>;
290
291//===----------------------------------------------------------------------===//
292// Machine Trap Setup
293//===----------------------------------------------------------------------===//
294
295def : SysReg<"mstatus", 0x300>;
296def : SysReg<"misa", 0x301>;
297def : SysReg<"medeleg", 0x302>;
298def : SysReg<"mideleg", 0x303>;
299def : SysReg<"mie", 0x304>;
300def : SysReg<"mtvec", 0x305>;
301def : SysReg<"mcounteren", 0x306>;
302let isRV32Only = 1 in {
303def : SysReg<"mstatush", 0x310>;
304def : SysReg<"medelegh", 0x312>;
305} // isRV32Only
306
307//===----------------------------------------------------------------------===//
308// Machine Trap Handling
309//===----------------------------------------------------------------------===//
310def : SysReg<"mscratch", 0x340>;
311def : SysReg<"mepc", 0x341>;
312def : SysReg<"mcause", 0x342>;
313def : SysReg<"mtval", 0x343>;
314let isDeprecatedName = 1 in
315def : SysReg<"mbadaddr", 0x343>;
316def : SysReg<"mip", 0x344>;
317def : SysReg<"mtinst", 0x34A>;
318def : SysReg<"mtval2", 0x34B>;
319
320//===----------------------------------------------------------------------===//
321// Machine Configuration
322//===----------------------------------------------------------------------===//
323
324def : SysReg<"menvcfg", 0x30A>;
325let isRV32Only = 1 in
326def : SysReg<"menvcfgh", 0x31A>;
327def : SysReg<"mseccfg", 0x747>;
328let isRV32Only = 1 in
329def : SysReg<"mseccfgh", 0x757>;
330
331//===----------------------------------------------------------------------===//
332// Machine Protection and Translation
333//===----------------------------------------------------------------------===//
334
335// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
336foreach i = 0...15 in {
337  let isRV32Only = !and(i, 1) in
338  def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>;
339}
340
341// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF.
342foreach i = 0...63 in
343  def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>;
344
345//===----------------------------------------------------------------------===//
346// Machine State Enable Registers
347//===----------------------------------------------------------------------===//
348
349foreach i = 0...3 in {
350  def : SysReg<"mstateen"#i, !add(0x30C, i)>;
351  let isRV32Only = 1 in
352  def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>;
353}
354
355//===-----------------------------------------------
356// Resumable Non-Maskable Interrupts(Smrnmi) CSRs
357//===-----------------------------------------------
358def : SysReg<"mnscratch", 0x740>;
359def : SysReg<"mnepc", 0x741>;
360def : SysReg<"mncause", 0x742>;
361def : SysReg<"mnstatus", 0x744>;
362
363//===----------------------------------------------------------------------===//
364// Machine Counter and Timers
365//===----------------------------------------------------------------------===//
366
367def : SysReg<"mcycle", 0xB00>;
368def : SysReg<"minstret", 0xB02>;
369
370// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F.
371foreach i = 3...31 in
372  def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>;
373
374let isRV32Only = 1 in {
375def: SysReg<"mcycleh", 0xB80>;
376def: SysReg<"minstreth", 0xB82>;
377
378// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F.
379foreach i = 3...31 in
380  def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>;
381}
382
383//===----------------------------------------------------------------------===//
384// Machine Counter Setup
385//===----------------------------------------------------------------------===//
386
387def : SysReg<"mcountinhibit", 0x320>;
388
389// mhpmevent3-mhpmevent31 at 0x323-0x33F.
390foreach i = 3...31 in
391  def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>;
392
393// mhpmevent3h-mhpmevent31h at 0x723-0x73F
394foreach i = 3...31 in {
395  let isRV32Only = 1 in
396  def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>;
397}
398
399//===----------------------------------------------------------------------===//
400// Debug/ Trace Registers (shared with Debug Mode)
401//===----------------------------------------------------------------------===//
402
403def : SysReg<"tselect", 0x7A0>;
404def : SysReg<"tdata1", 0x7A1>;
405let isAltName = 1 in {
406def : SysReg<"mcontrol", 0x7A1>;
407def : SysReg<"mcontrol6", 0x7A1>;
408def : SysReg<"icount", 0x7A1>;
409def : SysReg<"itrigger", 0x7A1>;
410def : SysReg<"etrigger", 0x7A1>;
411def : SysReg<"tmexttrigger", 0x7A1>;
412}
413def : SysReg<"tdata2", 0x7A2>;
414def : SysReg<"tdata3", 0x7A3>;
415let isAltName = 1 in {
416def : SysReg<"textra32", 0x7A3>;
417def : SysReg<"textra64", 0x7A3>;
418}
419def : SysReg<"tinfo", 0x7A4>;
420def : SysReg<"tcontrol", 0x7A5>;
421def : SysReg<"mcontext", 0x7A8>;
422def : SysReg<"mscontext", 0x7AA>;
423
424//===----------------------------------------------------------------------===//
425// Debug Mode Registers
426//===----------------------------------------------------------------------===//
427
428def : SysReg<"dcsr", 0x7B0>;
429def : SysReg<"dpc", 0x7B1>;
430
431// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
432// drafts of the RISC-V debug spec
433def : SysReg<"dscratch0", 0x7B2>;
434let isAltName = 1 in
435def : SysReg<"dscratch", 0x7B2>;
436def : SysReg<"dscratch1", 0x7B3>;
437
438//===-----------------------------------------------
439// Advanced Interrupt Architecture
440//===-----------------------------------------------
441
442// Machine-level CSRs
443def : SysReg<"miselect", 0x350>;
444def : SysReg<"mireg", 0x351>;
445foreach i = 2...3 in {
446  def : SysReg<"mireg"#i, !add(0x350, i)>;
447}
448foreach i = 4...6 in {
449  def : SysReg<"mireg"#i, !add(0x351, i)>;
450}
451def : SysReg<"mtopei", 0x35C>;
452def : SysReg<"mtopi", 0xFB0>;
453def : SysReg<"mvien", 0x308>;
454def : SysReg<"mvip", 0x309>;
455let isRV32Only = 1 in {
456def : SysReg<"midelegh", 0x313>;
457def : SysReg<"mieh", 0x314>;
458def : SysReg<"mvienh", 0x318>;
459def : SysReg<"mviph", 0x319>;
460def : SysReg<"miph", 0x354>;
461} // isRV32Only
462
463// Supervisor-level CSRs
464def : SysReg<"siselect", 0x150>;
465def : SysReg<"sireg", 0x151>;
466foreach i = 2...3 in {
467  def : SysReg<"sireg"#i, !add(0x150, i)>;
468}
469foreach i = 4...6 in {
470  def : SysReg<"sireg"#i, !add(0x151, i)>;
471}
472def : SysReg<"stopei", 0x15C>;
473def : SysReg<"stopi", 0xDB0>;
474let isRV32Only = 1 in {
475def : SysReg<"sieh", 0x114>;
476def : SysReg<"siph", 0x154>;
477} // isRV32Only
478
479// Hypervisor and VS CSRs
480def : SysReg<"hvien", 0x608>;
481def : SysReg<"hvictl", 0x609>;
482def : SysReg<"hviprio1", 0x646>;
483def : SysReg<"hviprio2", 0x647>;
484def : SysReg<"vsiselect", 0x250>;
485def : SysReg<"vsireg", 0x251>;
486foreach i = 2...3 in {
487  def : SysReg<"vsireg"#i, !add(0x250, i)>;
488}
489foreach i = 4...6 in {
490  def : SysReg<"vsireg"#i, !add(0x251, i)>;
491}
492def : SysReg<"vstopei", 0x25C>;
493def : SysReg<"vstopi", 0xEB0>;
494let isRV32Only = 1 in {
495def : SysReg<"hidelegh", 0x613>;
496def : SysReg<"hvienh", 0x618>;
497def : SysReg<"hviph", 0x655>;
498def : SysReg<"hviprio1h", 0x656>;
499def : SysReg<"hviprio2h", 0x657>;
500def : SysReg<"vsieh", 0x214>;
501def : SysReg<"vsiph", 0x254>;
502} // isRV32Only
503
504//===-----------------------------------------------
505// Control Transfer Records CSRs
506//===-----------------------------------------------
507def : SysReg<"sctrctl", 0x14e>;
508def : SysReg<"sctrstatus", 0x14f>;
509def : SysReg<"sctrdepth", 0x15f>;
510def : SysReg<"vsctrctl", 0x24e>;
511def : SysReg<"mctrctl", 0x34e>;
512
513//===-----------------------------------------------
514// Cycle and Instret Privilege Mode Filtering (Smcntrpmf)
515//===-----------------------------------------------
516def : SysReg<"mcyclecfg", 0x321>;
517def : SysReg<"minstretcfg", 0x322>;
518let isRV32Only = 1 in {
519def : SysReg<"mcyclecfgh", 0x721>;
520def : SysReg<"minstretcfgh", 0x722>;
521} // isRV32Only
522
523//===-----------------------------------------------
524// Vendor CSRs
525//===-----------------------------------------------
526
527// XSfmclic
528let FeaturesRequired = [{ {RISCV::FeatureVendorXSfmclic} }] in {
529def : SysReg<"sf.mtvt", 0x307>;
530def : SysReg<"sf.mnxti", 0x345>;
531def : SysReg<"sf.mintstatus", 0x346>;
532def : SysReg<"sf.mscratchcsw", 0x348>;
533def : SysReg<"sf.mscratchcswl", 0x349>;
534}
535
536// XSfsclic
537let FeaturesRequired = [{ {RISCV::FeatureVendorXSfsclic} }] in {
538def : SysReg<"sf.stvt", 0x107>;
539def : SysReg<"sf.snxti", 0x145>;
540def : SysReg<"sf.sintstatus", 0x146>;
541def : SysReg<"sf.sscratchcsw", 0x148>;
542def : SysReg<"sf.sscratchcswl", 0x149>;
543}
544
545// Xqciint
546let FeaturesRequired = [{ {RISCV::FeatureVendorXqciint} }], isRV32Only = 1 in {
547def : SysReg<"qc.mmcr", 0x7C0>;
548def : SysReg<"qc.mntvec", 0x7C3>;
549def : SysReg<"qc.mstktopaddr", 0x7C4>;
550def : SysReg<"qc.mstkbottomaddr", 0x7C5>;
551def : SysReg<"qc.mthreadptr", 0x7C8>;
552def : SysReg<"qc.mcause", 0x7C9>;
553
554foreach i = 0 - 7 in {
555  def : SysReg<"qc.mclicip" # i, !add(0x7F0, i)>;
556  def : SysReg<"qc.mclicie" # i, !add(0x7F8, i)>;
557}
558
559foreach i = 0 - 31 in {
560  def : SysReg<"qc.mclicilvl" # !if(!lt(i, 10), "0", "") # i,
561               !add(0xBC0, i)>;
562}
563
564foreach i = 0 - 3 in {
565  def : SysReg<"qc.mwpstartaddr" # i, !add(0x7D0, i)>;
566  def : SysReg<"qc.mwpendaddr" # i,   !add(0x7D4, i)>;
567}
568} // FeatureVendorXqciint, isRV32Only
569