1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// RISC-V system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// CSR (control and status register read/write) instruction options. 18//===----------------------------------------------------------------------===// 19 20class SysReg<string name, bits<12> op> { 21 string Name = name; 22 // A maximum of one alias is supported right now. 23 string AltName = name; 24 // A maximum of one deprecated name is supported right now. Unlike the 25 // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is 26 // used to encourage software to migrate away from the name. 27 string DeprecatedName = ""; 28 bits<12> Encoding = op; 29 // FIXME: add these additional fields when needed. 30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. 31 // Privilege Mode: User = 0, System = 1 or Machine = 3. 32 // bits<2> ReadWrite = op{11 - 10}; 33 // bits<2> XMode = op{9 - 8}; 34 // Check Extra field name and what bits 7-6 correspond to. 35 // bits<2> Extra = op{7 - 6}; 36 // Register number without the privilege bits. 37 // bits<6> Number = op{5 - 0}; 38 code FeaturesRequired = [{ {} }]; 39 bit isRV32Only = 0; 40} 41 42def SysRegsList : GenericTable { 43 let FilterClass = "SysReg"; 44 // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. 45 let Fields = [ 46 "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired", 47 "isRV32Only", 48 ]; 49 50 let PrimaryKey = [ "Encoding" ]; 51 let PrimaryKeyName = "lookupSysRegByEncoding"; 52 let PrimaryKeyReturnRange = true; 53} 54 55def lookupSysRegByName : SearchIndex { 56 let Table = SysRegsList; 57 let Key = [ "Name" ]; 58} 59 60def lookupSysRegByAltName : SearchIndex { 61 let Table = SysRegsList; 62 let Key = [ "AltName" ]; 63} 64 65def lookupSysRegByDeprecatedName : SearchIndex { 66 let Table = SysRegsList; 67 let Key = [ "DeprecatedName" ]; 68} 69 70// The following CSR encodings match those given in Tables 2.2, 71// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual 72// Volume II: Privileged Architecture. 73 74//===----------------------------------------------------------------------===// 75// User Floating-Point CSRs 76//===----------------------------------------------------------------------===// 77 78def SysRegFFLAGS : SysReg<"fflags", 0x001>; 79def SysRegFRM : SysReg<"frm", 0x002>; 80def SysRegFCSR : SysReg<"fcsr", 0x003>; 81 82//===----------------------------------------------------------------------===// 83// User Counter/Timers 84//===----------------------------------------------------------------------===// 85def CYCLE : SysReg<"cycle", 0xC00>; 86def TIME : SysReg<"time", 0xC01>; 87def INSTRET : SysReg<"instret", 0xC02>; 88 89// hpmcounter3-hpmcounter31 at 0xC03-0xC1F. 90foreach i = 3...31 in 91 def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>; 92 93let isRV32Only = 1 in { 94def CYCLEH : SysReg<"cycleh", 0xC80>; 95def TIMEH : SysReg<"timeh", 0xC81>; 96def INSTRETH : SysReg<"instreth", 0xC82>; 97 98// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F. 99foreach i = 3...31 in 100 def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>; 101} 102 103//===----------------------------------------------------------------------===// 104// Supervisor Trap Setup 105//===----------------------------------------------------------------------===// 106def : SysReg<"sstatus", 0x100>; 107def : SysReg<"sie", 0x104>; 108def : SysReg<"stvec", 0x105>; 109def : SysReg<"scounteren", 0x106>; 110def : SysReg<"stimecmp", 0x14D>; 111let isRV32Only = 1 in 112def : SysReg<"stimecmph", 0x15D>; 113 114//===----------------------------------------------------------------------===// 115// Supervisor Configuration 116//===----------------------------------------------------------------------===// 117 118def : SysReg<"senvcfg", 0x10A>; 119 120//===----------------------------------------------------------------------===// 121// Supervisor Trap Handling 122//===----------------------------------------------------------------------===// 123def : SysReg<"sscratch", 0x140>; 124def : SysReg<"sepc", 0x141>; 125def : SysReg<"scause", 0x142>; 126let DeprecatedName = "sbadaddr" in 127def : SysReg<"stval", 0x143>; 128def : SysReg<"sip", 0x144>; 129 130//===----------------------------------------------------------------------===// 131// Supervisor Protection and Translation 132//===----------------------------------------------------------------------===// 133let DeprecatedName = "sptbr" in 134def : SysReg<"satp", 0x180>; 135 136//===----------------------------------------------------------------------===// 137// Quality-of-Service(QoS) Identifiers (Ssqosid) 138//===----------------------------------------------------------------------===// 139def : SysReg<"srmcfg", 0x181>; 140 141//===----------------------------------------------------------------------===// 142// Debug/Trace Registers 143//===----------------------------------------------------------------------===// 144 145def : SysReg<"scontext", 0x5A8>; 146 147//===----------------------------------------------------------------------===// 148// Supervisor Count Overflow (defined in Sscofpmf) 149//===----------------------------------------------------------------------===// 150 151def : SysReg<"scountovf", 0xDA0>; 152 153//===----------------------------------------------------------------------===// 154// Hypervisor Trap Setup 155//===----------------------------------------------------------------------===// 156 157def : SysReg<"hstatus", 0x600>; 158def : SysReg<"hedeleg", 0x602>; 159def : SysReg<"hideleg", 0x603>; 160def : SysReg<"hie", 0x604>; 161def : SysReg<"hcounteren", 0x606>; 162def : SysReg<"hgeie", 0x607>; 163 164//===----------------------------------------------------------------------===// 165// Hypervisor Trap Handling 166//===----------------------------------------------------------------------===// 167 168def : SysReg<"htval", 0x643>; 169def : SysReg<"hip", 0x644>; 170def : SysReg<"hvip", 0x645>; 171def : SysReg<"htinst", 0x64A>; 172def : SysReg<"hgeip", 0xE12>; 173 174//===----------------------------------------------------------------------===// 175// Hypervisor Configuration 176//===----------------------------------------------------------------------===// 177 178def : SysReg<"henvcfg", 0x60A>; 179let isRV32Only = 1 in 180def : SysReg<"henvcfgh", 0x61A>; 181 182//===----------------------------------------------------------------------===// 183// Hypervisor Protection and Translation 184//===----------------------------------------------------------------------===// 185 186def : SysReg<"hgatp", 0x680>; 187 188//===----------------------------------------------------------------------===// 189// Debug/Trace Registers 190//===----------------------------------------------------------------------===// 191 192def : SysReg<"hcontext", 0x6A8>; 193 194//===----------------------------------------------------------------------===// 195// Hypervisor Counter/Timer Virtualization Registers 196//===----------------------------------------------------------------------===// 197 198def : SysReg<"htimedelta", 0x605>; 199let isRV32Only = 1 in 200def : SysReg<"htimedeltah", 0x615>; 201 202//===----------------------------------------------------------------------===// 203// Virtual Supervisor Registers 204//===----------------------------------------------------------------------===// 205 206def : SysReg<"vsstatus", 0x200>; 207def : SysReg<"vsie", 0x204>; 208def : SysReg<"vstvec", 0x205>; 209def : SysReg<"vsscratch", 0x240>; 210def : SysReg<"vsepc", 0x241>; 211def : SysReg<"vscause", 0x242>; 212def : SysReg<"vstval", 0x243>; 213def : SysReg<"vsip", 0x244>; 214def : SysReg<"vstimecmp", 0x24D>; 215let isRV32Only = 1 in 216def : SysReg<"vstimecmph", 0x25D>; 217def : SysReg<"vsatp", 0x280>; 218 219//===----------------------------------------------------------------------===// 220// Machine Information Registers 221//===----------------------------------------------------------------------===// 222 223def : SysReg<"mvendorid", 0xF11>; 224def : SysReg<"marchid", 0xF12>; 225def : SysReg<"mimpid", 0xF13>; 226def : SysReg<"mhartid", 0xF14>; 227def : SysReg<"mconfigptr", 0xF15>; 228 229//===----------------------------------------------------------------------===// 230// Machine Trap Setup 231//===----------------------------------------------------------------------===// 232def : SysReg<"mstatus", 0x300>; 233def : SysReg<"misa", 0x301>; 234def : SysReg<"medeleg", 0x302>; 235def : SysReg<"mideleg", 0x303>; 236def : SysReg<"mie", 0x304>; 237def : SysReg<"mtvec", 0x305>; 238def : SysReg<"mcounteren", 0x306>; 239let isRV32Only = 1 in 240def : SysReg<"mstatush", 0x310>; 241 242//===----------------------------------------------------------------------===// 243// Machine Trap Handling 244//===----------------------------------------------------------------------===// 245def : SysReg<"mscratch", 0x340>; 246def : SysReg<"mepc", 0x341>; 247def : SysReg<"mcause", 0x342>; 248let DeprecatedName = "mbadaddr" in 249def : SysReg<"mtval", 0x343>; 250def : SysReg<"mip", 0x344>; 251def : SysReg<"mtinst", 0x34A>; 252def : SysReg<"mtval2", 0x34B>; 253 254//===----------------------------------------------------------------------===// 255// Machine Configuration 256//===----------------------------------------------------------------------===// 257 258def : SysReg<"menvcfg", 0x30A>; 259let isRV32Only = 1 in 260def : SysReg<"menvcfgh", 0x31A>; 261def : SysReg<"mseccfg", 0x747>; 262let isRV32Only = 1 in 263def : SysReg<"mseccfgh", 0x757>; 264 265//===----------------------------------------------------------------------===// 266// Machine Protection and Translation 267//===----------------------------------------------------------------------===// 268 269// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only. 270foreach i = 0...15 in { 271 let isRV32Only = !and(i, 1) in 272 def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>; 273} 274 275// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF. 276foreach i = 0...63 in 277 def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; 278 279//===----------------------------------------------------------------------===// 280// Machine Counter and Timers 281//===----------------------------------------------------------------------===// 282def : SysReg<"mcycle", 0xB00>; 283def : SysReg<"minstret", 0xB02>; 284 285// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F. 286foreach i = 3...31 in 287 def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>; 288 289let isRV32Only = 1 in { 290def: SysReg<"mcycleh", 0xB80>; 291def: SysReg<"minstreth", 0xB82>; 292 293// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F. 294foreach i = 3...31 in 295 def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>; 296} 297 298//===----------------------------------------------------------------------===// 299// Machine Counter Setup 300//===----------------------------------------------------------------------===// 301let AltName = "mucounteren" in // Privileged spec v1.9.1 Name 302def : SysReg<"mcountinhibit", 0x320>; 303 304// mhpmevent3-mhpmevent31 at 0x323-0x33F. 305foreach i = 3...31 in 306 def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>; 307 308// mhpmevent3h-mhpmevent31h at 0x723-0x73F 309foreach i = 3...31 in { 310 let isRV32Only = 1 in 311 def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; 312} 313 314//===----------------------------------------------------------------------===// 315// Supervisor Counter Setup 316//===----------------------------------------------------------------------===// 317def : SysReg<"scountinhibit", 0x120>; 318 319//===----------------------------------------------------------------------===// 320// Debug/ Trace Registers (shared with Debug Mode) 321//===----------------------------------------------------------------------===// 322def : SysReg<"tselect", 0x7A0>; 323def : SysReg<"tdata1", 0x7A1>; 324def : SysReg<"tdata2", 0x7A2>; 325def : SysReg<"tdata3", 0x7A3>; 326def : SysReg<"mcontext", 0x7A8>; 327 328//===----------------------------------------------------------------------===// 329// Debug Mode Registers 330//===----------------------------------------------------------------------===// 331def : SysReg<"dcsr", 0x7B0>; 332def : SysReg<"dpc", 0x7B1>; 333 334// "dscratch" is an alternative name for "dscratch0" which appeared in earlier 335// drafts of the RISC-V debug spec 336let AltName = "dscratch" in 337def : SysReg<"dscratch0", 0x7B2>; 338def : SysReg<"dscratch1", 0x7B3>; 339 340//===----------------------------------------------------------------------===// 341// User Vector CSRs 342//===----------------------------------------------------------------------===// 343def : SysReg<"vstart", 0x008>; 344def : SysReg<"vxsat", 0x009>; 345def SysRegVXRM : SysReg<"vxrm", 0x00A>; 346def : SysReg<"vcsr", 0x00F>; 347def SysRegVL : SysReg<"vl", 0xC20>; 348def : SysReg<"vtype", 0xC21>; 349def SysRegVLENB: SysReg<"vlenb", 0xC22>; 350 351//===----------------------------------------------------------------------===// 352// Shadow Stack CSR 353//===----------------------------------------------------------------------===// 354def : SysReg<"ssp", 0x011>; 355 356//===----------------------------------------------------------------------===// 357// State Enable Extension (Smstateen) 358//===----------------------------------------------------------------------===// 359 360// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F, 361// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F, 362// and hstateen0h-hstateen3h at 0x61C-0x61F. 363foreach i = 0...3 in { 364 def : SysReg<"sstateen"#i, !add(0x10C, i)>; 365 def : SysReg<"mstateen"#i, !add(0x30C, i)>; 366 let isRV32Only = 1 in 367 def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>; 368 def : SysReg<"hstateen"#i, !add(0x60C, i)>; 369 let isRV32Only = 1 in 370 def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>; 371} 372 373//===----------------------------------------------- 374// Entropy Source CSR 375//===----------------------------------------------- 376 377def SEED : SysReg<"seed", 0x015>; 378 379//===----------------------------------------------- 380// Advanced Interrupt Architecture 381//===----------------------------------------------- 382 383// Machine-level CSRs 384def : SysReg<"miselect", 0x350>; 385def : SysReg<"mireg", 0x351>; 386foreach i = 2...3 in { 387 def : SysReg<"mireg"#i, !add(0x350, i)>; 388} 389foreach i = 4...6 in { 390 def : SysReg<"mireg"#i, !add(0x351, i)>; 391} 392def : SysReg<"mtopei", 0x35C>; 393def : SysReg<"mtopi", 0xFB0>; 394def : SysReg<"mvien", 0x308>; 395def : SysReg<"mvip", 0x309>; 396let isRV32Only = 1 in { 397def : SysReg<"midelegh", 0x313>; 398def : SysReg<"mieh", 0x314>; 399def : SysReg<"mvienh", 0x318>; 400def : SysReg<"mviph", 0x319>; 401def : SysReg<"miph", 0x354>; 402} // isRV32Only 403 404// Supervisor-level CSRs 405def : SysReg<"siselect", 0x150>; 406def : SysReg<"sireg", 0x151>; 407foreach i = 2...3 in { 408 def : SysReg<"sireg"#i, !add(0x150, i)>; 409} 410foreach i = 4...6 in { 411 def : SysReg<"sireg"#i, !add(0x151, i)>; 412} 413def : SysReg<"stopei", 0x15C>; 414def : SysReg<"stopi", 0xDB0>; 415let isRV32Only = 1 in { 416def : SysReg<"sieh", 0x114>; 417def : SysReg<"siph", 0x154>; 418} // isRV32Only 419 420// Hypervisor and VS CSRs 421def : SysReg<"hvien", 0x608>; 422def : SysReg<"hvictl", 0x609>; 423def : SysReg<"hviprio1", 0x646>; 424def : SysReg<"hviprio2", 0x647>; 425def : SysReg<"vsiselect", 0x250>; 426def : SysReg<"vsireg", 0x251>; 427foreach i = 2...3 in { 428 def : SysReg<"vsireg"#i, !add(0x250, i)>; 429} 430foreach i = 4...6 in { 431 def : SysReg<"vsireg"#i, !add(0x251, i)>; 432} 433def : SysReg<"vstopei", 0x25C>; 434def : SysReg<"vstopi", 0xEB0>; 435let isRV32Only = 1 in { 436def : SysReg<"hidelegh", 0x613>; 437def : SysReg<"hvienh", 0x618>; 438def : SysReg<"hviph", 0x655>; 439def : SysReg<"hviprio1h", 0x656>; 440def : SysReg<"hviprio2h", 0x657>; 441def : SysReg<"vsieh", 0x214>; 442def : SysReg<"vsiph", 0x254>; 443} // isRV32Only 444 445//===----------------------------------------------- 446// Jump Vector Table CSR 447//===----------------------------------------------- 448 449def : SysReg<"jvt", 0x017>; 450 451//===----------------------------------------------- 452// Resumable Non-Maskable Interrupts(Smrnmi) CSRs 453//===----------------------------------------------- 454def : SysReg<"mnscratch", 0x740>; 455def : SysReg<"mnepc", 0x741>; 456def : SysReg<"mncause", 0x742>; 457def : SysReg<"mnstatus", 0x744>; 458