xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVScheduleXSf.td (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583) 
1//===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the scheduling information for SiFive extensions.
10//
11//===----------------------------------------------------------------------===//
12
13multiclass LMULSchedWritesVCIX<string id>{
14defm "" : LMULSchedWrites<"WriteVC_" # id>;
15defm "" : LMULSchedWrites<"WriteVC_V_" # id>;
16}
17
18defm "" : LMULSchedWritesVCIX<"I">;
19defm "" : LMULSchedWritesVCIX<"X">;
20defm "" : LMULSchedWritesVCIX<"IV">;
21defm "" : LMULSchedWritesVCIX<"VV">;
22defm "" : LMULSchedWritesVCIX<"XV">;
23defm "" : LMULSchedWritesVCIX<"IVV">;
24defm "" : LMULSchedWritesVCIX<"IVW">;
25defm "" : LMULSchedWritesVCIX<"VVV">;
26defm "" : LMULSchedWritesVCIX<"VVW">;
27defm "" : LMULSchedWritesVCIX<"XVV">;
28defm "" : LMULSchedWritesVCIX<"XVW">;
29foreach f = ["FPR16", "FPR32", "FPR64"] in {
30  defm "" : LMULSchedWritesVCIX<f # "V">;
31  defm "" : LMULSchedWritesVCIX<f # "VV">;
32  defm "" : LMULSchedWritesVCIX<f # "VW">;
33}
34
35multiclass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{
36defm : LMULWriteRes<"WriteVC_" # id, resources>;
37defm : LMULWriteRes<"WriteVC_V_" # id, resources>;
38}
39
40multiclass UnsupportedSchedXsfvcp {
41let Unsupported = true in {
42defm : LMULWriteResVCIX<"I", []>;
43defm : LMULWriteResVCIX<"X", []>;
44defm : LMULWriteResVCIX<"IV", []>;
45defm : LMULWriteResVCIX<"VV", []>;
46defm : LMULWriteResVCIX<"XV", []>;
47defm : LMULWriteResVCIX<"IVV", []>;
48defm : LMULWriteResVCIX<"IVW", []>;
49defm : LMULWriteResVCIX<"VVV", []>;
50defm : LMULWriteResVCIX<"VVW", []>;
51defm : LMULWriteResVCIX<"XVV", []>;
52defm : LMULWriteResVCIX<"XVW", []>;
53foreach f = ["FPR16", "FPR32", "FPR64"] in {
54  defm : LMULWriteResVCIX<f # "V", []>;
55  defm : LMULWriteResVCIX<f # "VV", []>;
56  defm : LMULWriteResVCIX<f # "VW", []>;
57}
58}
59}
60