1//==- RISCVSchedSyntacoreSCR3.td - Syntacore SCR3 Scheduling Definitions -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10 11// This model covers SYNTACORE_SCR3_RV32IMC and SYNTACORE_RV64IMAC 12// configurations (syntacore-scr3-rv32/64). 13// Overview: https://syntacore.com/products/scr3 14 15// SCR3 is single-issue in-order processor 16class SyntacoreSCR3Model : SchedMachineModel { 17 let MicroOpBufferSize = 0; 18 let IssueWidth = 1; 19 let LoadLatency = 2; 20 let MispredictPenalty = 3; 21 let CompleteModel = 0; 22 let UnsupportedFeatures = [HasStdExtD, HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 23 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 24 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 25 HasVInstructions]; 26} 27 28// Branching 29multiclass SCR3_Branching<ProcResourceKind BRU> { 30 def : WriteRes<WriteJmp, [BRU]>; 31 def : WriteRes<WriteJal, [BRU]>; 32 def : WriteRes<WriteJalr, [BRU]>; 33} 34 35// Single-cycle integer arithmetic and logic 36multiclass SCR3_IntALU<ProcResourceKind ALU> { 37 def : WriteRes<WriteIALU, [ALU]>; 38 def : WriteRes<WriteIALU32, [ALU]>; 39 def : WriteRes<WriteShiftImm, [ALU]>; 40 def : WriteRes<WriteShiftImm32, [ALU]>; 41 def : WriteRes<WriteShiftReg, [ALU]>; 42 def : WriteRes<WriteShiftReg32, [ALU]>; 43} 44 45// Integer multiplication 46multiclass SCR3_IntMul<ProcResourceKind MUL> { 47 let Latency = 2 in { 48 def : WriteRes<WriteIMul, [MUL]>; 49 def : WriteRes<WriteIMul32, [MUL]>; 50 } 51} 52 53// Integer division 54multiclass SCR3_IntDiv<ProcResourceKind DIV, int DivLatency> { 55 let Latency = DivLatency, ReleaseAtCycles = [DivLatency] in { 56 def : WriteRes<WriteIDiv, [DIV]>; 57 def : WriteRes<WriteIDiv32, [DIV]>; 58 def : WriteRes<WriteIRem, [DIV]>; 59 def : WriteRes<WriteIRem32, [DIV]>; 60 } 61} 62 63// Load/store instructions on SCR3 have latency 2 64multiclass SCR3_Memory<ProcResourceKind LSU> { 65 let Latency = 2 in { 66 def : WriteRes<WriteSTB, [LSU]>; 67 def : WriteRes<WriteSTH, [LSU]>; 68 def : WriteRes<WriteSTW, [LSU]>; 69 def : WriteRes<WriteSTD, [LSU]>; 70 def : WriteRes<WriteLDB, [LSU]>; 71 def : WriteRes<WriteLDH, [LSU]>; 72 def : WriteRes<WriteLDW, [LSU]>; 73 def : WriteRes<WriteLDD, [LSU]>; 74 } 75} 76 77// Atomic memory 78multiclass SCR3_AtomicMemory<ProcResourceKind LSU> { 79 let Latency = 20 in { 80 def : WriteRes<WriteAtomicLDW, [LSU]>; 81 def : WriteRes<WriteAtomicLDD, [LSU]>; 82 def : WriteRes<WriteAtomicW, [LSU]>; 83 def : WriteRes<WriteAtomicD, [LSU]>; 84 def : WriteRes<WriteAtomicSTW, [LSU]>; 85 def : WriteRes<WriteAtomicSTD, [LSU]>; 86 } 87} 88 89// Others 90multiclass SCR3_Other { 91 def : WriteRes<WriteCSR, []>; 92 def : WriteRes<WriteNop, []>; 93 94 def : InstRW<[WriteIALU], (instrs COPY)>; 95} 96 97 98multiclass SCR3_Unsupported { 99 defm : UnsupportedSchedD; 100 defm : UnsupportedSchedF; 101 defm : UnsupportedSchedSFB; 102 defm : UnsupportedSchedV; 103 defm : UnsupportedSchedXsfvcp; 104 defm : UnsupportedSchedZabha; 105 defm : UnsupportedSchedZba; 106 defm : UnsupportedSchedZbb; 107 defm : UnsupportedSchedZbc; 108 defm : UnsupportedSchedZbs; 109 defm : UnsupportedSchedZbkb; 110 defm : UnsupportedSchedZbkx; 111 defm : UnsupportedSchedZfa; 112 defm : UnsupportedSchedZfh; 113 defm : UnsupportedSchedZvk; 114} 115 116// Bypasses (none) 117multiclass SCR3_NoReadAdvances { 118 def : ReadAdvance<ReadJmp, 0>; 119 def : ReadAdvance<ReadJalr, 0>; 120 def : ReadAdvance<ReadCSR, 0>; 121 def : ReadAdvance<ReadStoreData, 0>; 122 def : ReadAdvance<ReadMemBase, 0>; 123 def : ReadAdvance<ReadIALU, 0>; 124 def : ReadAdvance<ReadIALU32, 0>; 125 def : ReadAdvance<ReadShiftImm, 0>; 126 def : ReadAdvance<ReadShiftImm32, 0>; 127 def : ReadAdvance<ReadShiftReg, 0>; 128 def : ReadAdvance<ReadShiftReg32, 0>; 129 def : ReadAdvance<ReadIDiv, 0>; 130 def : ReadAdvance<ReadIDiv32, 0>; 131 def : ReadAdvance<ReadIRem, 0>; 132 def : ReadAdvance<ReadIRem32, 0>; 133 def : ReadAdvance<ReadIMul, 0>; 134 def : ReadAdvance<ReadIMul32, 0>; 135 def : ReadAdvance<ReadAtomicWA, 0>; 136 def : ReadAdvance<ReadAtomicWD, 0>; 137 def : ReadAdvance<ReadAtomicDA, 0>; 138 def : ReadAdvance<ReadAtomicDD, 0>; 139 def : ReadAdvance<ReadAtomicLDW, 0>; 140 def : ReadAdvance<ReadAtomicLDD, 0>; 141 def : ReadAdvance<ReadAtomicSTW, 0>; 142 def : ReadAdvance<ReadAtomicSTD, 0>; 143} 144 145def SyntacoreSCR3RV32Model : SyntacoreSCR3Model; 146 147let SchedModel = SyntacoreSCR3RV32Model in { 148 let BufferSize = 0 in { 149 def SCR3RV32_ALU : ProcResource<1>; 150 def SCR3RV32_MUL : ProcResource<1>; 151 def SCR3RV32_DIV : ProcResource<1>; 152 def SCR3RV32_LSU : ProcResource<1>; 153 def SCR3RV32_CFU : ProcResource<1>; 154 } 155 156 defm : SCR3_Branching<SCR3RV32_CFU>; 157 defm : SCR3_IntALU<SCR3RV32_ALU>; 158 defm : SCR3_IntMul<SCR3RV32_MUL>; 159 defm : SCR3_IntDiv<SCR3RV32_DIV, /* div latency = */ 8>; 160 defm : SCR3_Memory<SCR3RV32_LSU>; 161 defm : SCR3_AtomicMemory<SCR3RV32_LSU>; 162 defm : SCR3_Other; 163 164 defm : SCR3_Unsupported; 165 defm : SCR3_NoReadAdvances; 166} 167 168def SyntacoreSCR3RV64Model : SyntacoreSCR3Model; 169 170let SchedModel = SyntacoreSCR3RV64Model in { 171 let BufferSize = 0 in { 172 def SCR3RV64_ALU : ProcResource<1>; 173 def SCR3RV64_MUL : ProcResource<1>; 174 def SCR3RV64_DIV : ProcResource<1>; 175 def SCR3RV64_LSU : ProcResource<1>; 176 def SCR3RV64_CFU : ProcResource<1>; 177 } 178 179 defm : SCR3_Branching<SCR3RV64_CFU>; 180 defm : SCR3_IntALU<SCR3RV64_ALU>; 181 defm : SCR3_IntMul<SCR3RV64_MUL>; 182 defm : SCR3_IntDiv<SCR3RV64_DIV, /* div latency = */ 11>; 183 defm : SCR3_Memory<SCR3RV64_LSU>; 184 defm : SCR3_AtomicMemory<SCR3RV64_LSU>; 185 defm : SCR3_Other; 186 187 defm : SCR3_Unsupported; 188 defm : SCR3_NoReadAdvances; 189} 190