1//==- RISCVSchedSyntacoreSCR1.td - Syntacore SCR1 Scheduling Definitions --------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10 11// SCR1: https://github.com/syntacore/scr1 12 13// This model covers SYNTACORE_SCR1_CFG_RV32IMC_MAX configuration (syntacore-scr1-max). 14// SYNTACORE_SCR1_CFG_RV32IC_BASE (syntacore-scr1-base) configuration has essentially 15// same scheduling characteristics. 16 17// SCR1 is single-issue in-order processor 18def SyntacoreSCR1Model : SchedMachineModel { 19 let MicroOpBufferSize = 0; 20 let IssueWidth = 1; 21 let LoadLatency = 2; 22 let MispredictPenalty = 3; 23 let CompleteModel = 0; 24 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 25 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 26 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 27 HasVInstructions]; 28} 29 30let SchedModel = SyntacoreSCR1Model in { 31 32let BufferSize = 0 in { 33def SCR1_ALU : ProcResource<1>; 34def SCR1_LSU : ProcResource<1>; 35def SCR1_MUL : ProcResource<1>; 36def SCR1_DIV : ProcResource<1>; 37def SCR1_CFU : ProcResource<1>; 38} 39 40// Branching 41def : WriteRes<WriteJmp, [SCR1_CFU]>; 42def : WriteRes<WriteJal, [SCR1_CFU]>; 43def : WriteRes<WriteJalr, [SCR1_CFU]>; 44 45// Integer arithmetic and logic 46def : WriteRes<WriteIALU32, [SCR1_ALU]>; 47def : WriteRes<WriteIALU, [SCR1_ALU]>; 48def : WriteRes<WriteShiftImm32, [SCR1_ALU]>; 49def : WriteRes<WriteShiftImm, [SCR1_ALU]>; 50def : WriteRes<WriteShiftReg32, [SCR1_ALU]>; 51def : WriteRes<WriteShiftReg, [SCR1_ALU]>; 52 53// Integer multiplication: single-cycle multiplier in SCR1_CFG_RV32IMC_MAX 54def : WriteRes<WriteIMul, [SCR1_MUL]>; 55def : WriteRes<WriteIMul32, [SCR1_MUL]>; 56 57// Integer division/remainder: latency 33, inverse throughput 33 58let Latency = 33, ReleaseAtCycles = [33] in { 59def : WriteRes<WriteIDiv32, [SCR1_DIV]>; 60def : WriteRes<WriteIDiv, [SCR1_DIV]>; 61def : WriteRes<WriteIRem32, [SCR1_DIV]>; 62def : WriteRes<WriteIRem, [SCR1_DIV]>; 63} 64 65// Load/store instructions on SCR1 have latency 2 and inverse throughput 2 66// (SCR1_CFG_RV32IMC_MAX includes TCM) 67let Latency = 2, ReleaseAtCycles=[2] in { 68// Memory 69def : WriteRes<WriteSTB, [SCR1_LSU]>; 70def : WriteRes<WriteSTH, [SCR1_LSU]>; 71def : WriteRes<WriteSTW, [SCR1_LSU]>; 72def : WriteRes<WriteSTD, [SCR1_LSU]>; 73def : WriteRes<WriteLDB, [SCR1_LSU]>; 74def : WriteRes<WriteLDH, [SCR1_LSU]>; 75def : WriteRes<WriteLDW, [SCR1_LSU]>; 76def : WriteRes<WriteLDD, [SCR1_LSU]>; 77} 78 79// Others 80def : WriteRes<WriteCSR, []>; 81def : WriteRes<WriteNop, []>; 82 83def : InstRW<[WriteIALU], (instrs COPY)>; 84 85//===----------------------------------------------------------------------===// 86// Bypasses (none) 87def : ReadAdvance<ReadJmp, 0>; 88def : ReadAdvance<ReadJalr, 0>; 89def : ReadAdvance<ReadCSR, 0>; 90def : ReadAdvance<ReadStoreData, 0>; 91def : ReadAdvance<ReadMemBase, 0>; 92def : ReadAdvance<ReadIALU, 0>; 93def : ReadAdvance<ReadIALU32, 0>; 94def : ReadAdvance<ReadShiftImm, 0>; 95def : ReadAdvance<ReadShiftImm32, 0>; 96def : ReadAdvance<ReadShiftReg, 0>; 97def : ReadAdvance<ReadShiftReg32, 0>; 98def : ReadAdvance<ReadIDiv, 0>; 99def : ReadAdvance<ReadIDiv32, 0>; 100def : ReadAdvance<ReadIRem, 0>; 101def : ReadAdvance<ReadIRem32, 0>; 102def : ReadAdvance<ReadIMul, 0>; 103def : ReadAdvance<ReadIMul32, 0>; 104 105//===----------------------------------------------------------------------===// 106// Unsupported extensions 107defm : UnsupportedSchedA; 108defm : UnsupportedSchedD; 109defm : UnsupportedSchedF; 110defm : UnsupportedSchedSFB; 111defm : UnsupportedSchedV; 112defm : UnsupportedSchedZabha; 113defm : UnsupportedSchedZba; 114defm : UnsupportedSchedZbb; 115defm : UnsupportedSchedZbc; 116defm : UnsupportedSchedZbs; 117defm : UnsupportedSchedZbkb; 118defm : UnsupportedSchedZbkx; 119defm : UnsupportedSchedZfa; 120defm : UnsupportedSchedZfh; 121defm : UnsupportedSchedXsfvcp; 122defm : UnsupportedSchedZvk; 123} 124