1//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class RISCVProfile<string name, list<SubtargetFeature> features> 10 : SubtargetFeature<name, "Is" # NAME, "true", 11 "RISC-V " # name # " profile", features> { 12 // Indicates if the profile is not yet ratified, so should be treated as 13 // experimental. 14 bit Experimental = false; 15} 16class RISCVExperimentalProfile<string name, list<SubtargetFeature> features> 17 : RISCVProfile<"experimental-"#name, features> { 18 let Experimental = true; 19} 20 21defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI]; 22defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI]; 23 24defvar RVA20U64Features = [Feature64Bit, 25 FeatureStdExtI, 26 FeatureStdExtM, 27 FeatureStdExtA, 28 FeatureStdExtF, 29 FeatureStdExtD, 30 FeatureStdExtC, 31 FeatureStdExtZicntr, 32 FeatureStdExtZiccif, 33 FeatureStdExtZiccrse, 34 FeatureStdExtZiccamoa, 35 FeatureStdExtZa128rs, 36 FeatureStdExtZicclsm]; 37 38defvar RVA20S64Features = !listconcat(RVA20U64Features, 39 [FeatureStdExtZifencei, 40 FeatureStdExtSvbare, 41 FeatureStdExtSvade, 42 FeatureStdExtSsccptr, 43 FeatureStdExtSstvecd, 44 FeatureStdExtSstvala]); 45 46defvar RVA22U64Features = [Feature64Bit, 47 FeatureStdExtI, 48 FeatureStdExtM, 49 FeatureStdExtA, 50 FeatureStdExtF, 51 FeatureStdExtD, 52 FeatureStdExtC, 53 FeatureStdExtZicntr, 54 FeatureStdExtZiccif, 55 FeatureStdExtZiccrse, 56 FeatureStdExtZiccamoa, 57 FeatureStdExtZicclsm, 58 FeatureStdExtZa64rs, 59 FeatureStdExtZihpm, 60 FeatureStdExtZihintpause, 61 FeatureStdExtZba, 62 FeatureStdExtZbb, 63 FeatureStdExtZbs, 64 FeatureStdExtZic64b, 65 FeatureStdExtZicbom, 66 FeatureStdExtZicbop, 67 FeatureStdExtZicboz, 68 FeatureStdExtZfhmin, 69 FeatureStdExtZkt]; 70 71defvar RVA22S64Features = !listconcat(RVA22U64Features, 72 [FeatureStdExtZifencei, 73 FeatureStdExtSvbare, 74 FeatureStdExtSvade, 75 FeatureStdExtSsccptr, 76 FeatureStdExtSstvecd, 77 FeatureStdExtSstvala, 78 FeatureStdExtSscounterenw, 79 FeatureStdExtSvpbmt, 80 FeatureStdExtSvinval]); 81 82defvar RVA23U64Features = [Feature64Bit, 83 FeatureStdExtI, 84 FeatureStdExtM, 85 FeatureStdExtA, 86 FeatureStdExtF, 87 FeatureStdExtD, 88 FeatureStdExtC, 89 FeatureStdExtZicntr, 90 FeatureStdExtZihpm, 91 FeatureStdExtZiccif, 92 FeatureStdExtZiccrse, 93 FeatureStdExtZiccamoa, 94 FeatureStdExtZicclsm, 95 FeatureStdExtZa64rs, 96 FeatureStdExtZihintpause, 97 FeatureStdExtZba, 98 FeatureStdExtZbb, 99 FeatureStdExtZbs, 100 FeatureStdExtZic64b, 101 FeatureStdExtZicbom, 102 FeatureStdExtZicbop, 103 FeatureStdExtZicboz, 104 FeatureStdExtZfhmin, 105 FeatureStdExtZkt, 106 FeatureStdExtV, 107 FeatureStdExtZvfhmin, 108 FeatureStdExtZvbb, 109 FeatureStdExtZvkt, 110 FeatureStdExtZihintntl, 111 FeatureStdExtZicond, 112 FeatureStdExtZimop, 113 FeatureStdExtZcmop, 114 FeatureStdExtZcb, 115 FeatureStdExtZfa, 116 FeatureStdExtZawrs]; 117 118defvar RVA23S64Features = !listconcat(RVA23U64Features, 119 [FeatureStdExtZifencei, 120 FeatureStdExtSvbare, 121 FeatureStdExtSvade, 122 FeatureStdExtSsccptr, 123 FeatureStdExtSstvecd, 124 FeatureStdExtSstvala, 125 FeatureStdExtSscounterenw, 126 FeatureStdExtSvpbmt, 127 FeatureStdExtSvinval, 128 FeatureStdExtSvnapot, 129 FeatureStdExtSstc, 130 FeatureStdExtSscofpmf, 131 FeatureStdExtSsnpm, 132 FeatureStdExtSsu64xl, 133 FeatureStdExtH, 134 FeatureStdExtSsstateen, 135 FeatureStdExtShcounterenw, 136 FeatureStdExtShvstvala, 137 FeatureStdExtShtvala, 138 FeatureStdExtShvstvecd, 139 FeatureStdExtShvsatpa, 140 FeatureStdExtShgatpa]); 141 142defvar RVB23U64Features = [Feature64Bit, 143 FeatureStdExtI, 144 FeatureStdExtM, 145 FeatureStdExtA, 146 FeatureStdExtF, 147 FeatureStdExtD, 148 FeatureStdExtC, 149 FeatureStdExtZicntr, 150 FeatureStdExtZihpm, 151 FeatureStdExtZiccif, 152 FeatureStdExtZiccrse, 153 FeatureStdExtZiccamoa, 154 FeatureStdExtZicclsm, 155 FeatureStdExtZa64rs, 156 FeatureStdExtZihintpause, 157 FeatureStdExtZba, 158 FeatureStdExtZbb, 159 FeatureStdExtZbs, 160 FeatureStdExtZic64b, 161 FeatureStdExtZicbom, 162 FeatureStdExtZicbop, 163 FeatureStdExtZicboz, 164 FeatureStdExtZkt, 165 FeatureStdExtZihintntl, 166 FeatureStdExtZicond, 167 FeatureStdExtZimop, 168 FeatureStdExtZcmop, 169 FeatureStdExtZcb, 170 FeatureStdExtZfa, 171 FeatureStdExtZawrs]; 172 173defvar RVB23S64Features = !listconcat(RVB23U64Features, 174 [FeatureStdExtZifencei, 175 FeatureStdExtSvnapot, 176 FeatureStdExtSvbare, 177 FeatureStdExtSvade, 178 FeatureStdExtSsccptr, 179 FeatureStdExtSstvecd, 180 FeatureStdExtSstvala, 181 FeatureStdExtSscounterenw, 182 FeatureStdExtSvpbmt, 183 FeatureStdExtSvinval, 184 FeatureStdExtSstc, 185 FeatureStdExtSscofpmf, 186 FeatureStdExtSsu64xl]); 187 188defvar RVM23U32Features = [Feature32Bit, 189 FeatureStdExtI, 190 FeatureStdExtM, 191 FeatureStdExtZba, 192 FeatureStdExtZbb, 193 FeatureStdExtZbs, 194 FeatureStdExtZicond, 195 FeatureStdExtZihintpause, 196 FeatureStdExtZihintntl, 197 FeatureStdExtZce, 198 FeatureStdExtZicbop, 199 FeatureStdExtZimop, 200 FeatureStdExtZcmop]; 201 202def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>; 203def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>; 204def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>; 205def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>; 206def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; 207def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; 208def RVA23U64 : RISCVExperimentalProfile<"rva23u64", RVA23U64Features>; 209def RVA23S64 : RISCVExperimentalProfile<"rva23s64", RVA23S64Features>; 210def RVB23U64 : RISCVExperimentalProfile<"rvb23u64", RVB23U64Features>; 211def RVB23S64 : RISCVExperimentalProfile<"rvb23s64", RVB23S64Features>; 212def RVM23U32 : RISCVExperimentalProfile<"rvm23u32", RVM23U32Features>; 213