1//===-- RISCVInstrInfoZimop.td -----------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 10// May-Be-Operations Extension (Zimop). 11// 12//===----------------------------------------------------------------------===// 13 14class RVInstIMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3, RISCVOpcode opcode, 15 dag outs, dag ins, string opcodestr, string argstr> 16 : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> { 17 let Inst{31} = imm7{6}; 18 let Inst{30} = imm5{4}; 19 let Inst{29-28} = imm7{5-4}; 20 let Inst{27-26} = imm5{3-2}; 21 let Inst{25-22} = imm7{3-0}; 22 let Inst{21-20} = imm5{1-0}; 23} 24 25class RVInstRMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, RISCVOpcode opcode, 26 dag outs, dag ins, string opcodestr, string argstr> 27 : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> { 28 let Inst{31} = imm4{3}; 29 let Inst{30} = imm3{2}; 30 let Inst{29-28} = imm4{2-1}; 31 let Inst{27-26} = imm3{1-0}; 32 let Inst{25} = imm4{0}; 33} 34 35def riscv_mopr : SDNode<"RISCVISD::MOPR", 36 SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>]>>; 38def riscv_moprr : SDNode<"RISCVISD::MOPRR", 39 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 40 SDTCisSameAs<0, 2>, 41 SDTCisSameAs<0, 3>]>>; 42 43let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 44class RVMopr<bits<7> imm7, bits<5> imm5, bits<3> funct3, 45 RISCVOpcode opcode, string opcodestr> 46 : RVInstIMopr<imm7, imm5, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1), 47 opcodestr, "$rd, $rs1">; 48 49let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 50class RVMoprr<bits<4> imm4, bits<3> imm3, bits<3> funct3, 51 RISCVOpcode opcode, string opcodestr> 52 : RVInstRMoprr<imm4, imm3, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), 53 opcodestr, "$rd, $rs1, $rs2">; 54 55foreach i = 0...31 in { 56 let Predicates = [HasStdExtZimop] in 57 def MOPR#i : RVMopr<0b1000111, i, 0b100, OPC_SYSTEM, "mop.r."#i>, 58 Sched<[]>; 59} 60 61foreach i = 0...7 in { 62 let Predicates = [HasStdExtZimop] in 63 def MOPRR#i : RVMoprr<0b1001, i, 0b100, OPC_SYSTEM, "mop.rr."#i>, 64 Sched<[]>; 65} 66 67let Predicates = [HasStdExtZimop] in { 68// Zimop instructions 69foreach i = 0...31 in { 70 def : Pat<(XLenVT (riscv_mopr GPR:$rs1, (XLenVT i))), 71 (!cast<Instruction>("MOPR"#i) GPR:$rs1)>; 72} 73 74foreach i = 0...7 in { 75 def : Pat<(XLenVT (riscv_moprr GPR:$rs1, GPR:$rs2, (XLenVT i))), 76 (!cast<Instruction>("MOPRR"#i) GPR:$rs1, GPR:$rs2)>; 77} 78 79} // Predicates = [HasStdExtZimop] 80