1//===-- RISCVInstrInfoZicbo.td - RISC-V CMO instructions ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard Base Cache 10// Management Operation ISA Extensions document (Zicbom, Zicboz, and Zicbop). 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Operand definitions. 16//===----------------------------------------------------------------------===// 17 18// A 12-bit signed immediate where the least significant five bits are zero. 19def simm12_lsb00000 : RISCVOp, 20 ImmLeaf<XLenVT, [{return isShiftedInt<7, 5>(Imm);}]> { 21 let ParserMatchClass = SImmAsmOperand<12, "Lsb00000">; 22 let EncoderMethod = "getImmOpValue"; 23 let DecoderMethod = "decodeSImmOperand<12>"; 24 let MCOperandPredicate = [{ 25 int64_t Imm; 26 if (MCOp.evaluateAsConstantImm(Imm)) 27 return isShiftedInt<7, 5>(Imm); 28 return MCOp.isBareSymbolRef(); 29 }]; 30 let OperandType = "OPERAND_SIMM12_LSB00000"; 31} 32 33//===----------------------------------------------------------------------===// 34// Instruction Class Templates 35//===----------------------------------------------------------------------===// 36let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in 37class CBO_r<bits<12> optype, string opcodestr> 38 : RVInstI<0b010, OPC_MISC_MEM, (outs), (ins GPRMemZeroOffset:$rs1), 39 opcodestr, "$rs1"> { 40 let imm12 = optype; 41 let rd = 0b00000; 42} 43 44let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in 45class Prefetch_ri<bits<5> optype, string opcodestr> 46 : RVInstS<0b110, OPC_OP_IMM, (outs), (ins GPR:$rs1, simm12_lsb00000:$imm12), 47 opcodestr, "${imm12}(${rs1})"> { 48 let Inst{11-7} = 0b00000; 49 let rs2 = optype; 50} 51 52//===----------------------------------------------------------------------===// 53// Instructions 54//===----------------------------------------------------------------------===// 55 56let Predicates = [HasStdExtZicbom] in { 57def CBO_CLEAN : CBO_r<0b000000000001, "cbo.clean">, Sched<[]>; 58def CBO_FLUSH : CBO_r<0b000000000010, "cbo.flush">, Sched<[]>; 59def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>; 60} // Predicates = [HasStdExtZicbom] 61 62let Predicates = [HasStdExtZicboz] in { 63def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>; 64} // Predicates = [HasStdExtZicboz] 65 66let Predicates = [HasStdExtZicbop] in { 67def PREFETCH_I : Prefetch_ri<0b00000, "prefetch.i">, Sched<[]>; 68def PREFETCH_R : Prefetch_ri<0b00001, "prefetch.r">, Sched<[]>; 69def PREFETCH_W : Prefetch_ri<0b00011, "prefetch.w">, Sched<[]>; 70} // Predicates = [HasStdExtZicbop] 71 72//===----------------------------------------------------------------------===// 73// Patterns 74//===----------------------------------------------------------------------===// 75 76def AddrRegImmLsb00000 : ComplexPattern<iPTR, 2, "SelectAddrRegImmLsb00000">; 77 78let Predicates = [HasStdExtZicbop] in { 79 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12), 80 timm, timm, (i32 0)), 81 (PREFETCH_I GPR:$rs1, simm12_lsb00000:$imm12)>; 82 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12), 83 (i32 0), timm, (i32 1)), 84 (PREFETCH_R GPR:$rs1, simm12_lsb00000:$imm12)>; 85 def : Pat<(prefetch (AddrRegImmLsb00000 (XLenVT GPR:$rs1), simm12_lsb00000:$imm12), 86 (i32 1), timm, (i32 1)), 87 (PREFETCH_W GPR:$rs1, simm12_lsb00000:$imm12)>; 88} 89