1//===-- RISCVInstrFormatsC.td - RISC-V C Instruction Formats -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V C extension instruction formats. 10// 11//===----------------------------------------------------------------------===// 12 13class RVInst16<dag outs, dag ins, string opcodestr, string argstr, 14 list<dag> pattern, InstFormat format> 15 : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> { 16 field bits<16> Inst; 17 // SoftFail is a field the disassembler can use to provide a way for 18 // instructions to not match without killing the whole decode process. It is 19 // mainly used for ARM, but Tablegen expects this field to exist or it fails 20 // to build the decode table. 21 field bits<16> SoftFail = 0; 22 let Size = 2; 23} 24 25class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins, 26 string opcodestr, string argstr> 27 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCR> { 28 bits<5> rs1; 29 bits<5> rs2; 30 31 let Inst{15-12} = funct4; 32 let Inst{11-7} = rs1; 33 let Inst{6-2} = rs2; 34 let Inst{1-0} = opcode; 35} 36 37// The immediate value encoding differs for each instruction, so each subclass 38// is responsible for setting the appropriate bits in the Inst field. 39// The bits Inst{12} and Inst{6-2} may need to be set differently for some 40// instructions. 41class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 42 string opcodestr, string argstr> 43 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCI> { 44 bits<10> imm; 45 bits<5> rd; 46 47 let Inst{15-13} = funct3; 48 let Inst{12} = imm{5}; 49 let Inst{11-7} = rd; 50 let Inst{6-2} = imm{4-0}; 51 let Inst{1-0} = opcode; 52} 53 54// The immediate value encoding differs for each instruction, so each subclass 55// is responsible for setting the appropriate bits in the Inst field. 56// The bits Inst{12-7} may need to be set differently for some instructions. 57class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 58 string opcodestr, string argstr> 59 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSS> { 60 bits<10> imm; 61 bits<5> rs2; 62 bits<5> rs1; 63 64 let Inst{15-13} = funct3; 65 let Inst{12-7} = imm{5-0}; 66 let Inst{6-2} = rs2; 67 let Inst{1-0} = opcode; 68} 69 70class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 71 string opcodestr, string argstr> 72 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCIW> { 73 bits<10> imm; 74 bits<3> rd; 75 76 let Inst{15-13} = funct3; 77 let Inst{4-2} = rd; 78 let Inst{1-0} = opcode; 79} 80 81// The immediate value encoding differs for each instruction, so each subclass 82// is responsible for setting the appropriate bits in the Inst field. 83// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 84class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 85 string opcodestr, string argstr> 86 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCL> { 87 bits<3> rd; 88 bits<3> rs1; 89 90 let Inst{15-13} = funct3; 91 let Inst{9-7} = rs1; 92 let Inst{4-2} = rd; 93 let Inst{1-0} = opcode; 94} 95 96// The immediate value encoding differs for each instruction, so each subclass 97// is responsible for setting the appropriate bits in the Inst field. 98// The bits Inst{12-10} and Inst{6-5} must be set for each instruction. 99class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 100 string opcodestr, string argstr> 101 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCS> { 102 bits<3> rs2; 103 bits<3> rs1; 104 105 let Inst{15-13} = funct3; 106 let Inst{9-7} = rs1; 107 let Inst{4-2} = rs2; 108 let Inst{1-0} = opcode; 109} 110 111class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs, 112 dag ins, string opcodestr, string argstr> 113 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCA> { 114 bits<3> rs2; 115 bits<3> rs1; 116 117 let Inst{15-10} = funct6; 118 let Inst{9-7} = rs1; 119 let Inst{6-5} = funct2; 120 let Inst{4-2} = rs2; 121 let Inst{1-0} = opcode; 122} 123 124class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 125 string opcodestr, string argstr> 126 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCB> { 127 bits<9> imm; 128 bits<3> rs1; 129 130 let Inst{15-13} = funct3; 131 let Inst{9-7} = rs1; 132 let Inst{1-0} = opcode; 133} 134 135class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins, 136 string opcodestr, string argstr> 137 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCJ> { 138 bits<11> offset; 139 140 let Inst{15-13} = funct3; 141 let Inst{12} = offset{10}; 142 let Inst{11} = offset{3}; 143 let Inst{10-9} = offset{8-7}; 144 let Inst{8} = offset{9}; 145 let Inst{7} = offset{5}; 146 let Inst{6} = offset{6}; 147 let Inst{5-3} = offset{2-0}; 148 let Inst{2} = offset{4}; 149 let Inst{1-0} = opcode; 150} 151 152class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs, 153 dag ins, string opcodestr, string argstr> 154 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCU>{ 155 bits<3> rd; 156 157 let Inst{15-10} = funct6; 158 let Inst{9-7} = rd; 159 let Inst{6-2} = funct5; 160 let Inst{1-0} = opcode; 161} 162 163// The immediate value encoding differs for each instruction, so each subclass 164// is responsible for setting the appropriate bits in the Inst field. 165// The bits Inst{6-5} must be set for each instruction. 166class RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins, 167 string opcodestr, string argstr> 168 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLB> { 169 bits<3> rd; 170 bits<3> rs1; 171 172 let Inst{15-10} = funct6; 173 let Inst{9-7} = rs1; 174 let Inst{4-2} = rd; 175 let Inst{1-0} = opcode; 176} 177 178// The immediate value encoding differs for each instruction, so each subclass 179// is responsible for setting the appropriate bits in the Inst field. 180// The bits Inst{5} must be set for each instruction. 181class RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs, 182 dag ins, string opcodestr, string argstr> 183 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCLH> { 184 bits<3> rd; 185 bits<3> rs1; 186 187 let Inst{15-10} = funct6; 188 let Inst{9-7} = rs1; 189 let Inst{6} = funct1; 190 let Inst{4-2} = rd; 191 let Inst{1-0} = opcode; 192} 193 194// The immediate value encoding differs for each instruction, so each subclass 195// is responsible for setting the appropriate bits in the Inst field. 196// The bits Inst{6-5} must be set for each instruction. 197class RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins, 198 string opcodestr, string argstr> 199 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSB> { 200 bits<3> rs2; 201 bits<3> rs1; 202 203 let Inst{15-10} = funct6; 204 let Inst{9-7} = rs1; 205 let Inst{4-2} = rs2; 206 let Inst{1-0} = opcode; 207} 208 209// The immediate value encoding differs for each instruction, so each subclass 210// is responsible for setting the appropriate bits in the Inst field. 211// The bits Inst{5} must be set for each instruction. 212class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs, 213 dag ins, string opcodestr, string argstr> 214 : RVInst16<outs, ins, opcodestr, argstr, [], InstFormatCSH> { 215 bits<3> rs2; 216 bits<3> rs1; 217 218 let Inst{15-10} = funct6; 219 let Inst{9-7} = rs1; 220 let Inst{6} = funct1; 221 let Inst{4-2} = rs2; 222 let Inst{1-0} = opcode; 223} 224 225//===----------------------------------------------------------------------===// 226// Instruction classes for .insn directives 227//===----------------------------------------------------------------------===// 228 229class DirectiveInsnCR<dag outs, dag ins, string argstr> 230 : RVInst16<outs, ins, "", "", [], InstFormatCR> { 231 bits<2> opcode; 232 bits<4> funct4; 233 234 bits<5> rs2; 235 bits<5> rd; 236 237 let Inst{15-12} = funct4; 238 let Inst{11-7} = rd; 239 let Inst{6-2} = rs2; 240 let Inst{1-0} = opcode; 241 242 let AsmString = ".insn cr " # argstr; 243} 244 245class DirectiveInsnCI<dag outs, dag ins, string argstr> 246 : RVInst16<outs, ins, "", "", [], InstFormatCI> { 247 bits<2> opcode; 248 bits<3> funct3; 249 250 bits<6> imm6; 251 bits<5> rd; 252 253 let Inst{15-13} = funct3; 254 let Inst{12} = imm6{5}; 255 let Inst{11-7} = rd; 256 let Inst{6-2} = imm6{4-0}; 257 let Inst{1-0} = opcode; 258 259 let AsmString = ".insn ci " # argstr; 260} 261 262class DirectiveInsnCIW<dag outs, dag ins, string argstr> 263 : RVInst16<outs, ins, "", "", [], InstFormatCIW> { 264 bits<2> opcode; 265 bits<3> funct3; 266 267 bits<8> imm8; 268 bits<3> rd; 269 270 let Inst{15-13} = funct3; 271 let Inst{12-5} = imm8; 272 let Inst{4-2} = rd; 273 let Inst{1-0} = opcode; 274 275 let AsmString = ".insn ciw " # argstr; 276} 277 278class DirectiveInsnCSS<dag outs, dag ins, string argstr> 279 : RVInst16<outs, ins, "", "", [], InstFormatCSS> { 280 bits<2> opcode; 281 bits<3> funct3; 282 283 bits<6> imm6; 284 bits<5> rs2; 285 286 let Inst{15-13} = funct3; 287 let Inst{12-7} = imm6; 288 let Inst{6-2} = rs2; 289 let Inst{1-0} = opcode; 290 291 let AsmString = ".insn css " # argstr; 292} 293 294class DirectiveInsnCL<dag outs, dag ins, string argstr> 295 : RVInst16<outs, ins, "", "", [], InstFormatCL> { 296 bits<2> opcode; 297 bits<3> funct3; 298 299 bits<5> imm5; 300 bits<3> rd; 301 bits<3> rs1; 302 303 let Inst{15-13} = funct3; 304 let Inst{12-10} = imm5{4-2}; 305 let Inst{9-7} = rs1; 306 let Inst{6-5} = imm5{1-0}; 307 let Inst{4-2} = rd; 308 let Inst{1-0} = opcode; 309 310 let AsmString = ".insn cl " # argstr; 311} 312 313class DirectiveInsnCS<dag outs, dag ins, string argstr> 314 : RVInst16<outs, ins, "", "", [], InstFormatCS> { 315 bits<2> opcode; 316 bits<3> funct3; 317 318 bits<5> imm5; 319 bits<3> rs2; 320 bits<3> rs1; 321 322 let Inst{15-13} = funct3; 323 let Inst{12-10} = imm5{4-2}; 324 let Inst{9-7} = rs1; 325 let Inst{6-5} = imm5{1-0}; 326 let Inst{4-2} = rs2; 327 let Inst{1-0} = opcode; 328 329 let AsmString = ".insn cs " # argstr; 330} 331 332class DirectiveInsnCA<dag outs, dag ins, string argstr> 333 : RVInst16<outs, ins, "", "", [], InstFormatCA> { 334 bits<2> opcode; 335 bits<6> funct6; 336 bits<2> funct2; 337 338 bits<3> rd; 339 bits<3> rs2; 340 341 let Inst{15-10} = funct6; 342 let Inst{9-7} = rd; 343 let Inst{6-5} = funct2; 344 let Inst{4-2} = rs2; 345 let Inst{1-0} = opcode; 346 347 let AsmString = ".insn ca " # argstr; 348} 349 350class DirectiveInsnCB<dag outs, dag ins, string argstr> 351 : RVInst16<outs, ins, "", "", [], InstFormatCB> { 352 bits<2> opcode; 353 bits<3> funct3; 354 355 bits<8> imm8; 356 bits<3> rs1; 357 358 let Inst{15-13} = funct3; 359 let Inst{12} = imm8{7}; 360 let Inst{11-10} = imm8{3-2}; 361 let Inst{9-7} = rs1; 362 let Inst{6-5} = imm8{6-5}; 363 let Inst{4-3} = imm8{1-0}; 364 let Inst{2} = imm8{4}; 365 let Inst{1-0} = opcode; 366 367 let AsmString = ".insn cb " # argstr; 368} 369 370class DirectiveInsnCJ<dag outs, dag ins, string argstr> 371 : RVInst16<outs, ins, "", "", [], InstFormatCJ> { 372 bits<2> opcode; 373 bits<3> funct3; 374 375 bits<11> imm11; 376 377 let Inst{15-13} = funct3; 378 let Inst{12} = imm11{10}; 379 let Inst{11} = imm11{3}; 380 let Inst{10-9} = imm11{8-7}; 381 let Inst{8} = imm11{9}; 382 let Inst{7} = imm11{5}; 383 let Inst{6} = imm11{6}; 384 let Inst{5-3} = imm11{2-0}; 385 let Inst{2} = imm11{4}; 386 let Inst{1-0} = opcode; 387 388 let AsmString = ".insn cj " # argstr; 389} 390