xref: /illumos-gate/usr/src/boot/efi/include/Protocol/PciIo.h (revision f334afcfaebea1b7dc3430015651d8d748fa8a3e)
1 /** @file
2   EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,
3   and DMA interfaces that a driver uses to access its PCI controller.
4 
5   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6   SPDX-License-Identifier: BSD-2-Clause-Patent
7 **/
8 
9 #ifndef __PCI_IO_H__
10 #define __PCI_IO_H__
11 
12 ///
13 /// Global ID for the PCI I/O Protocol
14 ///
15 #define EFI_PCI_IO_PROTOCOL_GUID \
16   { \
17     0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \
18   }
19 
20 typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;
21 
22 ///
23 /// *******************************************************
24 /// EFI_PCI_IO_PROTOCOL_WIDTH
25 /// *******************************************************
26 ///
27 typedef enum {
28   EfiPciIoWidthUint8 = 0,
29   EfiPciIoWidthUint16,
30   EfiPciIoWidthUint32,
31   EfiPciIoWidthUint64,
32   EfiPciIoWidthFifoUint8,
33   EfiPciIoWidthFifoUint16,
34   EfiPciIoWidthFifoUint32,
35   EfiPciIoWidthFifoUint64,
36   EfiPciIoWidthFillUint8,
37   EfiPciIoWidthFillUint16,
38   EfiPciIoWidthFillUint32,
39   EfiPciIoWidthFillUint64,
40   EfiPciIoWidthMaximum
41 } EFI_PCI_IO_PROTOCOL_WIDTH;
42 
43 //
44 // Complete PCI address generater
45 //
46 #define EFI_PCI_IO_PASS_THROUGH_BAR                0xff    ///< Special BAR that passes a memory or I/O cycle through unchanged
47 #define EFI_PCI_IO_ATTRIBUTE_MASK                  0x077f  ///< All the following I/O and Memory cycles
48 #define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO    0x0001  ///< I/O cycles 0x0000-0x00FF (10 bit decode)
49 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO                0x0002  ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)
50 #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO        0x0004  ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
51 #define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY            0x0008  ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)
52 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO                0x0010  ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
53 #define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO        0x0020  ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
54 #define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO      0x0040  ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
55 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE  0x0080  ///< Map a memory range so writes are combined
56 #define EFI_PCI_IO_ATTRIBUTE_IO                    0x0100  ///< Enable the I/O decode bit in the PCI Config Header
57 #define EFI_PCI_IO_ATTRIBUTE_MEMORY                0x0200  ///< Enable the Memory decode bit in the PCI Config Header
58 #define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER            0x0400  ///< Enable the DMA bit in the PCI Config Header
59 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED         0x0800  ///< Map a memory range so all r/w accesses are cached
60 #define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE        0x1000  ///< Disable a memory range
61 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE       0x2000  ///< Clear for an add-in PCI Device
62 #define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM          0x4000  ///< Clear for a physical PCI Option ROM accessed through ROM BAR
63 #define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE    0x8000  ///< Clear for PCI controllers that can not genrate a DAC
64 #define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16             0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)
65 #define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16     0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
66 #define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16             0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
67 
68 #define EFI_PCI_DEVICE_ENABLE  (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)
69 #define EFI_VGA_DEVICE_ENABLE  (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)
70 
71 ///
72 /// *******************************************************
73 /// EFI_PCI_IO_PROTOCOL_OPERATION
74 /// *******************************************************
75 ///
76 typedef enum {
77   ///
78   /// A read operation from system memory by a bus master.
79   ///
80   EfiPciIoOperationBusMasterRead,
81   ///
82   /// A write operation from system memory by a bus master.
83   ///
84   EfiPciIoOperationBusMasterWrite,
85   ///
86   /// Provides both read and write access to system memory by both the processor and a
87   /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.
88   ///
89   EfiPciIoOperationBusMasterCommonBuffer,
90   EfiPciIoOperationMaximum
91 } EFI_PCI_IO_PROTOCOL_OPERATION;
92 
93 ///
94 /// *******************************************************
95 /// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION
96 /// *******************************************************
97 ///
98 typedef enum {
99   ///
100   /// Retrieve the PCI controller's current attributes, and return them in Result.
101   ///
102   EfiPciIoAttributeOperationGet,
103   ///
104   /// Set the PCI controller's current attributes to Attributes.
105   ///
106   EfiPciIoAttributeOperationSet,
107   ///
108   /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.
109   ///
110   EfiPciIoAttributeOperationEnable,
111   ///
112   /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.
113   ///
114   EfiPciIoAttributeOperationDisable,
115   ///
116   /// Retrieve the PCI controller's supported attributes, and return them in Result.
117   ///
118   EfiPciIoAttributeOperationSupported,
119   EfiPciIoAttributeOperationMaximum
120 } EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;
121 
122 /**
123   Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is
124   satisfied or after a defined duration.
125 
126   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
127   @param  Width                 Signifies the width of the memory or I/O operations.
128   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
129                                 base address for the memory operation to perform.
130   @param  Offset                The offset within the selected BAR to start the memory operation.
131   @param  Mask                  Mask used for the polling criteria.
132   @param  Value                 The comparison value used for the polling exit criteria.
133   @param  Delay                 The number of 100 ns units to poll.
134   @param  Result                Pointer to the last value read from the memory location.
135 
136   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
137   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
138   @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.
139   @retval EFI_TIMEOUT           Delay expired before a match occurred.
140   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
141   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
142 
143 **/
144 typedef
145 EFI_STATUS
146 (EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(
147   IN EFI_PCI_IO_PROTOCOL           *This,
148   IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,
149   IN  UINT8                        BarIndex,
150   IN  UINT64                       Offset,
151   IN  UINT64                       Mask,
152   IN  UINT64                       Value,
153   IN  UINT64                       Delay,
154   OUT UINT64                       *Result
155   );
156 
157 /**
158   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
159 
160   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
161   @param  Width                 Signifies the width of the memory or I/O operations.
162   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
163                                 base address for the memory or I/O operation to perform.
164   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
165   @param  Count                 The number of memory or I/O operations to perform.
166   @param  Buffer                For read operations, the destination buffer to store the results. For write
167                                 operations, the source buffer to write data from.
168 
169   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
170   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
171   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
172                                 valid for the PCI BAR specified by BarIndex.
173   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
174   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
175 
176 **/
177 typedef
178 EFI_STATUS
179 (EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(
180   IN EFI_PCI_IO_PROTOCOL              *This,
181   IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
182   IN     UINT8                        BarIndex,
183   IN     UINT64                       Offset,
184   IN     UINTN                        Count,
185   IN OUT VOID                         *Buffer
186   );
187 
188 typedef struct {
189   ///
190   /// Read PCI controller registers in the PCI memory or I/O space.
191   ///
192   EFI_PCI_IO_PROTOCOL_IO_MEM    Read;
193   ///
194   /// Write PCI controller registers in the PCI memory or I/O space.
195   ///
196   EFI_PCI_IO_PROTOCOL_IO_MEM    Write;
197 } EFI_PCI_IO_PROTOCOL_ACCESS;
198 
199 /**
200   Enable a PCI driver to access PCI controller registers in PCI configuration space.
201 
202   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
203   @param  Width                 Signifies the width of the memory operations.
204   @param  Offset                The offset within the PCI configuration space for the PCI controller.
205   @param  Count                 The number of PCI configuration operations to perform.
206   @param  Buffer                For read operations, the destination buffer to store the results. For write
207                                 operations, the source buffer to write data from.
208 
209 
210   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
211   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
212                                 valid for the PCI configuration header of the PCI controller.
213   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
214   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
215 
216 **/
217 typedef
218 EFI_STATUS
219 (EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(
220   IN EFI_PCI_IO_PROTOCOL              *This,
221   IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
222   IN     UINT32                       Offset,
223   IN     UINTN                        Count,
224   IN OUT VOID                         *Buffer
225   );
226 
227 typedef struct {
228   ///
229   /// Read PCI controller registers in PCI configuration space.
230   ///
231   EFI_PCI_IO_PROTOCOL_CONFIG    Read;
232   ///
233   /// Write PCI controller registers in PCI configuration space.
234   ///
235   EFI_PCI_IO_PROTOCOL_CONFIG    Write;
236 } EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;
237 
238 /**
239   Enables a PCI driver to copy one region of PCI memory space to another region of PCI
240   memory space.
241 
242   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
243   @param  Width                 Signifies the width of the memory operations.
244   @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the
245                                 base address for the memory operation to perform.
246   @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to
247                                 start the memory writes for the copy operation.
248   @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the
249                                 base address for the memory operation to perform.
250   @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start
251                                 the memory reads for the copy operation.
252   @param  Count                 The number of memory operations to perform. Bytes moved is Width
253                                 size * Count, starting at DestOffset and SrcOffset.
254 
255   @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
256   @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.
257   @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.
258   @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count
259                                 is not valid for the PCI BAR specified by DestBarIndex.
260   @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is
261                                 not valid for the PCI BAR specified by SrcBarIndex.
262   @retval EFI_INVALID_PARAMETER Width is invalid.
263   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
264 
265 **/
266 typedef
267 EFI_STATUS
268 (EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(
269   IN EFI_PCI_IO_PROTOCOL              *This,
270   IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
271   IN     UINT8                        DestBarIndex,
272   IN     UINT64                       DestOffset,
273   IN     UINT8                        SrcBarIndex,
274   IN     UINT64                       SrcOffset,
275   IN     UINTN                        Count
276   );
277 
278 /**
279   Provides the PCI controller-specific addresses needed to access system memory.
280 
281   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
282   @param  Operation             Indicates if the bus master is going to read or write to system memory.
283   @param  HostAddress           The system memory address to map to the PCI controller.
284   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
285                                 that were mapped.
286   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
287                                 access the hosts HostAddress.
288   @param  Mapping               A resulting value to pass to Unmap().
289 
290   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
291   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
292   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
293   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
294   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
295 
296 **/
297 typedef
298 EFI_STATUS
299 (EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(
300   IN EFI_PCI_IO_PROTOCOL                *This,
301   IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
302   IN     VOID                           *HostAddress,
303   IN OUT UINTN                          *NumberOfBytes,
304   OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
305   OUT    VOID                           **Mapping
306   );
307 
308 /**
309   Completes the Map() operation and releases any corresponding resources.
310 
311   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
312   @param  Mapping               The mapping value returned from Map().
313 
314   @retval EFI_SUCCESS           The range was unmapped.
315   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
316 
317 **/
318 typedef
319 EFI_STATUS
320 (EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(
321   IN EFI_PCI_IO_PROTOCOL           *This,
322   IN  VOID                         *Mapping
323   );
324 
325 /**
326   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
327   or EfiPciOperationBusMasterCommonBuffer64 mapping.
328 
329   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
330   @param  Type                  This parameter is not used and must be ignored.
331   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
332                                 EfiRuntimeServicesData.
333   @param  Pages                 The number of pages to allocate.
334   @param  HostAddress           A pointer to store the base system memory address of the
335                                 allocated range.
336   @param  Attributes            The requested bit mask of attributes for the allocated range.
337 
338   @retval EFI_SUCCESS           The requested memory pages were allocated.
339   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
340                                 MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.
341   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
342   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
343 
344 **/
345 typedef
346 EFI_STATUS
347 (EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(
348   IN EFI_PCI_IO_PROTOCOL           *This,
349   IN  EFI_ALLOCATE_TYPE            Type,
350   IN  EFI_MEMORY_TYPE              MemoryType,
351   IN  UINTN                        Pages,
352   OUT VOID                         **HostAddress,
353   IN  UINT64                       Attributes
354   );
355 
356 /**
357   Frees memory that was allocated with AllocateBuffer().
358 
359   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
360   @param  Pages                 The number of pages to free.
361   @param  HostAddress           The base system memory address of the allocated range.
362 
363   @retval EFI_SUCCESS           The requested memory pages were freed.
364   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
365                                 was not allocated with AllocateBuffer().
366 
367 **/
368 typedef
369 EFI_STATUS
370 (EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(
371   IN EFI_PCI_IO_PROTOCOL           *This,
372   IN  UINTN                        Pages,
373   IN  VOID                         *HostAddress
374   );
375 
376 /**
377   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
378 
379   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
380 
381   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
382                                 bridge to system memory.
383   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
384                                 host bridge due to a hardware error.
385 
386 **/
387 typedef
388 EFI_STATUS
389 (EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(
390   IN EFI_PCI_IO_PROTOCOL  *This
391   );
392 
393 /**
394   Retrieves this PCI controller's current PCI bus number, device number, and function number.
395 
396   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
397   @param  SegmentNumber         The PCI controller's current PCI segment number.
398   @param  BusNumber             The PCI controller's current PCI bus number.
399   @param  DeviceNumber          The PCI controller's current PCI device number.
400   @param  FunctionNumber        The PCI controller's current PCI function number.
401 
402   @retval EFI_SUCCESS           The PCI controller location was returned.
403   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
404 
405 **/
406 typedef
407 EFI_STATUS
408 (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(
409   IN EFI_PCI_IO_PROTOCOL          *This,
410   OUT UINTN                       *SegmentNumber,
411   OUT UINTN                       *BusNumber,
412   OUT UINTN                       *DeviceNumber,
413   OUT UINTN                       *FunctionNumber
414   );
415 
416 /**
417   Performs an operation on the attributes that this PCI controller supports. The operations include
418   getting the set of supported attributes, retrieving the current attributes, setting the current
419   attributes, enabling attributes, and disabling attributes.
420 
421   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
422   @param  Operation             The operation to perform on the attributes for this PCI controller.
423   @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable
424                                 operations.
425   @param  Result                A pointer to the result mask of attributes that are returned for the Get
426                                 and Supported operations.
427 
428   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
429   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
430   @retval EFI_UNSUPPORTED       one or more of the bits set in
431                                 Attributes are not supported by this PCI controller or one of
432                                 its parent bridges when Operation is Set, Enable or Disable.
433 
434 **/
435 typedef
436 EFI_STATUS
437 (EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(
438   IN EFI_PCI_IO_PROTOCOL                       *This,
439   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
440   IN  UINT64                                   Attributes,
441   OUT UINT64                                   *Result OPTIONAL
442   );
443 
444 /**
445   Gets the attributes that this PCI controller supports setting on a BAR using
446   SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
447 
448   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
449   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
450                                 base address for resource range. The legal range for this field is 0..5.
451   @param  Supports              A pointer to the mask of attributes that this PCI controller supports
452                                 setting for this BAR with SetBarAttributes().
453   @param  Resources             A pointer to the resource descriptors that describe the current
454                                 configuration of this BAR of the PCI controller.
455 
456   @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI
457                                 controller supports are returned in Supports. If Resources
458                                 is not NULL, then the resource descriptors that the PCI
459                                 controller is currently using are returned in Resources.
460   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
461   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
462   @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate
463                                 Resources.
464 **/
465 typedef
466 EFI_STATUS
467 (EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(
468   IN EFI_PCI_IO_PROTOCOL             *This,
469   IN  UINT8                          BarIndex,
470   OUT UINT64                         *Supports  OPTIONAL,
471   OUT VOID                           **Resources OPTIONAL
472   );
473 
474 /**
475   Sets the attributes for a range of a BAR on a PCI controller.
476 
477   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
478   @param  Attributes            The mask of attributes to set for the resource range specified by
479                                 BarIndex, Offset, and Length.
480   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
481                                 base address for resource range. The legal range for this field is 0..5.
482   @param  Offset                A pointer to the BAR relative base address of the resource range to be
483                                 modified by the attributes specified by Attributes.
484   @param  Length                A pointer to the length of the resource range to be modified by the
485                                 attributes specified by Attributes.
486 
487   @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
488                                 range specified by BarIndex, Offset, and Length were
489                                 set on the PCI controller, and the actual resource range is returned
490                                 in Offset and Length.
491   @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
492   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
493   @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
494                                 resource range specified by BarIndex, Offset, and
495                                 Length.
496 
497 **/
498 typedef
499 EFI_STATUS
500 (EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(
501   IN EFI_PCI_IO_PROTOCOL              *This,
502   IN     UINT64                       Attributes,
503   IN     UINT8                        BarIndex,
504   IN OUT UINT64                       *Offset,
505   IN OUT UINT64                       *Length
506   );
507 
508 ///
509 /// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,
510 /// and DMA interfaces used to abstract accesses to PCI controllers.
511 /// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.
512 /// A device driver that wishes to manage a PCI controller in a system will have to
513 /// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.
514 ///
515 struct _EFI_PCI_IO_PROTOCOL {
516   EFI_PCI_IO_PROTOCOL_POLL_IO_MEM           PollMem;
517   EFI_PCI_IO_PROTOCOL_POLL_IO_MEM           PollIo;
518   EFI_PCI_IO_PROTOCOL_ACCESS                Mem;
519   EFI_PCI_IO_PROTOCOL_ACCESS                Io;
520   EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS         Pci;
521   EFI_PCI_IO_PROTOCOL_COPY_MEM              CopyMem;
522   EFI_PCI_IO_PROTOCOL_MAP                   Map;
523   EFI_PCI_IO_PROTOCOL_UNMAP                 Unmap;
524   EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER       AllocateBuffer;
525   EFI_PCI_IO_PROTOCOL_FREE_BUFFER           FreeBuffer;
526   EFI_PCI_IO_PROTOCOL_FLUSH                 Flush;
527   EFI_PCI_IO_PROTOCOL_GET_LOCATION          GetLocation;
528   EFI_PCI_IO_PROTOCOL_ATTRIBUTES            Attributes;
529   EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES    GetBarAttributes;
530   EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES    SetBarAttributes;
531 
532   ///
533   /// The size, in bytes, of the ROM image.
534   ///
535   UINT64                                    RomSize;
536 
537   ///
538   /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible
539   /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.
540   /// The contents of this buffer are either from the PCI option ROM that can be accessed
541   /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.
542   /// The Attributes() function can be used to determine from which of these two sources
543   /// the RomImage buffer was initialized.
544   ///
545   VOID    *RomImage;
546 };
547 
548 extern EFI_GUID  gEfiPciIoProtocolGuid;
549 
550 #endif
551