1//===- PPCTargetParser.def - PPC target parsing defines ---------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file provides defines to build up the PPC target parser's logic. 10// 11//===----------------------------------------------------------------------===// 12 13// NOTE: NO INCLUDE GUARD DESIRED! 14 15#ifdef PPC_TGT_PARSER_UNDEF_MACROS 16#undef PPC_LNX_FEATURE 17#undef PPC_CPU 18#undef PPC_FAWORD_HWCAP 19#undef PPC_FAWORD_HWCAP2 20#undef PPC_FAWORD_CPUID 21#undef PPC_HWCAP_OFFSET_LE32 22#undef PPC_HWCAP_OFFSET_LE64 23#undef PPC_HWCAP_OFFSET_BE32 24#undef PPC_HWCAP_OFFSET_BE64 25#undef PPC_HWCAP2_OFFSET_LE32 26#undef PPC_HWCAP2_OFFSET_LE64 27#undef PPC_HWCAP2_OFFSET_BE32 28#undef PPC_HWCAP2_OFFSET_BE64 29#undef PPC_CPUID_OFFSET_LE32 30#undef PPC_CPUID_OFFSET_LE64 31#undef PPC_CPUID_OFFSET_BE32 32#undef PPC_CPUID_OFFSET_BE64 33#undef BUILTIN_PPC_TRUE 34#undef BUILTIN_PPC_FALSE 35#undef USE_SYS_CONF 36#undef SYS_CALL 37#undef BUILTIN_PPC_UNSUPPORTED 38#undef AIX_SYSCON_IMPL_IDX 39#undef AIX_PPC7_VALUE 40#undef AIX_PPC8_VALUE 41#undef AIX_PPC9_VALUE 42#undef AIX_PPC10_VALUE 43#undef AIX_PPC11_VALUE 44#else 45#ifndef PPC_LNX_FEATURE 46#define PPC_LNX_FEATURE(NAME, DESC, ENUMNAME, ENUMVAL, HWCAPN) 47#endif 48#ifndef PPC_CPU 49#define PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID) 50#endif 51#ifndef PPC_FAWORD_HWCAP 52#define PPC_FAWORD_HWCAP 1 53#endif 54#ifndef PPC_FAWORD_HWCAP2 55#define PPC_FAWORD_HWCAP2 2 56#endif 57#ifndef PPC_FAWORD_CPUID 58#define PPC_FAWORD_CPUID 3 59#endif 60 61// PPC CPUs 62// 63// The value of SUPPORT_METHOD can be: 64// BUILTIN_PPC_TRUE : feature supported 65// BUILTIN_PPC_FALSE : feature not supported 66// USE_SYS_CONF : return value depends on comparing VALUE with the specified 67// data member of _system_configuration at INDEX, where the 68// data member is masked by Mask. 69// SYS_CALL : return value depends on comparing a VALUE with the return value 70// of calling `getsystemcfg` with the parameter INDEX, which is 71// then masked by Mask. 72// 73// USE_SYS_CONF is only a methond supported on AIX. 74// 75// Supported SUPPORT_METHOD values. 76#define BUILTIN_PPC_TRUE 1 77#define BUILTIN_PPC_FALSE 0 78#define USE_SYS_CONF 2 79#define SYS_CALL 3 80#define BUILTIN_PPC_UNSUPPORTED 4 81 82#define AIX_SYSCON_IMPL_IDX 1 83 84#define AIX_PPC7_VALUE 0x00008000 85#define AIX_PPC8_VALUE 0x00010000 86#define AIX_PPC9_VALUE 0x00020000 87#define AIX_PPC10_VALUE 0x00040000 88#define AIX_PPC11_VALUE 0x00080000 89 90// __builtin_cpu_is() and __builtin_cpu_supports() are supported only on Power7 and up on AIX. 91// PPC_CPU(Name, Linux_SUPPORT_METHOD, LinuxID, AIX_SUPPORT_METHOD, AIXID) 92PPC_CPU("power4",SYS_CALL,32,BUILTIN_PPC_FALSE,0) 93PPC_CPU("ppc970",SYS_CALL,33,BUILTIN_PPC_FALSE,0) 94PPC_CPU("power5",SYS_CALL,34,BUILTIN_PPC_FALSE,0) 95PPC_CPU("power5+",SYS_CALL,35,BUILTIN_PPC_FALSE,0) 96PPC_CPU("power6",SYS_CALL,36,BUILTIN_PPC_FALSE,0) 97PPC_CPU("ppc-cell-be",SYS_CALL,37,BUILTIN_PPC_FALSE,0) 98PPC_CPU("power6x",SYS_CALL,38,BUILTIN_PPC_FALSE,0) 99PPC_CPU("power7",SYS_CALL,39,USE_SYS_CONF,AIX_PPC7_VALUE) 100PPC_CPU("ppca2",SYS_CALL,40,BUILTIN_PPC_FALSE,0) 101PPC_CPU("ppc405",SYS_CALL,41,BUILTIN_PPC_FALSE,0) 102PPC_CPU("ppc440",SYS_CALL,42,BUILTIN_PPC_FALSE,0) 103PPC_CPU("ppc464",SYS_CALL,43,BUILTIN_PPC_FALSE,0) 104PPC_CPU("ppc476",SYS_CALL,44,BUILTIN_PPC_FALSE,0) 105PPC_CPU("power8",SYS_CALL,45,USE_SYS_CONF,AIX_PPC8_VALUE) 106PPC_CPU("power9",SYS_CALL,46,USE_SYS_CONF,AIX_PPC9_VALUE) 107PPC_CPU("power10",SYS_CALL,47,USE_SYS_CONF,AIX_PPC10_VALUE) 108PPC_CPU("power11",SYS_CALL,48,USE_SYS_CONF,AIX_PPC11_VALUE) 109#undef PPC_CPU 110 111// PPC features on Linux: 112// 113// PPC_LNX_FEATURE(Name, Description, EnumName, BitMask, PPC_FAWORD_WORD) 114PPC_LNX_FEATURE("4xxmac","4xx CPU has a Multiply Accumulator",PPCF_4XXMAC,0x02000000,PPC_FAWORD_HWCAP) 115PPC_LNX_FEATURE("altivec","CPU has a SIMD/Vector Unit",PPCF_ALTIVEC,0x10000000,PPC_FAWORD_HWCAP) 116PPC_LNX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",PPCF_ARCH205,0x00001000,PPC_FAWORD_HWCAP) 117PPC_LNX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",PPCF_ARCH206,0x00000100,PPC_FAWORD_HWCAP) 118PPC_LNX_FEATURE("arch_2_07","CPU supports ISA 207 (eg, POWER8)",PPCF_ARCH207,0x80000000,PPC_FAWORD_HWCAP2) 119PPC_LNX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)",PPCF_ARCH30,0x00800000,PPC_FAWORD_HWCAP2) 120PPC_LNX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)",PPCF_ARCH31,0x00040000,PPC_FAWORD_HWCAP2) 121PPC_LNX_FEATURE("archpmu","CPU supports the set of compatible performance monitoring events",PPCF_ARCHPMU,0x00000040,PPC_FAWORD_HWCAP) 122PPC_LNX_FEATURE("booke","CPU supports the Embedded ISA category",PPCF_BOOKE,0x00008000,PPC_FAWORD_HWCAP) 123PPC_LNX_FEATURE("cellbe","CPU has a CELL broadband engine",PPCF_CELLBE,0x00010000,PPC_FAWORD_HWCAP) 124PPC_LNX_FEATURE("darn","CPU supports the darn (deliver a random number) instruction",PPCF_DARN,0x00200000,PPC_FAWORD_HWCAP2) 125PPC_LNX_FEATURE("dfp","CPU has a decimal floating point unit",PPCF_DFP,0x00000400,PPC_FAWORD_HWCAP) 126PPC_LNX_FEATURE("dscr","CPU supports the data stream control register",PPCF_DSCR,0x20000000,PPC_FAWORD_HWCAP2) 127PPC_LNX_FEATURE("ebb","CPU supports event base branching",PPCF_EBB,0x10000000,PPC_FAWORD_HWCAP2) 128PPC_LNX_FEATURE("efpdouble","CPU has a SPE double precision floating point unit",PPCF_EFPDOUBLE,0x00200000,PPC_FAWORD_HWCAP) 129PPC_LNX_FEATURE("efpsingle","CPU has a SPE single precision floating point unit",PPCF_EFPSINGLE,0x00400000,PPC_FAWORD_HWCAP) 130PPC_LNX_FEATURE("fpu","CPU has a floating point unit",PPCF_FPU,0x08000000,PPC_FAWORD_HWCAP) 131PPC_LNX_FEATURE("htm","CPU has hardware transaction memory instructions",PPCF_HTM,0x40000000,PPC_FAWORD_HWCAP2) 132PPC_LNX_FEATURE("htm-nosc","Kernel aborts hardware transactions when a syscall is made",PPCF_HTM_NOSC,0x01000000,PPC_FAWORD_HWCAP2) 133PPC_LNX_FEATURE("htm-no-suspend","CPU supports hardware transaction memory but does not support the tsuspend instruction.",PPCF_HTM_NO_SUSPEND,0x00080000,PPC_FAWORD_HWCAP2) 134PPC_LNX_FEATURE("ic_snoop","CPU supports icache snooping capabilities",PPCF_IC_SNOOP,0x00002000,PPC_FAWORD_HWCAP) 135PPC_LNX_FEATURE("ieee128","CPU supports 128-bit IEEE binary floating point instructions",PPCF_IEEE128,0x00400000,PPC_FAWORD_HWCAP2) 136PPC_LNX_FEATURE("isel","CPU supports the integer select instruction",PPCF_ISEL,0x08000000,PPC_FAWORD_HWCAP2) 137PPC_LNX_FEATURE("mma","CPU supports the matrix-multiply assist instructions",PPCF_MMA,0x00020000,PPC_FAWORD_HWCAP2) 138PPC_LNX_FEATURE("mmu","CPU has a memory management unit",PPCF_MMU,0x04000000,PPC_FAWORD_HWCAP) 139PPC_LNX_FEATURE("notb","CPU does not have a timebase (eg, 601 and 403gx)",PPCF_NOTB,0x00100000,PPC_FAWORD_HWCAP) 140PPC_LNX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE ISA",PPCF_PA6T,0x00000800,PPC_FAWORD_HWCAP) 141PPC_LNX_FEATURE("power4","CPU supports ISA 200 (eg, POWER4)",PPCF_POWER4,0x00080000,PPC_FAWORD_HWCAP) 142PPC_LNX_FEATURE("power5","CPU supports ISA 202 (eg, POWER5)",PPCF_POWER5,0x00040000,PPC_FAWORD_HWCAP) 143PPC_LNX_FEATURE("power5+","CPU supports ISA 203 (eg, POWER5+)",PPCF_POWER5P,0x00020000,PPC_FAWORD_HWCAP) 144PPC_LNX_FEATURE("power6x","CPU supports ISA 205 (eg, POWER6) extended opcodes mffgpr and mftgpr.",PPCF_POWER6X,0x00000200,PPC_FAWORD_HWCAP) 145PPC_LNX_FEATURE("ppc32","CPU supports 32-bit mode execution",PPCF_PPC32,0x80000000,PPC_FAWORD_HWCAP) 146PPC_LNX_FEATURE("ppc601","CPU supports the old POWER ISA (eg, 601)",PPCF_PPC601,0x20000000,PPC_FAWORD_HWCAP) 147PPC_LNX_FEATURE("ppc64","CPU supports 64-bit mode execution",PPCF_PPC64,0x40000000,PPC_FAWORD_HWCAP) 148PPC_LNX_FEATURE("ppcle","CPU supports a little-endian mode that uses address swizzling",PPCF_PPCLE,0x00000001,PPC_FAWORD_HWCAP) 149PPC_LNX_FEATURE("scv","Kernel supports system call vectored",PPCF_SCV,0x00100000,PPC_FAWORD_HWCAP2) 150PPC_LNX_FEATURE("smt","CPU support simultaneous multi-threading",PPCF_SMT,0x00004000,PPC_FAWORD_HWCAP) 151PPC_LNX_FEATURE("spe","CPU has a signal processing extension unit",PPCF_SPE,0x00800000,PPC_FAWORD_HWCAP) 152PPC_LNX_FEATURE("tar","CPU supports the target address register",PPCF_TAR,0x04000000,PPC_FAWORD_HWCAP2) 153PPC_LNX_FEATURE("true_le","CPU supports true little-endian mode",PPCF_TRUE_LE,0x00000002,PPC_FAWORD_HWCAP) 154PPC_LNX_FEATURE("ucache","CPU has unified I/D cache",PPCF_UCACHE,0x01000000,PPC_FAWORD_HWCAP) 155PPC_LNX_FEATURE("vcrypto","CPU supports the vector cryptography instructions",PPCF_VCRYPTO,0x02000000,PPC_FAWORD_HWCAP2) 156PPC_LNX_FEATURE("vsx","CPU supports the vector-scalar extension",PPCF_VSX,0x00000080,PPC_FAWORD_HWCAP) 157 158#ifdef PPC_LNX_DEFINE_OFFSETS 159# define PPC_HWCAP_OFFSET_LE32 -0x703C 160# define PPC_HWCAP_OFFSET_LE64 -0x7064 161# define PPC_HWCAP_OFFSET_BE32 -0x7040 162# define PPC_HWCAP_OFFSET_BE64 -0x7068 163# define PPC_HWCAP2_OFFSET_LE32 -0x7040 164# define PPC_HWCAP2_OFFSET_LE64 -0x7068 165# define PPC_HWCAP2_OFFSET_BE32 -0x703C 166# define PPC_HWCAP2_OFFSET_BE64 -0x7064 167# define PPC_CPUID_OFFSET_LE32 -0x7034 168# define PPC_CPUID_OFFSET_LE64 -0x705C 169# define PPC_CPUID_OFFSET_BE32 -0x7034 170# define PPC_CPUID_OFFSET_BE64 -0x705C 171#endif 172#undef PPC_LNX_DEFINE_OFFSETS 173#undef PPC_LNX_FEATURE 174 175// PPC features on AIX 176// 177// Definition of the following values are found in the AIX header 178// file: </usr/include/sys/systemcfg.h>. 179#ifndef AIX_POWERPC_USE_SYS_CONF 180 #define AIX_POWERPC_USE_SYS_CONF 181 #define AIX_SYSCON_CACHE_IDX 5 182 #define AIX_SYSCON_SMT_IDX 44 183 #define AIX_SYSCON_VMX_IDX 46 184 #define AIX_SYSCON_DFP_IDX 53 185 186 #define SYS_CALL_TM_VER 59 187 #define SYS_CALL_MMA_VER 62 188#endif 189 190#ifndef PPC_AIX_FEATURE 191#define PPC_AIX_FEATURE(NAME,DESC,SUPPORT_METHOD,INDEX,MASK,COMPARE_OP,VALUE) 192#endif 193 194PPC_AIX_FEATURE("4xxmac","4xx CPU has a Multiply Accumulator",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 195PPC_AIX_FEATURE("altivec","CPU has a SIMD/Vector Unit",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::ICMP_UGT,0) 196PPC_AIX_FEATURE("arch_2_05","CPU supports ISA 205 (eg, POWER6)",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 197PPC_AIX_FEATURE("arch_2_06","CPU supports ISA 206 (eg, POWER7)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC7_VALUE) 198PPC_AIX_FEATURE("arch_2_07","CPU supports ISA 207 (eg, POWER8)",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE) 199PPC_AIX_FEATURE("arch_3_00","CPU supports ISA 30 (eg, POWER9)", USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC9_VALUE) 200PPC_AIX_FEATURE("arch_3_1","CPU supports ISA 31 (eg, POWER10)", USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC10_VALUE) 201PPC_AIX_FEATURE("booke","CPU supports the Embedded ISA category",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 202PPC_AIX_FEATURE("cellbe","CPU has a CELL broadband engine",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 203PPC_AIX_FEATURE("darn","CPU supports the darn (deliver a random number) instruction",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC9_VALUE) 204PPC_AIX_FEATURE("dfp","CPU has a decimal floating point unit",USE_SYS_CONF,AIX_SYSCON_DFP_IDX,0,ICmpInst::ICMP_NE,0) 205PPC_AIX_FEATURE("dscr","CPU supports the data stream control register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE) 206PPC_AIX_FEATURE("ebb","CPU supports event base branching",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE) 207PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point unit",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 208PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point unit",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 209PPC_AIX_FEATURE("fpu","CPU has a floating point unit",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 210PPC_AIX_FEATURE("htm","CPU has hardware transaction memory instructions",SYS_CALL,SYS_CALL_TM_VER,0,ICmpInst::ICMP_UGT,0) 211PPC_AIX_FEATURE("isel","CPU supports the integer select instruction",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 212PPC_AIX_FEATURE("mma","CPU supports the matrix-multiply assist instructions",SYS_CALL,SYS_CALL_MMA_VER,0,ICmpInst::ICMP_UGT,0) 213PPC_AIX_FEATURE("mmu","CPU has a memory management unit",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 214PPC_AIX_FEATURE("pa6t","CPU supports the PA Semi 6T CORE ISA",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 215PPC_AIX_FEATURE("power4","CPU supports ISA 200 (eg, POWER4)",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 216PPC_AIX_FEATURE("power5","CPU supports ISA 202 (eg, POWER5)",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 217PPC_AIX_FEATURE("power5+","CPU supports ISA 203 (eg, POWER5+)",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 218PPC_AIX_FEATURE("power6x","CPU supports ISA 205 (eg, POWER6)",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 219PPC_AIX_FEATURE("ppc32","CPU supports 32-bit mode execution",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 220PPC_AIX_FEATURE("ppc601","CPU supports the old POWER ISA (eg, 601)",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 221PPC_AIX_FEATURE("ppc64","CPU supports 64-bit mode execution",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 222PPC_AIX_FEATURE("ppcle","CPU supports a little-endian mode that uses address swizzling",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 223PPC_AIX_FEATURE("smt","CPU supports simultaneous multi-threading",USE_SYS_CONF,AIX_SYSCON_SMT_IDX,0x3,ICmpInst::ICMP_EQ,0x3) 224PPC_AIX_FEATURE("spe","CPU has a signal processing extension unit",BUILTIN_PPC_FALSE,0,0,CmpInst::Predicate(),0) 225PPC_AIX_FEATURE("tar","CPU supports the target address register",USE_SYS_CONF,AIX_SYSCON_IMPL_IDX,0,ICmpInst::ICMP_UGE,AIX_PPC8_VALUE) 226PPC_AIX_FEATURE("true_le","CPU supports true little-endian mode",BUILTIN_PPC_TRUE,0,0,CmpInst::Predicate(),0) 227PPC_AIX_FEATURE("ucache","CPU has unified I/D cache",USE_SYS_CONF,AIX_SYSCON_CACHE_IDX,0x00000002,ICmpInst::ICMP_EQ,0x00000002) 228PPC_AIX_FEATURE("vsx","CPU supports the vector-scalar extension",USE_SYS_CONF,AIX_SYSCON_VMX_IDX,0,ICmpInst::ICMP_UGT,1) 229#undef PPC_AIX_FEATURE 230 231// PPC_SYSTEMCONFIG_TYPE defines the IR data structure of kernel variable 232// `_system_configuration`, that is found in the AIX OS header file: </usr/include/sys/systemcfg.h>. 233#ifndef PPC_SYSTEMCONFIG_TYPE 234#define PPC_SYSTEMCONFIG_TYPE \ 235Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \ 236Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \ 237Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \ 238Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \ 239Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, \ 240Int32Ty, Int32Ty, Int64Ty, Int32Ty, Int32Ty, Int32Ty, \ 241Int32Ty, Int64Ty, Int64Ty, Int64Ty, Int64Ty, Int32Ty, \ 242Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int32Ty, Int64Ty, \ 243Int32Ty, Int8Ty, Int8Ty, Int8Ty, Int8Ty, Int32Ty, \ 244Int32Ty, Int16Ty, Int16Ty, llvm::ArrayType::get(Int32Ty,3), Int32Ty 245#endif 246 247#endif // !PPC_TGT_PARSER_UNDEF_MACROS 248