1//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the subset of the 32-bit PowerPC instruction set, as used 10// by the PowerPC instruction selector. 11// 12//===----------------------------------------------------------------------===// 13 14include "PPCInstrFormats.td" 15 16//===----------------------------------------------------------------------===// 17// PowerPC specific type constraints. 18// 19def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx 20 SDTCisVT<0, f64>, SDTCisPtrTy<1> 21]>; 22def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x 23 SDTCisVT<0, f64>, SDTCisPtrTy<1> 24]>; 25def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ 26 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 27]>; 28def SDT_PPCstxsix : SDTypeProfile<0, 3, [ 29 SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 30]>; 31def SDT_PPCcv_fp_to_int : SDTypeProfile<1, 1, [ 32 SDTCisFP<0>, SDTCisFP<1> 33 ]>; 34def SDT_PPCstore_scal_int_from_vsr : SDTypeProfile<0, 3, [ 35 SDTCisFP<0>, SDTCisPtrTy<1>, SDTCisPtrTy<2> 36]>; 37def SDT_PPCVexts : SDTypeProfile<1, 2, [ 38 SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> 39]>; 40 41def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 42 SDTCisVT<1, i32> ]>; 43def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 44 SDTCisVT<1, i32> ]>; 45def SDT_PPCvperm : SDTypeProfile<1, 3, [ 46 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2> 47]>; 48 49def SDT_PPCVecSplat : SDTypeProfile<1, 2, [ SDTCisVec<0>, 50 SDTCisVec<1>, SDTCisInt<2> 51]>; 52 53def SDT_PPCSpToDp : SDTypeProfile<1, 1, [ SDTCisVT<0, v2f64>, 54 SDTCisInt<1> 55]>; 56 57def SDT_PPCVecShift : SDTypeProfile<1, 3, [ SDTCisVec<0>, 58 SDTCisVec<1>, SDTCisVec<2>, SDTCisPtrTy<3> 59]>; 60 61def SDT_PPCVecInsert : SDTypeProfile<1, 3, [ SDTCisVec<0>, 62 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 63]>; 64 65def SDT_PPCxxpermdi: SDTypeProfile<1, 3, [ SDTCisVec<0>, 66 SDTCisVec<1>, SDTCisVec<2>, SDTCisInt<3> 67]>; 68 69def SDT_PPCvcmp : SDTypeProfile<1, 3, [ 70 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32> 71]>; 72 73def SDT_PPCcondbr : SDTypeProfile<0, 3, [ 74 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT> 75]>; 76 77def SDT_PPCFtsqrt : SDTypeProfile<1, 1, [ 78 SDTCisVT<0, i32>]>; 79 80def SDT_PPClbrx : SDTypeProfile<1, 2, [ 81 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 82]>; 83def SDT_PPCstbrx : SDTypeProfile<0, 3, [ 84 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT> 85]>; 86def SDT_StoreCond : SDTypeProfile<0, 3, [ 87 SDTCisPtrTy<0>, SDTCisInt<1>, SDTCisPtrTy<2> 88]>; 89 90def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ 91 SDTCisPtrTy<0>, SDTCisVT<1, i32> 92]>; 93 94def tocentry32 : Operand<iPTR> { 95 let MIOperandInfo = (ops i32imm:$imm); 96} 97 98def SDT_PPCqvfperm : SDTypeProfile<1, 3, [ 99 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisVec<3> 100]>; 101def SDT_PPCqvgpci : SDTypeProfile<1, 1, [ 102 SDTCisVec<0>, SDTCisInt<1> 103]>; 104def SDT_PPCqvaligni : SDTypeProfile<1, 3, [ 105 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<3> 106]>; 107def SDT_PPCqvesplati : SDTypeProfile<1, 2, [ 108 SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2> 109]>; 110 111def SDT_PPCqbflt : SDTypeProfile<1, 1, [ 112 SDTCisVec<0>, SDTCisVec<1> 113]>; 114 115def SDT_PPCqvlfsb : SDTypeProfile<1, 1, [ 116 SDTCisVec<0>, SDTCisPtrTy<1> 117]>; 118 119def SDT_PPCextswsli : SDTypeProfile<1, 2, [ // extswsli 120 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisInt<2> 121]>; 122 123def SDT_PPCFPMinMax : SDTypeProfile<1, 2, [ 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125]>; 126 127// RES, CARRY = op LHS, RHS 128def SDT_PPCBinaryArithWithFlagsOut : SDTypeProfile<2, 2, [ 129 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 130 SDTCisInt<0>, 131 SDTCisVT<1, i32>, 132]>; 133 134// RES, CARRY = op LHS, RHS, CARRY 135def SDT_PPCBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [ 136 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 137 SDTCisInt<0>, 138 SDTCisSameAs<1, 4>, 139 SDTCisVT<1, i32>, 140]>; 141 142//===----------------------------------------------------------------------===// 143// PowerPC specific DAG Nodes. 144// 145 146def PPCfre : SDNode<"PPCISD::FRE", SDTFPUnaryOp, []>; 147def PPCfrsqrte: SDNode<"PPCISD::FRSQRTE", SDTFPUnaryOp, []>; 148def PPCfsqrt : SDNode<"PPCISD::FSQRT", SDTFPUnaryOp, []>; 149def PPCftsqrt : SDNode<"PPCISD::FTSQRT", SDT_PPCFtsqrt,[]>; 150 151def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; 152def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; 153def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; 154def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; 155def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; 156def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; 157def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; 158def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; 159 160def PPCstrict_fcfid : SDNode<"PPCISD::STRICT_FCFID", 161 SDTFPUnaryOp, [SDNPHasChain]>; 162def PPCstrict_fcfidu : SDNode<"PPCISD::STRICT_FCFIDU", 163 SDTFPUnaryOp, [SDNPHasChain]>; 164def PPCstrict_fcfids : SDNode<"PPCISD::STRICT_FCFIDS", 165 SDTFPRoundOp, [SDNPHasChain]>; 166def PPCstrict_fcfidus : SDNode<"PPCISD::STRICT_FCFIDUS", 167 SDTFPRoundOp, [SDNPHasChain]>; 168 169def PPCany_fcfid : PatFrags<(ops node:$op), 170 [(PPCfcfid node:$op), 171 (PPCstrict_fcfid node:$op)]>; 172def PPCany_fcfidu : PatFrags<(ops node:$op), 173 [(PPCfcfidu node:$op), 174 (PPCstrict_fcfidu node:$op)]>; 175def PPCany_fcfids : PatFrags<(ops node:$op), 176 [(PPCfcfids node:$op), 177 (PPCstrict_fcfids node:$op)]>; 178def PPCany_fcfidus : PatFrags<(ops node:$op), 179 [(PPCfcfidus node:$op), 180 (PPCstrict_fcfidus node:$op)]>; 181 182def PPCstore_scal_int_from_vsr: 183 SDNode<"PPCISD::ST_VSR_SCAL_INT", SDT_PPCstore_scal_int_from_vsr, 184 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 185def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx, 186 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 187def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, 188 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 189def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, 190 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 191def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, 192 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 193def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, 194 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 195def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; 196 197// Extract FPSCR (not modeled at the DAG level). 198def PPCmffs : SDNode<"PPCISD::MFFS", 199 SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>, 200 [SDNPHasChain]>; 201 202// Perform FADD in round-to-zero mode. 203def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp, []>; 204def PPCstrict_faddrtz: SDNode<"PPCISD::STRICT_FADDRTZ", SDTFPBinOp, 205 [SDNPHasChain]>; 206 207def PPCany_faddrtz: PatFrags<(ops node:$lhs, node:$rhs), 208 [(PPCfaddrtz node:$lhs, node:$rhs), 209 (PPCstrict_faddrtz node:$lhs, node:$rhs)]>; 210 211def PPCfsel : SDNode<"PPCISD::FSEL", 212 // Type constraint for fsel. 213 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, 214 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>; 215def PPCxsmaxc : SDNode<"PPCISD::XSMAXC", SDT_PPCFPMinMax, []>; 216def PPCxsminc : SDNode<"PPCISD::XSMINC", SDT_PPCFPMinMax, []>; 217def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>; 218def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>; 219def PPCtoc_entry: SDNode<"PPCISD::TOC_ENTRY", SDTIntBinOp, 220 [SDNPMayLoad, SDNPMemOperand]>; 221 222def PPCppc32GOT : SDNode<"PPCISD::PPC32_GOT", SDTIntLeaf, []>; 223 224def PPCaddisGotTprelHA : SDNode<"PPCISD::ADDIS_GOT_TPREL_HA", SDTIntBinOp>; 225def PPCldGotTprelL : SDNode<"PPCISD::LD_GOT_TPREL_L", SDTIntBinOp, 226 [SDNPMayLoad]>; 227def PPCaddTls : SDNode<"PPCISD::ADD_TLS", SDTIntBinOp, []>; 228def PPCaddisTlsgdHA : SDNode<"PPCISD::ADDIS_TLSGD_HA", SDTIntBinOp>; 229def PPCaddiTlsgdL : SDNode<"PPCISD::ADDI_TLSGD_L", SDTIntBinOp>; 230def PPCgetTlsAddr : SDNode<"PPCISD::GET_TLS_ADDR", SDTIntBinOp>; 231def PPCgetTlsMod : SDNode<"PPCISD::GET_TLS_MOD_AIX", SDTIntUnaryOp>; 232def PPCgetTpointer : SDNode<"PPCISD::GET_TPOINTER", SDTIntLeaf, []>; 233def PPCaddiTlsgdLAddr : SDNode<"PPCISD::ADDI_TLSGD_L_ADDR", 234 SDTypeProfile<1, 3, [ 235 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 236 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 237def PPCTlsgdAIX : SDNode<"PPCISD::TLSGD_AIX", SDTIntBinOp>; 238def PPCTlsldAIX : SDNode<"PPCISD::TLSLD_AIX", SDTIntUnaryOp>; 239def PPCaddisTlsldHA : SDNode<"PPCISD::ADDIS_TLSLD_HA", SDTIntBinOp>; 240def PPCaddiTlsldL : SDNode<"PPCISD::ADDI_TLSLD_L", SDTIntBinOp>; 241def PPCgetTlsldAddr : SDNode<"PPCISD::GET_TLSLD_ADDR", SDTIntBinOp>; 242def PPCaddiTlsldLAddr : SDNode<"PPCISD::ADDI_TLSLD_L_ADDR", 243 SDTypeProfile<1, 3, [ 244 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 245 SDTCisSameAs<0, 3>, SDTCisInt<0> ]>>; 246def PPCaddisDtprelHA : SDNode<"PPCISD::ADDIS_DTPREL_HA", SDTIntBinOp>; 247def PPCaddiDtprelL : SDNode<"PPCISD::ADDI_DTPREL_L", SDTIntBinOp>; 248def PPCpaddiDtprel : SDNode<"PPCISD::PADDI_DTPREL", SDTIntBinOp>; 249 250def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>; 251def PPCxxsplt : SDNode<"PPCISD::XXSPLT", SDT_PPCVecSplat, []>; 252def PPCxxspltidp : SDNode<"PPCISD::XXSPLTI_SP_TO_DP", SDT_PPCSpToDp, []>; 253def PPCvecinsert : SDNode<"PPCISD::VECINSERT", SDT_PPCVecInsert, []>; 254def PPCxxpermdi : SDNode<"PPCISD::XXPERMDI", SDT_PPCxxpermdi, []>; 255def PPCvecshl : SDNode<"PPCISD::VECSHL", SDT_PPCVecShift, []>; 256 257def PPCcmpb : SDNode<"PPCISD::CMPB", SDTIntBinOp, []>; 258 259// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift 260// amounts. These nodes are generated by the multi-precision shift code. 261def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>; 262def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>; 263def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>; 264 265def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>; 266 267def PPCextswsli : SDNode<"PPCISD::EXTSWSLI" , SDT_PPCextswsli>; 268 269def PPCstrict_fctidz : SDNode<"PPCISD::STRICT_FCTIDZ", 270 SDTFPUnaryOp, [SDNPHasChain]>; 271def PPCstrict_fctiwz : SDNode<"PPCISD::STRICT_FCTIWZ", 272 SDTFPUnaryOp, [SDNPHasChain]>; 273def PPCstrict_fctiduz : SDNode<"PPCISD::STRICT_FCTIDUZ", 274 SDTFPUnaryOp, [SDNPHasChain]>; 275def PPCstrict_fctiwuz : SDNode<"PPCISD::STRICT_FCTIWUZ", 276 SDTFPUnaryOp, [SDNPHasChain]>; 277 278def PPCany_fctidz : PatFrags<(ops node:$op), 279 [(PPCstrict_fctidz node:$op), 280 (PPCfctidz node:$op)]>; 281def PPCany_fctiwz : PatFrags<(ops node:$op), 282 [(PPCstrict_fctiwz node:$op), 283 (PPCfctiwz node:$op)]>; 284def PPCany_fctiduz : PatFrags<(ops node:$op), 285 [(PPCstrict_fctiduz node:$op), 286 (PPCfctiduz node:$op)]>; 287def PPCany_fctiwuz : PatFrags<(ops node:$op), 288 [(PPCstrict_fctiwuz node:$op), 289 (PPCfctiwuz node:$op)]>; 290 291// Move 2 i64 values into a VSX register 292def PPCbuild_fp128: SDNode<"PPCISD::BUILD_FP128", 293 SDTypeProfile<1, 2, 294 [SDTCisFP<0>, SDTCisSameSizeAs<1,2>, 295 SDTCisSameAs<1,2>]>, 296 []>; 297 298def PPCbuild_spe64: SDNode<"PPCISD::BUILD_SPE64", 299 SDTypeProfile<1, 2, 300 [SDTCisVT<0, f64>, SDTCisVT<1,i32>, 301 SDTCisVT<1,i32>]>, 302 []>; 303 304def PPCextract_spe : SDNode<"PPCISD::EXTRACT_SPE", 305 SDTypeProfile<1, 2, 306 [SDTCisVT<0, i32>, SDTCisVT<1, f64>, 307 SDTCisPtrTy<2>]>, 308 []>; 309 310// These are target-independent nodes, but have target-specific formats. 311def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart, 312 [SDNPHasChain, SDNPOutGlue]>; 313def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd, 314 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 315 316def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; 317def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall, 318 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 319 SDNPVariadic]>; 320def PPCcall_nop : SDNode<"PPCISD::CALL_NOP", SDT_PPCCall, 321 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 322 SDNPVariadic]>; 323def PPCcall_notoc : SDNode<"PPCISD::CALL_NOTOC", SDT_PPCCall, 324 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 325 SDNPVariadic]>; 326def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall, 327 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 328def PPCbctrl : SDNode<"PPCISD::BCTRL", SDTNone, 329 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 330 SDNPVariadic]>; 331def PPCbctrl_load_toc : SDNode<"PPCISD::BCTRL_LOAD_TOC", 332 SDTypeProfile<0, 1, []>, 333 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 334 SDNPVariadic]>; 335 336// Call nodes for strictfp calls (that define RM). 337def PPCcall_rm : SDNode<"PPCISD::CALL_RM", SDT_PPCCall, 338 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 339 SDNPVariadic]>; 340def PPCcall_nop_rm : SDNode<"PPCISD::CALL_NOP_RM", SDT_PPCCall, 341 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 342 SDNPVariadic]>; 343def PPCcall_notoc_rm : SDNode<"PPCISD::CALL_NOTOC_RM", SDT_PPCCall, 344 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 345 SDNPVariadic]>; 346def PPCbctrl_rm : SDNode<"PPCISD::BCTRL_RM", SDTNone, 347 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 348 SDNPVariadic]>; 349def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", 350 SDTypeProfile<0, 1, []>, 351 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 352 SDNPVariadic]>; 353 354def PPCretglue : SDNode<"PPCISD::RET_GLUE", SDTNone, 355 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 356 357def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, 358 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 359 360def PPCeh_sjlj_setjmp : SDNode<"PPCISD::EH_SJLJ_SETJMP", 361 SDTypeProfile<1, 1, [SDTCisInt<0>, 362 SDTCisPtrTy<1>]>, 363 [SDNPHasChain, SDNPSideEffect]>; 364def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP", 365 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 366 [SDNPHasChain, SDNPSideEffect]>; 367 368def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 369def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc, 370 [SDNPHasChain, SDNPSideEffect]>; 371 372def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone, 373 [SDNPHasChain, SDNPSideEffect]>; 374def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>; 375def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc, 376 [SDNPHasChain, SDNPSideEffect]>; 377 378def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>; 379def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>; 380 381def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr, 382 [SDNPHasChain, SDNPOptInGlue]>; 383 384// PPC-specific atomic operations. 385def PPCatomicCmpSwap_8 : 386 SDNode<"PPCISD::ATOMIC_CMP_SWAP_8", SDTAtomic3, 387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 388def PPCatomicCmpSwap_16 : 389 SDNode<"PPCISD::ATOMIC_CMP_SWAP_16", SDTAtomic3, 390 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 391def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, 392 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 393def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, 394 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 395def PPCStoreCond : SDNode<"PPCISD::STORE_COND", SDT_StoreCond, 396 [SDNPHasChain, SDNPMayStore, 397 SDNPMemOperand, SDNPOutGlue]>; 398 399// Instructions to set/unset CR bit 6 for SVR4 vararg calls 400def PPCcr6set : SDNode<"PPCISD::CR6SET", SDTNone, 401 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 402def PPCcr6unset : SDNode<"PPCISD::CR6UNSET", SDTNone, 403 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 404 405// Instructions to support dynamic alloca. 406def SDTDynOp : SDTypeProfile<1, 2, []>; 407def SDTDynAreaOp : SDTypeProfile<1, 1, []>; 408def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>; 409def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>; 410def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>; 411 412// PC Relative Specific Nodes 413def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>; 414def PPCtlsdynamatpcreladdr : SDNode<"PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR", 415 SDTIntUnaryOp, []>; 416def PPCtlslocalexecmataddr : SDNode<"PPCISD::TLS_LOCAL_EXEC_MAT_ADDR", 417 SDTIntUnaryOp, []>; 418 419def PPCaddc : SDNode<"PPCISD::ADDC", SDT_PPCBinaryArithWithFlagsOut, 420 [SDNPCommutative]>; 421def PPCadde : SDNode<"PPCISD::ADDE", SDT_PPCBinaryArithWithFlagsInOut, 422 []>; 423def PPCsubc : SDNode<"PPCISD::SUBC", SDT_PPCBinaryArithWithFlagsOut, 424 []>; 425def PPCsube : SDNode<"PPCISD::SUBE", SDT_PPCBinaryArithWithFlagsInOut, 426 []>; 427 428//===----------------------------------------------------------------------===// 429// PowerPC specific transformation functions and pattern fragments. 430// 431 432// A floating point immediate that is not a positive zero and can be converted 433// to a single precision floating point non-denormal immediate without loss of 434// information. 435def nzFPImmAsi32 : PatLeaf<(fpimm), [{ 436 APFloat APFloatOfN = N->getValueAPF(); 437 return convertToNonDenormSingle(APFloatOfN) && !N->isExactlyValue(+0.0); 438}]>; 439 440// A floating point immediate that is exactly an integer (for example 3.0, -5.0) 441// and can be represented in 5 bits (range of [-16, 15]). 442def nzFPImmExactInti5 : PatLeaf<(fpimm), [{ 443 APFloat FloatValue = N->getValueAPF(); 444 bool IsExact; 445 APSInt IntResult(16, false); 446 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 447 return IsExact && IntResult <= 15 && IntResult >= -16 && !FloatValue.isZero(); 448}]>; 449 450def getFPAs5BitExactInt : SDNodeXForm<fpimm, [{ 451 APFloat FloatValue = N->getValueAPF(); 452 bool IsExact; 453 APSInt IntResult(32, false); 454 FloatValue.convertToInteger(IntResult, APFloat::rmTowardZero, &IsExact); 455 return CurDAG->getTargetConstant(IntResult, SDLoc(N), MVT::i32); 456}]>; 457 458// Convert the floating point immediate into a 32 bit floating point immediate 459// and get a i32 with the resulting bits. 460def getFPAs32BitInt : SDNodeXForm<fpimm, [{ 461 APFloat APFloatOfN = N->getValueAPF(); 462 convertToNonDenormSingle(APFloatOfN); 463 return CurDAG->getTargetConstant(APFloatOfN.bitcastToAPInt().getZExtValue(), 464 SDLoc(N), MVT::i32); 465}]>; 466 467// Check if the value can be converted to be single precision immediate, which 468// can be exploited by XXSPLTIDP. Ensure that it cannot be converted to single 469// precision before exploiting with XXSPLTI32DX. 470def nzFPImmAsi64 : PatLeaf<(fpimm), [{ 471 APFloat APFloatOfN = N->getValueAPF(); 472 return !N->isExactlyValue(+0.0) && !checkConvertToNonDenormSingle(APFloatOfN); 473}]>; 474 475// Get the Hi bits of a 64 bit immediate. 476def getFPAs64BitIntHi : SDNodeXForm<fpimm, [{ 477 APFloat APFloatOfN = N->getValueAPF(); 478 bool Unused; 479 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 480 &Unused); 481 uint32_t Hi = (uint32_t)((APFloatOfN.bitcastToAPInt().getZExtValue() & 482 0xFFFFFFFF00000000LL) >> 32); 483 return CurDAG->getTargetConstant(Hi, SDLoc(N), MVT::i32); 484}]>; 485 486// Get the Lo bits of a 64 bit immediate. 487def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{ 488 APFloat APFloatOfN = N->getValueAPF(); 489 bool Unused; 490 APFloatOfN.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 491 &Unused); 492 uint32_t Lo = (uint32_t)(APFloatOfN.bitcastToAPInt().getZExtValue() & 493 0xFFFFFFFF); 494 return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32); 495}]>; 496 497def imm34 : PatLeaf<(imm), [{ 498 return isInt<34>(N->getSExtValue()); 499}]>; 500 501def getImmAs64BitInt : SDNodeXForm<imm, [{ 502 return getI64Imm(N->getSExtValue(), SDLoc(N)); 503}]>; 504 505def SHL32 : SDNodeXForm<imm, [{ 506 // Transformation function: 31 - imm 507 return getI32Imm(31 - N->getZExtValue(), SDLoc(N)); 508}]>; 509 510def SRL32 : SDNodeXForm<imm, [{ 511 // Transformation function: 32 - imm 512 return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N)) 513 : getI32Imm(0, SDLoc(N)); 514}]>; 515 516def LO16 : SDNodeXForm<imm, [{ 517 // Transformation function: get the low 16 bits. 518 return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N)); 519}]>; 520 521def HI16 : SDNodeXForm<imm, [{ 522 // Transformation function: shift the immediate value down into the low bits. 523 return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N)); 524}]>; 525 526def HA16 : SDNodeXForm<imm, [{ 527 // Transformation function: shift the immediate value down into the low bits. 528 int64_t Val = N->getZExtValue(); 529 return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N)); 530}]>; 531def MB : SDNodeXForm<imm, [{ 532 // Transformation function: get the start bit of a mask 533 unsigned mb = 0, me; 534 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 535 return getI32Imm(mb, SDLoc(N)); 536}]>; 537 538def ME : SDNodeXForm<imm, [{ 539 // Transformation function: get the end bit of a mask 540 unsigned mb, me = 0; 541 (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 542 return getI32Imm(me, SDLoc(N)); 543}]>; 544def maskimm32 : PatLeaf<(imm), [{ 545 // maskImm predicate - True if immediate is a run of ones. 546 unsigned mb, me; 547 if (N->getValueType(0) == MVT::i32) 548 return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); 549 else 550 return false; 551}]>; 552 553def imm32SExt16 : Operand<i32>, ImmLeaf<i32, [{ 554 // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit 555 // sign extended field. Used by instructions like 'addi'. 556 return (int32_t)Imm == (short)Imm; 557}]>; 558def imm64SExt16 : Operand<i64>, ImmLeaf<i64, [{ 559 // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit 560 // sign extended field. Used by instructions like 'addi'. 561 return (int64_t)Imm == (short)Imm; 562}]>; 563def immZExt16 : PatLeaf<(imm), [{ 564 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended 565 // field. Used by instructions like 'ori'. 566 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 567}], LO16>; 568def immNonAllOneAnyExt8 : ImmLeaf<i32, [{ 569 return (isInt<8>(Imm) && (Imm != -1)) || (isUInt<8>(Imm) && (Imm != 0xFF)); 570}]>; 571def i32immNonAllOneNonZero : ImmLeaf<i32, [{ return Imm && (Imm != -1); }]>; 572def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; 573 574// imm16Shifted* - These match immediates where the low 16-bits are zero. There 575// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are 576// identical in 32-bit mode, but in 64-bit mode, they return true if the 577// immediate fits into a sign/zero extended 32-bit immediate (with the low bits 578// clear). 579def imm16ShiftedZExt : PatLeaf<(imm), [{ 580 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the 581 // immediate are set. Used by instructions like 'xoris'. 582 return (N->getZExtValue() & ~uint64_t(0xFFFF0000)) == 0; 583}], HI16>; 584 585def imm16ShiftedSExt : PatLeaf<(imm), [{ 586 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the 587 // immediate are set. Used by instructions like 'addis'. Identical to 588 // imm16ShiftedZExt in 32-bit mode. 589 if (N->getZExtValue() & 0xFFFF) return false; 590 if (N->getValueType(0) == MVT::i32) 591 return true; 592 // For 64-bit, make sure it is sext right. 593 return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); 594}], HI16>; 595 596def imm64ZExt32 : Operand<i64>, ImmLeaf<i64, [{ 597 // imm64ZExt32 predicate - True if the i64 immediate fits in a 32-bit 598 // zero extended field. 599 return isUInt<32>(Imm); 600}]>; 601 602// This is a somewhat weaker condition than actually checking for 4-byte 603// alignment. It is simply checking that the displacement can be represented 604// as an immediate that is a multiple of 4 (i.e. the requirements for DS-Form 605// instructions). 606// But some r+i load/store instructions (such as LD, STD, LDU, etc.) that require 607// restricted memrix (4-aligned) constants are alignment sensitive. If these 608// offsets are hidden behind TOC entries than the values of the lower-order 609// bits cannot be checked directly. As a result, we need to also incorporate 610// an alignment check into the relevant patterns. 611 612def DSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 613 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 614}]>; 615def DSFormStore : PatFrag<(ops node:$val, node:$ptr), 616 (store node:$val, node:$ptr), [{ 617 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 618}]>; 619def DSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 620 return isOffsetMultipleOf(N, 4) || cast<LoadSDNode>(N)->getAlign() >= 4; 621}]>; 622def DSFormPreStore : PatFrag< 623 (ops node:$val, node:$base, node:$offset), 624 (pre_store node:$val, node:$base, node:$offset), [{ 625 return isOffsetMultipleOf(N, 4) || cast<StoreSDNode>(N)->getAlign() >= 4; 626}]>; 627 628def NonDSFormLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 629 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 630}]>; 631def NonDSFormStore : PatFrag<(ops node:$val, node:$ptr), 632 (store node:$val, node:$ptr), [{ 633 return cast<StoreSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 634}]>; 635def NonDSFormSextLoadi32 : PatFrag<(ops node:$ptr), (sextloadi32 node:$ptr), [{ 636 return cast<LoadSDNode>(N)->getAlign() < 4 && !isOffsetMultipleOf(N, 4); 637}]>; 638 639// This is a somewhat weaker condition than actually checking for 16-byte 640// alignment. It is simply checking that the displacement can be represented 641// as an immediate that is a multiple of 16 (i.e. the requirements for DQ-Form 642// instructions). 643def quadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 644 return isOffsetMultipleOf(N, 16); 645}]>; 646def quadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 647 (store node:$val, node:$ptr), [{ 648 return isOffsetMultipleOf(N, 16); 649}]>; 650def nonQuadwOffsetLoad : PatFrag<(ops node:$ptr), (load node:$ptr), [{ 651 return !isOffsetMultipleOf(N, 16); 652}]>; 653def nonQuadwOffsetStore : PatFrag<(ops node:$val, node:$ptr), 654 (store node:$val, node:$ptr), [{ 655 return !isOffsetMultipleOf(N, 16); 656}]>; 657 658// PatFrag for binary operation whose operands are both non-constant 659class BinOpWithoutSImm16Operand<SDNode opcode> : 660 PatFrag<(ops node:$left, node:$right), (opcode node:$left, node:$right), [{ 661 int16_t Imm; 662 return !isIntS16Immediate(N->getOperand(0), Imm) 663 && !isIntS16Immediate(N->getOperand(1), Imm); 664}]>; 665 666def add_without_simm16 : BinOpWithoutSImm16Operand<add>; 667def mul_without_simm16 : BinOpWithoutSImm16Operand<mul>; 668 669//===----------------------------------------------------------------------===// 670// PowerPC Flag Definitions. 671 672class isPPC64 { bit PPC64 = 1; } 673class isRecordForm { bit RC = 1; } 674 675class RegConstraint<string C> { 676 string Constraints = C; 677} 678class NoEncode<string E> { 679 string DisableEncoding = E; 680} 681 682 683// Define PowerPC specific addressing mode. 684 685// d-form 686def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>; // "stb" 687// ds-form 688def iaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrImmX4", [], []>; // "std" 689// dq-form 690def iaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrImmX16", [], []>; // "stxv" 691// 8LS:d-form 692def iaddrX34 : ComplexPattern<iPTR, 2, "SelectAddrImmX34", [], []>; // "pstxvp" 693 694// Below forms are all x-form addressing mode, use three different ones so we 695// can make a accurate check for x-form instructions in ISEL. 696// x-form addressing mode whose associated displacement form is D. 697def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>; // "stbx" 698// x-form addressing mode whose associated displacement form is DS. 699def xaddrX4 : ComplexPattern<iPTR, 2, "SelectAddrIdxX4", [], []>; // "stdx" 700// x-form addressing mode whose associated displacement form is DQ. 701def xaddrX16 : ComplexPattern<iPTR, 2, "SelectAddrIdxX16", [], []>; // "stxvx" 702 703def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>; 704 705// The address in a single register. This is used with the SjLj 706// pseudo-instructions. 707def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>; 708 709/// This is just the offset part of iaddr, used for preinc. 710def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>; 711 712// Load and Store Instruction Selection addressing modes. 713let WantsParent = true in { 714 def DForm : ComplexPattern<iPTR, 2, "SelectDForm">; 715 def DSForm : ComplexPattern<iPTR, 2, "SelectDSForm">; 716 def DQForm : ComplexPattern<iPTR, 2, "SelectDQForm">; 717 def XForm : ComplexPattern<iPTR, 2, "SelectXForm">; 718 def ForceXForm : ComplexPattern<iPTR, 2, "SelectForceXForm">; 719 def PCRelForm : ComplexPattern<iPTR, 2, "SelectPCRelForm">; 720 def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">; 721} 722 723//===----------------------------------------------------------------------===// 724// PowerPC Instruction Predicate Definitions. 725def In32BitMode : Predicate<"!Subtarget->isPPC64()">; 726def In64BitMode : Predicate<"Subtarget->isPPC64()">; 727def IsBookE : Predicate<"Subtarget->isBookE()">; 728def IsNotBookE : Predicate<"!Subtarget->isBookE()">; 729def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">; 730def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">; 731def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">; 732def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">; 733def IsE500 : Predicate<"Subtarget->isE500()">; 734def HasSPE : Predicate<"Subtarget->hasSPE()">; 735def HasICBT : Predicate<"Subtarget->hasICBT()">; 736def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">; 737def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">; 738def NoNaNsFPMath 739 : Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 740def NaNsFPMath 741 : Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">; 742def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">; 743def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">; 744def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">; 745def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">; 746def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">; 747def HasFPU : Predicate<"Subtarget->hasFPU()">; 748def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">; 749def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">; 750 751// AIX assembler may not be modern enough to support some extended mne. 752def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">, 753 AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>; 754def IsAIX : Predicate<"Subtarget->isAIXABI()">; 755def NotAIX : Predicate<"!Subtarget->isAIXABI()">; 756def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; 757def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; 758 759//===----------------------------------------------------------------------===// 760// PowerPC Multiclass Definitions. 761multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 762 string asmbase, string asmstr, list<dag> pattern> { 763 let BaseName = asmbase in { 764 def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL, 765 !strconcat(asmbase, !strconcat(" ", asmstr)), 766 NoItinerary, pattern>, RecFormRel; 767 let Defs = [CR1] in 768 def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL, 769 !strconcat(asmbase, !strconcat(". ", asmstr)), 770 NoItinerary, []>, isRecordForm, RecFormRel; 771 } 772} 773 774multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 775 string asmbase, string asmstr, InstrItinClass itin, 776 list<dag> pattern> { 777 let BaseName = asmbase in { 778 def NAME : XForm_6<opcode, xo, OOL, IOL, 779 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 780 pattern>, RecFormRel; 781 let Defs = [CR0] in 782 def _rec : XForm_6<opcode, xo, OOL, IOL, 783 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 784 []>, isRecordForm, RecFormRel; 785 } 786} 787 788multiclass XForm_6rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 789 string asmbase, string asmstr, InstrItinClass itin, 790 list<dag> pattern> { 791 let BaseName = asmbase in { 792 let Defs = [CARRY] in 793 def NAME : XForm_6<opcode, xo, OOL, IOL, 794 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 795 pattern>, RecFormRel; 796 let Defs = [CARRY, CR0] in 797 def _rec : XForm_6<opcode, xo, OOL, IOL, 798 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 799 []>, isRecordForm, RecFormRel; 800 } 801} 802 803multiclass XForm_10rc<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 804 string asmbase, string asmstr, InstrItinClass itin, 805 list<dag> pattern> { 806 let BaseName = asmbase in { 807 let Defs = [CARRY] in 808 def NAME : XForm_10<opcode, xo, OOL, IOL, 809 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 810 pattern>, RecFormRel; 811 let Defs = [CARRY, CR0] in 812 def _rec : XForm_10<opcode, xo, OOL, IOL, 813 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 814 []>, isRecordForm, RecFormRel; 815 } 816} 817 818multiclass XForm_11r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 819 string asmbase, string asmstr, InstrItinClass itin, 820 list<dag> pattern> { 821 let BaseName = asmbase in { 822 def NAME : XForm_11<opcode, xo, OOL, IOL, 823 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 824 pattern>, RecFormRel; 825 let Defs = [CR0] in 826 def _rec : XForm_11<opcode, xo, OOL, IOL, 827 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 828 []>, isRecordForm, RecFormRel; 829 } 830} 831 832multiclass XOForm_1r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 833 string asmbase, string asmstr, InstrItinClass itin, 834 list<dag> pattern> { 835 let BaseName = asmbase in { 836 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 837 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 838 pattern>, RecFormRel; 839 let Defs = [CR0] in 840 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 841 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 842 []>, isRecordForm, RecFormRel; 843 } 844} 845 846// Multiclass for instructions which have a record overflow form as well 847// as a record form but no carry (i.e. mulld, mulldo, subf, subfo, etc.) 848multiclass XOForm_1rx<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 849 string asmbase, string asmstr, InstrItinClass itin, 850 list<dag> pattern> { 851 let BaseName = asmbase in { 852 def NAME : XOForm_1<opcode, xo, 0, OOL, IOL, 853 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 854 pattern>, RecFormRel; 855 let Defs = [CR0] in 856 def _rec : XOForm_1<opcode, xo, 0, OOL, IOL, 857 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 858 []>, isRecordForm, RecFormRel; 859 } 860 let BaseName = !strconcat(asmbase, "O") in { 861 let Defs = [XER] in 862 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 863 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 864 []>, RecFormRel; 865 let Defs = [XER, CR0] in 866 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 867 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 868 []>, isRecordForm, RecFormRel; 869 } 870} 871 872// Multiclass for instructions for which the non record form is not cracked 873// and the record form is cracked (i.e. divw, mullw, etc.) 874multiclass XOForm_1rcr<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 875 string asmbase, string asmstr, InstrItinClass itin, 876 list<dag> pattern> { 877 let BaseName = asmbase in { 878 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 879 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 880 pattern>, RecFormRel; 881 let Defs = [CR0] in 882 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 883 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 884 []>, isRecordForm, RecFormRel, PPC970_DGroup_First, 885 PPC970_DGroup_Cracked; 886 } 887 let BaseName = !strconcat(asmbase, "O") in { 888 let Defs = [XER] in 889 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 890 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 891 []>, RecFormRel; 892 let Defs = [XER, CR0] in 893 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 894 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 895 []>, isRecordForm, RecFormRel; 896 } 897} 898 899multiclass XOForm_1rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 900 string asmbase, string asmstr, InstrItinClass itin, 901 list<dag> pattern> { 902 let BaseName = asmbase in { 903 let Defs = [CARRY] in 904 def NAME : XOForm_1<opcode, xo, oe, OOL, IOL, 905 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 906 pattern>, RecFormRel; 907 let Defs = [CARRY, CR0] in 908 def _rec : XOForm_1<opcode, xo, oe, OOL, IOL, 909 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 910 []>, isRecordForm, RecFormRel; 911 } 912 let BaseName = !strconcat(asmbase, "O") in { 913 let Defs = [CARRY, XER] in 914 def O : XOForm_1<opcode, xo, 1, OOL, IOL, 915 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 916 []>, RecFormRel; 917 let Defs = [CARRY, XER, CR0] in 918 def O_rec : XOForm_1<opcode, xo, 1, OOL, IOL, 919 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 920 []>, isRecordForm, RecFormRel; 921 } 922} 923 924multiclass XOForm_3r<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 925 string asmbase, string asmstr, InstrItinClass itin, 926 list<dag> pattern> { 927 let BaseName = asmbase in { 928 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 929 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 930 pattern>, RecFormRel; 931 let Defs = [CR0] in 932 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 933 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 934 []>, isRecordForm, RecFormRel; 935 } 936 let BaseName = !strconcat(asmbase, "O") in { 937 let Defs = [XER] in 938 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 939 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 940 []>, RecFormRel; 941 let Defs = [XER, CR0] in 942 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 943 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 944 []>, isRecordForm, RecFormRel; 945 } 946} 947 948multiclass XOForm_3rc<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, 949 string asmbase, string asmstr, InstrItinClass itin, 950 list<dag> pattern> { 951 let BaseName = asmbase in { 952 let Defs = [CARRY] in 953 def NAME : XOForm_3<opcode, xo, oe, OOL, IOL, 954 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 955 pattern>, RecFormRel; 956 let Defs = [CARRY, CR0] in 957 def _rec : XOForm_3<opcode, xo, oe, OOL, IOL, 958 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 959 []>, isRecordForm, RecFormRel; 960 } 961 let BaseName = !strconcat(asmbase, "O") in { 962 let Defs = [CARRY, XER] in 963 def O : XOForm_3<opcode, xo, 1, OOL, IOL, 964 !strconcat(asmbase, !strconcat("o ", asmstr)), itin, 965 []>, RecFormRel; 966 let Defs = [CARRY, XER, CR0] in 967 def O_rec : XOForm_3<opcode, xo, 1, OOL, IOL, 968 !strconcat(asmbase, !strconcat("o. ", asmstr)), itin, 969 []>, isRecordForm, RecFormRel; 970 } 971} 972 973multiclass MForm_1r<bits<6> opcode, dag OOL, dag IOL, 974 string asmbase, string asmstr, InstrItinClass itin, 975 list<dag> pattern> { 976 let BaseName = asmbase in { 977 def NAME : MForm_1<opcode, OOL, IOL, 978 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 979 pattern>, RecFormRel; 980 let Defs = [CR0] in 981 def _rec : MForm_1<opcode, OOL, IOL, 982 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 983 []>, isRecordForm, RecFormRel; 984 } 985} 986 987multiclass MForm_2r<bits<6> opcode, dag OOL, dag IOL, 988 string asmbase, string asmstr, InstrItinClass itin, 989 list<dag> pattern> { 990 let BaseName = asmbase in { 991 def NAME : MForm_2<opcode, OOL, IOL, 992 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 993 pattern>, RecFormRel; 994 let Defs = [CR0] in 995 def _rec : MForm_2<opcode, OOL, IOL, 996 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 997 []>, isRecordForm, RecFormRel; 998 } 999} 1000 1001multiclass MDForm_1r<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 1002 string asmbase, string asmstr, InstrItinClass itin, 1003 list<dag> pattern> { 1004 let BaseName = asmbase in { 1005 def NAME : MDForm_1<opcode, xo, OOL, IOL, 1006 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1007 pattern>, RecFormRel; 1008 let Defs = [CR0] in 1009 def _rec : MDForm_1<opcode, xo, OOL, IOL, 1010 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1011 []>, isRecordForm, RecFormRel; 1012 } 1013} 1014 1015multiclass MDSForm_1r<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, 1016 string asmbase, string asmstr, InstrItinClass itin, 1017 list<dag> pattern> { 1018 let BaseName = asmbase in { 1019 def NAME : MDSForm_1<opcode, xo, OOL, IOL, 1020 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1021 pattern>, RecFormRel; 1022 let Defs = [CR0] in 1023 def _rec : MDSForm_1<opcode, xo, OOL, IOL, 1024 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1025 []>, isRecordForm, RecFormRel; 1026 } 1027} 1028 1029multiclass XSForm_1rc<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1030 string asmbase, string asmstr, InstrItinClass itin, 1031 list<dag> pattern> { 1032 let BaseName = asmbase in { 1033 let Defs = [CARRY] in 1034 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1035 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1036 pattern>, RecFormRel; 1037 let Defs = [CARRY, CR0] in 1038 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1039 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1040 []>, isRecordForm, RecFormRel; 1041 } 1042} 1043 1044multiclass XSForm_1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1045 string asmbase, string asmstr, InstrItinClass itin, 1046 list<dag> pattern> { 1047 let BaseName = asmbase in { 1048 def NAME : XSForm_1<opcode, xo, OOL, IOL, 1049 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1050 pattern>, RecFormRel; 1051 let Defs = [CR0] in 1052 def _rec : XSForm_1<opcode, xo, OOL, IOL, 1053 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1054 []>, isRecordForm, RecFormRel; 1055 } 1056} 1057 1058multiclass XForm_26r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1059 string asmbase, string asmstr, InstrItinClass itin, 1060 list<dag> pattern> { 1061 let BaseName = asmbase in { 1062 def NAME : XForm_26<opcode, xo, OOL, IOL, 1063 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1064 pattern>, RecFormRel; 1065 let Defs = [CR1] in 1066 def _rec : XForm_26<opcode, xo, OOL, IOL, 1067 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1068 []>, isRecordForm, RecFormRel; 1069 } 1070} 1071 1072multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1073 string asmbase, string asmstr, InstrItinClass itin, 1074 list<dag> pattern> { 1075 let BaseName = asmbase in { 1076 def NAME : XForm_28<opcode, xo, OOL, IOL, 1077 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1078 pattern>, RecFormRel; 1079 let Defs = [CR1] in 1080 def _rec : XForm_28<opcode, xo, OOL, IOL, 1081 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1082 []>, isRecordForm, RecFormRel; 1083 } 1084} 1085 1086multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1087 string asmbase, string asmstr, list<dag> pattern> { 1088 let BaseName = asmbase in { 1089 def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1090 !strconcat(asmbase, !strconcat(" ", asmstr)), 1091 pattern, NoItinerary>, RecFormRel; 1092 let Defs = [CR1] in 1093 def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL, 1094 !strconcat(asmbase, !strconcat(". ", asmstr)), 1095 [], NoItinerary>, isRecordForm, RecFormRel; 1096 } 1097} 1098 1099multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 1100 string asmbase, string asmstr, list<dag> pattern> { 1101 let BaseName = asmbase in { 1102 def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1103 !strconcat(asmbase, !strconcat(" ", asmstr)), 1104 pattern, NoItinerary>, RecFormRel; 1105 let Defs = [CR1] in 1106 def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL, 1107 !strconcat(asmbase, !strconcat(". ", asmstr)), [], 1108 NoItinerary>, isRecordForm, RecFormRel; 1109 } 1110} 1111 1112multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1113 string asmbase, string asmstr, InstrItinClass itin, 1114 list<dag> pattern> { 1115 let BaseName = asmbase in { 1116 def NAME : AForm_1<opcode, xo, OOL, IOL, 1117 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1118 pattern>, RecFormRel; 1119 let Defs = [CR1] in 1120 def _rec : AForm_1<opcode, xo, OOL, IOL, 1121 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1122 []>, isRecordForm, RecFormRel; 1123 } 1124} 1125 1126multiclass AForm_2r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1127 string asmbase, string asmstr, InstrItinClass itin, 1128 list<dag> pattern> { 1129 let BaseName = asmbase in { 1130 def NAME : AForm_2<opcode, xo, OOL, IOL, 1131 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1132 pattern>, RecFormRel; 1133 let Defs = [CR1] in 1134 def _rec : AForm_2<opcode, xo, OOL, IOL, 1135 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1136 []>, isRecordForm, RecFormRel; 1137 } 1138} 1139 1140multiclass AForm_3r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, 1141 string asmbase, string asmstr, InstrItinClass itin, 1142 list<dag> pattern> { 1143 let BaseName = asmbase in { 1144 def NAME : AForm_3<opcode, xo, OOL, IOL, 1145 !strconcat(asmbase, !strconcat(" ", asmstr)), itin, 1146 pattern>, RecFormRel; 1147 let Defs = [CR1] in 1148 def _rec : AForm_3<opcode, xo, OOL, IOL, 1149 !strconcat(asmbase, !strconcat(". ", asmstr)), itin, 1150 []>, isRecordForm, RecFormRel; 1151 } 1152} 1153 1154multiclass 1155 Z23Form_TE5_FRTB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1156 string asmbase, string asmstr, list<dag> pattern> { 1157 let BaseName = asmbase in { 1158 def NAME 1159 : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1160 !strconcat(asmbase, !strconcat(" ", asmstr)), 1161 pattern>, RecFormRel; 1162 let Defs = [CR0] in 1163 def _rec : Z23Form_TE5_FRTB5_RMC2<opcode, xo, OOL, IOL, 1164 !strconcat(asmbase, !strconcat(". ", asmstr)), 1165 []>, isRecordForm, RecFormRel; 1166 } 1167} 1168 1169multiclass 1170 Z23Form_FRTAB5_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1171 string asmbase, string asmstr, list<dag> pattern> { 1172 let BaseName = asmbase in { 1173 def NAME : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1174 !strconcat(asmbase, !strconcat(" ", asmstr)), 1175 pattern>, RecFormRel; 1176 let Defs = [CR1] in 1177 def _rec : Z23Form_FRTAB5_RMC2<opcode, xo, OOL, IOL, 1178 !strconcat(asmbase, !strconcat(". ", asmstr)), 1179 []>, isRecordForm, RecFormRel; 1180 } 1181} 1182 1183multiclass 1184 Z23Form_FRTB5_R1_RMC2r<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 1185 string asmbase, string asmstr, list<dag> pattern> { 1186 let BaseName = asmbase in { 1187 def NAME : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1188 !strconcat(asmbase, !strconcat(" ", asmstr)), 1189 pattern>, RecFormRel; 1190 let Defs = [CR1] in 1191 def _rec : Z23Form_FRTB5_R1_RMC2<opcode, xo, OOL, IOL, 1192 !strconcat(asmbase, !strconcat(". ", asmstr)), 1193 []>, isRecordForm, RecFormRel; 1194 } 1195} 1196 1197multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 1198 string asmbase, string asmstr, list<dag> pattern> { 1199 let BaseName = asmbase in { 1200 def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1201 !strconcat(asmbase, !strconcat(" ", asmstr)), 1202 pattern, NoItinerary>, RecFormRel; 1203 let Defs = [CR1] in 1204 def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL, 1205 !strconcat(asmbase, !strconcat(". ", asmstr)), 1206 [], NoItinerary>, isRecordForm, RecFormRel; 1207 } 1208} 1209 1210//===----------------------------------------------------------------------===// 1211// END OF MULTICLASS DEFINITIONS 1212//===----------------------------------------------------------------------===// 1213 1214//===----------------------------------------------------------------------===// 1215// PowerPC Instruction Definitions. 1216 1217// Pseudo instructions: 1218 1219let hasCtrlDep = 1 in { 1220let Defs = [R1], Uses = [R1] in { 1221def ADJCALLSTACKDOWN : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1222 "#ADJCALLSTACKDOWN $amt1 $amt2", 1223 [(callseq_start timm:$amt1, timm:$amt2)]>; 1224def ADJCALLSTACKUP : PPCEmitTimePseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), 1225 "#ADJCALLSTACKUP $amt1 $amt2", 1226 [(callseq_end timm:$amt1, timm:$amt2)]>; 1227} 1228} // hasCtrlDep 1229 1230let Defs = [R1], Uses = [R1] in 1231def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC", 1232 [(set i32:$result, 1233 (PPCdynalloc i32:$negsize, iaddr:$fpsi))]>; 1234def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET", 1235 [(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>; 1236// Probed alloca to support stack clash protection. 1237let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in { 1238def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result), 1239 (ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32", 1240 [(set i32:$result, 1241 (PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>; 1242def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs 1243 gprc:$fp, gprc:$actual_negsize), 1244 (ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>; 1245def PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 : PPCEmitTimePseudo<(outs 1246 gprc:$fp, gprc:$actual_negsize), 1247 (ins gprc:$negsize, memri:$fpsi), 1248 "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32", []>, 1249 RegConstraint<"$actual_negsize = $negsize">; 1250def PROBED_STACKALLOC_32 : PPCEmitTimePseudo<(outs gprc:$scratch, gprc:$temp), 1251 (ins i64imm:$stacksize), 1252 "#PROBED_STACKALLOC_32", []>; 1253} 1254 1255// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 1256// instruction selection into a branch sequence. 1257let PPC970_Single = 1 in { 1258 // Note that SELECT_CC_I4 and SELECT_CC_I8 use the no-r0 register classes 1259 // because either operand might become the first operand in an isel, and 1260 // that operand cannot be r0. 1261 def SELECT_CC_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crrc:$cond, 1262 gprc_nor0:$T, gprc_nor0:$F, 1263 i32imm:$BROPC), "#SELECT_CC_I4", 1264 []>; 1265 def SELECT_CC_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crrc:$cond, 1266 g8rc_nox0:$T, g8rc_nox0:$F, 1267 i32imm:$BROPC), "#SELECT_CC_I8", 1268 []>; 1269 def SELECT_CC_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F, 1270 i32imm:$BROPC), "#SELECT_CC_F4", 1271 []>; 1272 def SELECT_CC_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F, 1273 i32imm:$BROPC), "#SELECT_CC_F8", 1274 []>; 1275 def SELECT_CC_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1276 i32imm:$BROPC), "#SELECT_CC_F16", 1277 []>; 1278 def SELECT_CC_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F, 1279 i32imm:$BROPC), "#SELECT_CC_VRRC", 1280 []>; 1281 1282 // SELECT_* pseudo instructions, like SELECT_CC_* but taking condition 1283 // register bit directly. 1284 def SELECT_I4 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins crbitrc:$cond, 1285 gprc_nor0:$T, gprc_nor0:$F), "#SELECT_I4", 1286 [(set i32:$dst, (select i1:$cond, i32:$T, i32:$F))]>; 1287 def SELECT_I8 : PPCCustomInserterPseudo<(outs g8rc:$dst), (ins crbitrc:$cond, 1288 g8rc_nox0:$T, g8rc_nox0:$F), "#SELECT_I8", 1289 [(set i64:$dst, (select i1:$cond, i64:$T, i64:$F))]>; 1290let Predicates = [HasFPU] in { 1291 def SELECT_F4 : PPCCustomInserterPseudo<(outs f4rc:$dst), (ins crbitrc:$cond, 1292 f4rc:$T, f4rc:$F), "#SELECT_F4", 1293 [(set f32:$dst, (select i1:$cond, f32:$T, f32:$F))]>; 1294 def SELECT_F8 : PPCCustomInserterPseudo<(outs f8rc:$dst), (ins crbitrc:$cond, 1295 f8rc:$T, f8rc:$F), "#SELECT_F8", 1296 [(set f64:$dst, (select i1:$cond, f64:$T, f64:$F))]>; 1297 def SELECT_F16 : PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1298 vrrc:$T, vrrc:$F), "#SELECT_F16", 1299 [(set f128:$dst, (select i1:$cond, f128:$T, f128:$F))]>; 1300} 1301 def SELECT_VRRC: PPCCustomInserterPseudo<(outs vrrc:$dst), (ins crbitrc:$cond, 1302 vrrc:$T, vrrc:$F), "#SELECT_VRRC", 1303 [(set v4i32:$dst, 1304 (select i1:$cond, v4i32:$T, v4i32:$F))]>; 1305} 1306 1307// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to 1308// scavenge a register for it. 1309let mayStore = 1 in { 1310def SPILL_CR : PPCEmitTimePseudo<(outs), (ins crrc:$cond, memri:$F), 1311 "#SPILL_CR", []>; 1312def SPILL_CRBIT : PPCEmitTimePseudo<(outs), (ins crbitrc:$cond, memri:$F), 1313 "#SPILL_CRBIT", []>; 1314} 1315 1316// RESTORE_CR - Indicate that we're restoring the CR register (previously 1317// spilled), so we'll need to scavenge a register for it. 1318let mayLoad = 1 in { 1319def RESTORE_CR : PPCEmitTimePseudo<(outs crrc:$cond), (ins memri:$F), 1320 "#RESTORE_CR", []>; 1321def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), 1322 "#RESTORE_CRBIT", []>; 1323} 1324 1325let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { 1326 let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in 1327 def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, 1328 [(PPCretglue)]>, Requires<[In32BitMode]>; 1329 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { 1330 let isPredicable = 1 in 1331 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1332 []>; 1333 1334 let isCodeGenOnly = 1 in { 1335 def BCCCTR : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1336 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB, 1337 []>; 1338 1339 def BCCTR : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI), 1340 "bcctr 12, $BI, 0", IIC_BrB, []>; 1341 def BCCTRn : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI), 1342 "bcctr 4, $BI, 0", IIC_BrB, []>; 1343 } 1344 } 1345} 1346 1347// Set the float rounding mode. 1348let Uses = [RM], Defs = [RM] in { 1349def SETRNDi : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins u2imm:$RND), 1350 "#SETRNDi", [(set f64:$FRT, (int_ppc_setrnd (i32 imm:$RND)))]>; 1351 1352def SETRND : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins gprc:$in), 1353 "#SETRND", [(set f64:$FRT, (int_ppc_setrnd gprc :$in))]>; 1354 1355def SETFLM : PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FLM), 1356 "#SETFLM", [(set f64:$FRT, (int_ppc_setflm f8rc:$FLM))]>; 1357} 1358 1359let isBarrier = 1, hasSideEffects = 1, Defs = [RM] in 1360def FENCE : PPCEmitTimePseudo<(outs), (ins), "#FENCE", []>; 1361 1362let Defs = [LR] in 1363 def MovePCtoLR : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR", []>, 1364 PPC970_Unit_BRU; 1365let Defs = [LR] in 1366 def MoveGOTtoLR : PPCEmitTimePseudo<(outs), (ins), "#MoveGOTtoLR", []>, 1367 PPC970_Unit_BRU; 1368 1369let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1370 hasSideEffects = 0 in { 1371 let isBarrier = 1 in { 1372 let isPredicable = 1 in 1373 def B : IForm<18, 0, 0, (outs), (ins directbrtarget:$LI), 1374 "b $LI", IIC_BrB, 1375 [(br bb:$LI)]>; 1376 def BA : IForm<18, 1, 0, (outs), (ins absdirectbrtarget:$LI), 1377 "ba $LI", IIC_BrB, []>; 1378 } 1379 1380 // BCC represents an arbitrary conditional branch on a predicate. 1381 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use 1382 // a two-value operand where a dag node expects two operands. :( 1383 let isCodeGenOnly = 1 in { 1384 class BCC_class : BForm<16, 0, 0, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1385 "b${cond:cc}${cond:pm} ${cond:reg}, $BD" 1386 /*[(PPCcondbranch crrc:$crS, imm:$opc, bb:$BD)]*/>; 1387 def BCC : BCC_class; 1388 1389 // The same as BCC, except that it's not a terminator. Used for introducing 1390 // control flow dependency without creating new blocks. 1391 let isTerminator = 0 in def CTRL_DEP : BCC_class; 1392 1393 def BCCA : BForm<16, 1, 0, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1394 "b${cond:cc}a${cond:pm} ${cond:reg}, $BD">; 1395 1396 let isReturn = 1, Uses = [LR, RM] in 1397 def BCCLR : XLForm_2_br<19, 16, 0, (outs), (ins (pred $BIBO, $CR):$cond), 1398 "b${cond:cc}lr${cond:pm} ${cond:reg}", IIC_BrB, []>; 1399 } 1400 1401 let isCodeGenOnly = 1 in { 1402 let Pattern = [(brcond i1:$BI, bb:$BD)] in 1403 def BC : BForm_4<16, 12, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1404 "bc 12, $BI, $BD">; 1405 1406 let Pattern = [(brcond (not i1:$BI), bb:$BD)] in 1407 def BCn : BForm_4<16, 4, 0, 0, (outs), (ins crbitrc:$BI, condbrtarget:$BD), 1408 "bc 4, $BI, $BD">; 1409 1410 let isReturn = 1, Uses = [LR, RM] in { 1411 def BCLR : XLForm_2_br2<19, 16, 12, 0, (outs), (ins crbitrc:$BI), 1412 "bclr 12, $BI, 0", IIC_BrB, []>; 1413 def BCLRn : XLForm_2_br2<19, 16, 4, 0, (outs), (ins crbitrc:$BI), 1414 "bclr 4, $BI, 0", IIC_BrB, []>; 1415 } 1416 } 1417 1418 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in { 1419 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 1420 "bdzlr", IIC_BrB, []>; 1421 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 1422 "bdnzlr", IIC_BrB, []>; 1423 def BDZLRp : XLForm_2_ext<19, 16, 27, 0, 0, (outs), (ins), 1424 "bdzlr+", IIC_BrB, []>; 1425 def BDNZLRp: XLForm_2_ext<19, 16, 25, 0, 0, (outs), (ins), 1426 "bdnzlr+", IIC_BrB, []>; 1427 def BDZLRm : XLForm_2_ext<19, 16, 26, 0, 0, (outs), (ins), 1428 "bdzlr-", IIC_BrB, []>; 1429 def BDNZLRm: XLForm_2_ext<19, 16, 24, 0, 0, (outs), (ins), 1430 "bdnzlr-", IIC_BrB, []>; 1431 } 1432 1433 let Defs = [CTR], Uses = [CTR] in { 1434 def BDZ : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD), 1435 "bdz $BD">; 1436 def BDNZ : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD), 1437 "bdnz $BD">; 1438 def BDZA : BForm_1<16, 18, 1, 0, (outs), (ins abscondbrtarget:$BD), 1439 "bdza $BD">; 1440 def BDNZA : BForm_1<16, 16, 1, 0, (outs), (ins abscondbrtarget:$BD), 1441 "bdnza $BD">; 1442 def BDZp : BForm_1<16, 27, 0, 0, (outs), (ins condbrtarget:$BD), 1443 "bdz+ $BD">; 1444 def BDNZp: BForm_1<16, 25, 0, 0, (outs), (ins condbrtarget:$BD), 1445 "bdnz+ $BD">; 1446 def BDZAp : BForm_1<16, 27, 1, 0, (outs), (ins abscondbrtarget:$BD), 1447 "bdza+ $BD">; 1448 def BDNZAp: BForm_1<16, 25, 1, 0, (outs), (ins abscondbrtarget:$BD), 1449 "bdnza+ $BD">; 1450 def BDZm : BForm_1<16, 26, 0, 0, (outs), (ins condbrtarget:$BD), 1451 "bdz- $BD">; 1452 def BDNZm: BForm_1<16, 24, 0, 0, (outs), (ins condbrtarget:$BD), 1453 "bdnz- $BD">; 1454 def BDZAm : BForm_1<16, 26, 1, 0, (outs), (ins abscondbrtarget:$BD), 1455 "bdza- $BD">; 1456 def BDNZAm: BForm_1<16, 24, 1, 0, (outs), (ins abscondbrtarget:$BD), 1457 "bdnza- $BD">; 1458 } 1459} 1460 1461// The unconditional BCL used by the SjLj setjmp code. 1462let isCall = 1, hasCtrlDep = 1, isCodeGenOnly = 1, PPC970_Unit = 7, 1463 hasSideEffects = 0 in { 1464 let Defs = [LR], Uses = [RM] in { 1465 def BCLalways : BForm_2<16, 20, 31, 0, 1, (outs), (ins condbrtarget:$BD), 1466 "bcl 20, 31, $BD">; 1467 } 1468} 1469 1470let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { 1471 // Convenient aliases for call instructions 1472 let Uses = [RM] in { 1473 def BL : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1474 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1475 def BLA : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1476 "bla $LI", IIC_BrB, [(PPCcall (i32 imm:$LI))]>; 1477 1478 let isCodeGenOnly = 1 in { 1479 def BL_TLS : IForm<18, 0, 1, (outs), (ins tlscall32:$LI), 1480 "bl $LI", IIC_BrB, []>; 1481 def BCCL : BForm<16, 0, 1, (outs), (ins (pred $BIBO, $CR):$cond, condbrtarget:$BD), 1482 "b${cond:cc}l${cond:pm} ${cond:reg}, $BD">; 1483 def BCCLA : BForm<16, 1, 1, (outs), (ins (pred $BIBO, $CR):$cond, abscondbrtarget:$BD), 1484 "b${cond:cc}la${cond:pm} ${cond:reg}, $BD">; 1485 1486 def BCL : BForm_4<16, 12, 0, 1, (outs), 1487 (ins crbitrc:$BI, condbrtarget:$BD), 1488 "bcl 12, $BI, $BD">; 1489 def BCLn : BForm_4<16, 4, 0, 1, (outs), 1490 (ins crbitrc:$BI, condbrtarget:$BD), 1491 "bcl 4, $BI, $BD">; 1492 def BL_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 1493 (outs), (ins calltarget:$LI), 1494 "bl $LI\n\tnop", IIC_BrB, []>; 1495 } 1496 } 1497 let Uses = [CTR, RM] in { 1498 let isPredicable = 1 in 1499 def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1500 "bctrl", IIC_BrB, [(PPCbctrl)]>, 1501 Requires<[In32BitMode]>; 1502 1503 let isCodeGenOnly = 1 in { 1504 def BCCCTRL : XLForm_2_br<19, 528, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1505 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB, 1506 []>; 1507 1508 def BCCTRL : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$BI), 1509 "bcctrl 12, $BI, 0", IIC_BrB, []>; 1510 def BCCTRLn : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$BI), 1511 "bcctrl 4, $BI, 0", IIC_BrB, []>; 1512 } 1513 } 1514 let Uses = [LR, RM] in { 1515 def BLRL : XLForm_2_ext<19, 16, 20, 0, 1, (outs), (ins), 1516 "blrl", IIC_BrB, []>; 1517 1518 let isCodeGenOnly = 1 in { 1519 def BCCLRL : XLForm_2_br<19, 16, 1, (outs), (ins (pred $BIBO, $CR):$cond), 1520 "b${cond:cc}lrl${cond:pm} ${cond:reg}", IIC_BrB, 1521 []>; 1522 1523 def BCLRL : XLForm_2_br2<19, 16, 12, 1, (outs), (ins crbitrc:$BI), 1524 "bclrl 12, $BI, 0", IIC_BrB, []>; 1525 def BCLRLn : XLForm_2_br2<19, 16, 4, 1, (outs), (ins crbitrc:$BI), 1526 "bclrl 4, $BI, 0", IIC_BrB, []>; 1527 } 1528 } 1529 let Defs = [CTR], Uses = [CTR, RM] in { 1530 def BDZL : BForm_1<16, 18, 0, 1, (outs), (ins condbrtarget:$BD), 1531 "bdzl $BD">; 1532 def BDNZL : BForm_1<16, 16, 0, 1, (outs), (ins condbrtarget:$BD), 1533 "bdnzl $BD">; 1534 def BDZLA : BForm_1<16, 18, 1, 1, (outs), (ins abscondbrtarget:$BD), 1535 "bdzla $BD">; 1536 def BDNZLA : BForm_1<16, 16, 1, 1, (outs), (ins abscondbrtarget:$BD), 1537 "bdnzla $BD">; 1538 def BDZLp : BForm_1<16, 27, 0, 1, (outs), (ins condbrtarget:$BD), 1539 "bdzl+ $BD">; 1540 def BDNZLp: BForm_1<16, 25, 0, 1, (outs), (ins condbrtarget:$BD), 1541 "bdnzl+ $BD">; 1542 def BDZLAp : BForm_1<16, 27, 1, 1, (outs), (ins abscondbrtarget:$BD), 1543 "bdzla+ $BD">; 1544 def BDNZLAp: BForm_1<16, 25, 1, 1, (outs), (ins abscondbrtarget:$BD), 1545 "bdnzla+ $BD">; 1546 def BDZLm : BForm_1<16, 26, 0, 1, (outs), (ins condbrtarget:$BD), 1547 "bdzl- $BD">; 1548 def BDNZLm: BForm_1<16, 24, 0, 1, (outs), (ins condbrtarget:$BD), 1549 "bdnzl- $BD">; 1550 def BDZLAm : BForm_1<16, 26, 1, 1, (outs), (ins abscondbrtarget:$BD), 1551 "bdzla- $BD">; 1552 def BDNZLAm: BForm_1<16, 24, 1, 1, (outs), (ins abscondbrtarget:$BD), 1553 "bdnzla- $BD">; 1554 } 1555 let Defs = [CTR], Uses = [CTR, LR, RM] in { 1556 def BDZLRL : XLForm_2_ext<19, 16, 18, 0, 1, (outs), (ins), 1557 "bdzlrl", IIC_BrB, []>; 1558 def BDNZLRL : XLForm_2_ext<19, 16, 16, 0, 1, (outs), (ins), 1559 "bdnzlrl", IIC_BrB, []>; 1560 def BDZLRLp : XLForm_2_ext<19, 16, 27, 0, 1, (outs), (ins), 1561 "bdzlrl+", IIC_BrB, []>; 1562 def BDNZLRLp: XLForm_2_ext<19, 16, 25, 0, 1, (outs), (ins), 1563 "bdnzlrl+", IIC_BrB, []>; 1564 def BDZLRLm : XLForm_2_ext<19, 16, 26, 0, 1, (outs), (ins), 1565 "bdzlrl-", IIC_BrB, []>; 1566 def BDNZLRLm: XLForm_2_ext<19, 16, 24, 0, 1, (outs), (ins), 1567 "bdnzlrl-", IIC_BrB, []>; 1568 } 1569} 1570 1571let isCall = 1, PPC970_Unit = 7, Defs = [LR, RM], isCodeGenOnly = 1 in { 1572 // Convenient aliases for call instructions 1573 let Uses = [RM] in { 1574 def BL_RM : IForm<18, 0, 1, (outs), (ins calltarget:$LI), 1575 "bl $LI", IIC_BrB, []>; // See Pat patterns below. 1576 def BLA_RM : IForm<18, 1, 1, (outs), (ins abscalltarget:$LI), 1577 "bla $LI", IIC_BrB, [(PPCcall_rm (i32 imm:$LI))]>; 1578 1579 def BL_NOP_RM : IForm_and_DForm_4_zero<18, 0, 1, 24, 1580 (outs), (ins calltarget:$LI), 1581 "bl $LI\n\tnop", IIC_BrB, []>; 1582 } 1583 let Uses = [CTR, RM] in { 1584 let isPredicable = 1 in 1585 def BCTRL_RM : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 1586 "bctrl", IIC_BrB, [(PPCbctrl_rm)]>, 1587 Requires<[In32BitMode]>; 1588 } 1589} 1590 1591let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1592def TCRETURNdi :PPCEmitTimePseudo< (outs), 1593 (ins calltarget:$dst, i32imm:$offset), 1594 "#TC_RETURNd $dst $offset", 1595 []>; 1596 1597 1598let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1599def TCRETURNai :PPCEmitTimePseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 1600 "#TC_RETURNa $func $offset", 1601 [(PPCtc_return (i32 imm:$func), imm:$offset)]>; 1602 1603let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 1604def TCRETURNri : PPCEmitTimePseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), 1605 "#TC_RETURNr $dst $offset", 1606 []>; 1607 1608let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1609 Defs = [LR, R2], Uses = [CTR, RM], RST = 2 in { 1610 def BCTRL_LWZinto_toc: 1611 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1612 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1613 [(PPCbctrl_load_toc iaddr:$addr)]>, Requires<[In32BitMode]>; 1614 1615} 1616 1617let isCall = 1, PPC970_Unit = 7, isCodeGenOnly = 1, 1618 Defs = [LR, R2, RM], Uses = [CTR, RM], RST = 2 in { 1619 def BCTRL_LWZinto_toc_RM: 1620 XLForm_2_ext_and_DForm_1<19, 528, 20, 0, 1, 32, (outs), 1621 (ins (memri $D, $RA):$addr), "bctrl\n\tlwz 2, $addr", IIC_BrB, 1622 [(PPCbctrl_load_toc_rm iaddr:$addr)]>, Requires<[In32BitMode]>; 1623 1624} 1625 1626let isCodeGenOnly = 1, hasSideEffects = 0 in { 1627 1628let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 1629 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 1630def TAILBCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, 1631 []>, Requires<[In32BitMode]>; 1632 1633let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1634 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1635def TAILB : IForm<18, 0, 0, (outs), (ins calltarget:$LI), 1636 "b $LI", IIC_BrB, 1637 []>; 1638 1639let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 1640 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 1641def TAILBA : IForm<18, 0, 0, (outs), (ins abscalltarget:$LI), 1642 "ba $LI", IIC_BrB, 1643 []>; 1644 1645} 1646 1647// While longjmp is a control-flow barrier (fallthrough isn't allowed), setjmp 1648// is not. 1649let hasSideEffects = 1 in { 1650 let Defs = [CTR] in 1651 def EH_SjLj_SetJmp32 : PPCCustomInserterPseudo<(outs gprc:$dst), (ins memr:$buf), 1652 "#EH_SJLJ_SETJMP32", 1653 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 1654 Requires<[In32BitMode]>; 1655} 1656 1657let hasSideEffects = 1, isBarrier = 1 in { 1658 let isTerminator = 1 in 1659 def EH_SjLj_LongJmp32 : PPCCustomInserterPseudo<(outs), (ins memr:$buf), 1660 "#EH_SJLJ_LONGJMP32", 1661 [(PPCeh_sjlj_longjmp addr:$buf)]>, 1662 Requires<[In32BitMode]>; 1663} 1664 1665// This pseudo is never removed from the function, as it serves as 1666// a terminator. Size is set to 0 to prevent the builtin assembler 1667// from emitting it. 1668let isBranch = 1, isTerminator = 1, Size = 0 in { 1669 def EH_SjLj_Setup : PPCEmitTimePseudo<(outs), (ins directbrtarget:$dst), 1670 "#EH_SjLj_Setup\t$dst", []>; 1671} 1672 1673// System call. 1674let PPC970_Unit = 7 in { 1675 def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV), 1676 "sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>; 1677} 1678 1679// We mark SCV as having no scheduling model since it is only meant to be used 1680// as inline assembly. If we implement a builtin pattern for it we will need to 1681// add it to the P9 and P10 scheduling models. 1682let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in { 1683 def SCV : SCForm<17, 0, 1, (outs), (ins i32imm:$LEV), 1684 "scv $LEV", IIC_BrB, []>; 1685} 1686 1687// Branch history rolling buffer. 1688def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, 1689 [(PPCclrbhrb)]>, 1690 PPC970_DGroup_Single; 1691// The $dmy argument used for MFBHRBE is not needed; however, including 1692// it avoids automatic generation of PPCFastISel::fastEmit_i(), which 1693// interferes with necessary special handling (see PPCFastISel.cpp). 1694def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), 1695 (ins u10imm:$imm, u10imm:$dmy), 1696 "mfbhrbe $RT, $imm", IIC_BrB, 1697 [(set i32:$RT, 1698 (PPCmfbhrbe imm:$imm, imm:$dmy))]>, 1699 PPC970_DGroup_First; 1700 1701def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", 1702 IIC_BrB, [(PPCrfebb (i32 imm:$S))]>, 1703 PPC970_DGroup_Single; 1704 1705def : InstAlias<"rfebb", (RFEBB 1)>; 1706 1707// DCB* instructions. 1708def DCBA : DCB_Form<758, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcba $addr", 1709 IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$addr)]>, 1710 PPC970_DGroup_Single; 1711def DCBI : DCB_Form<470, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbi $addr", 1712 IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$addr)]>, 1713 PPC970_DGroup_Single; 1714def DCBST : DCB_Form<54, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbst $addr", 1715 IIC_LdStDCBF, [(int_ppc_dcbst xoaddr:$addr)]>, 1716 PPC970_DGroup_Single; 1717def DCBZ : DCB_Form<1014, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbz $addr", 1718 IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$addr)]>, 1719 PPC970_DGroup_Single; 1720def DCBZL : DCB_Form<1014, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzl $addr", 1721 IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$addr)]>, 1722 PPC970_DGroup_Single; 1723 1724def DCBF : DCB_Form_hint<86, (outs), (ins u3imm:$TH, (memrr $RA, $RB):$addr), 1725 "dcbf $addr, $TH", IIC_LdStDCBF, []>, 1726 PPC970_DGroup_Single; 1727 1728let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { 1729def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1730 "dcbt $addr, $TH", IIC_LdStDCBF, []>, 1731 PPC970_DGroup_Single; 1732def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, (memrr $RA, $RB):$addr), 1733 "dcbtst $addr, $TH", IIC_LdStDCBF, []>, 1734 PPC970_DGroup_Single; 1735} // hasSideEffects = 0 1736 1737def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1738 "icblc $CT, $addr", IIC_LdStStore>, Requires<[HasICBT]>; 1739def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1740 "icblq. $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1741def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1742 "icbt $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1743def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, (memrr $RA, $RB):$addr), 1744 "icbtls $CT, $addr", IIC_LdStLoad>, Requires<[HasICBT]>; 1745 1746def : Pat<(int_ppc_dcbt xoaddr:$dst), 1747 (DCBT 0, xoaddr:$dst)>; 1748def : Pat<(int_ppc_dcbtst xoaddr:$dst), 1749 (DCBTST 0, xoaddr:$dst)>; 1750def : Pat<(int_ppc_dcbf xoaddr:$dst), 1751 (DCBF 0, xoaddr:$dst)>; 1752def : Pat<(int_ppc_icbt xoaddr:$dst), 1753 (ICBT 0, xoaddr:$dst)>; 1754 1755def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 1)), 1756 (DCBT 0, xoaddr:$dst)>; // data prefetch for loads 1757def : Pat<(prefetch xoaddr:$dst, (i32 1), timm, (i32 1)), 1758 (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores 1759def : Pat<(prefetch xoaddr:$dst, (i32 0), timm, (i32 0)), 1760 (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read) 1761 1762def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH), 1763 (DCBT i32:$TH, xoaddr:$dst)>; 1764def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH), 1765 (DCBTST i32:$TH, xoaddr:$dst)>; 1766 1767// Atomic operations 1768// FIXME: some of these might be used with constant operands. This will result 1769// in constant materialization instructions that may be redundant. We currently 1770// clean this up in PPCMIPeephole with calls to 1771// PPCInstrInfo::convertToImmediateForm() but we should probably not emit them 1772// in the first place. 1773let Defs = [CR0] in { 1774 def ATOMIC_LOAD_ADD_I8 : PPCCustomInserterPseudo< 1775 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I8", 1776 [(set i32:$dst, (atomic_load_add_i8 ForceXForm:$ptr, i32:$incr))]>; 1777 def ATOMIC_LOAD_SUB_I8 : PPCCustomInserterPseudo< 1778 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I8", 1779 [(set i32:$dst, (atomic_load_sub_i8 ForceXForm:$ptr, i32:$incr))]>; 1780 def ATOMIC_LOAD_AND_I8 : PPCCustomInserterPseudo< 1781 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I8", 1782 [(set i32:$dst, (atomic_load_and_i8 ForceXForm:$ptr, i32:$incr))]>; 1783 def ATOMIC_LOAD_OR_I8 : PPCCustomInserterPseudo< 1784 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I8", 1785 [(set i32:$dst, (atomic_load_or_i8 ForceXForm:$ptr, i32:$incr))]>; 1786 def ATOMIC_LOAD_XOR_I8 : PPCCustomInserterPseudo< 1787 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "ATOMIC_LOAD_XOR_I8", 1788 [(set i32:$dst, (atomic_load_xor_i8 ForceXForm:$ptr, i32:$incr))]>; 1789 def ATOMIC_LOAD_NAND_I8 : PPCCustomInserterPseudo< 1790 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I8", 1791 [(set i32:$dst, (atomic_load_nand_i8 ForceXForm:$ptr, i32:$incr))]>; 1792 def ATOMIC_LOAD_MIN_I8 : PPCCustomInserterPseudo< 1793 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I8", 1794 [(set i32:$dst, (atomic_load_min_i8 ForceXForm:$ptr, i32:$incr))]>; 1795 def ATOMIC_LOAD_MAX_I8 : PPCCustomInserterPseudo< 1796 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I8", 1797 [(set i32:$dst, (atomic_load_max_i8 ForceXForm:$ptr, i32:$incr))]>; 1798 def ATOMIC_LOAD_UMIN_I8 : PPCCustomInserterPseudo< 1799 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I8", 1800 [(set i32:$dst, (atomic_load_umin_i8 ForceXForm:$ptr, i32:$incr))]>; 1801 def ATOMIC_LOAD_UMAX_I8 : PPCCustomInserterPseudo< 1802 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I8", 1803 [(set i32:$dst, (atomic_load_umax_i8 ForceXForm:$ptr, i32:$incr))]>; 1804 def ATOMIC_LOAD_ADD_I16 : PPCCustomInserterPseudo< 1805 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I16", 1806 [(set i32:$dst, (atomic_load_add_i16 ForceXForm:$ptr, i32:$incr))]>; 1807 def ATOMIC_LOAD_SUB_I16 : PPCCustomInserterPseudo< 1808 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I16", 1809 [(set i32:$dst, (atomic_load_sub_i16 ForceXForm:$ptr, i32:$incr))]>; 1810 def ATOMIC_LOAD_AND_I16 : PPCCustomInserterPseudo< 1811 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I16", 1812 [(set i32:$dst, (atomic_load_and_i16 ForceXForm:$ptr, i32:$incr))]>; 1813 def ATOMIC_LOAD_OR_I16 : PPCCustomInserterPseudo< 1814 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I16", 1815 [(set i32:$dst, (atomic_load_or_i16 ForceXForm:$ptr, i32:$incr))]>; 1816 def ATOMIC_LOAD_XOR_I16 : PPCCustomInserterPseudo< 1817 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I16", 1818 [(set i32:$dst, (atomic_load_xor_i16 ForceXForm:$ptr, i32:$incr))]>; 1819 def ATOMIC_LOAD_NAND_I16 : PPCCustomInserterPseudo< 1820 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I16", 1821 [(set i32:$dst, (atomic_load_nand_i16 ForceXForm:$ptr, i32:$incr))]>; 1822 def ATOMIC_LOAD_MIN_I16 : PPCCustomInserterPseudo< 1823 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I16", 1824 [(set i32:$dst, (atomic_load_min_i16 ForceXForm:$ptr, i32:$incr))]>; 1825 def ATOMIC_LOAD_MAX_I16 : PPCCustomInserterPseudo< 1826 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I16", 1827 [(set i32:$dst, (atomic_load_max_i16 ForceXForm:$ptr, i32:$incr))]>; 1828 def ATOMIC_LOAD_UMIN_I16 : PPCCustomInserterPseudo< 1829 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I16", 1830 [(set i32:$dst, (atomic_load_umin_i16 ForceXForm:$ptr, i32:$incr))]>; 1831 def ATOMIC_LOAD_UMAX_I16 : PPCCustomInserterPseudo< 1832 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I16", 1833 [(set i32:$dst, (atomic_load_umax_i16 ForceXForm:$ptr, i32:$incr))]>; 1834 def ATOMIC_LOAD_ADD_I32 : PPCCustomInserterPseudo< 1835 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_ADD_I32", 1836 [(set i32:$dst, (atomic_load_add_i32 ForceXForm:$ptr, i32:$incr))]>; 1837 def ATOMIC_LOAD_SUB_I32 : PPCCustomInserterPseudo< 1838 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_SUB_I32", 1839 [(set i32:$dst, (atomic_load_sub_i32 ForceXForm:$ptr, i32:$incr))]>; 1840 def ATOMIC_LOAD_AND_I32 : PPCCustomInserterPseudo< 1841 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_AND_I32", 1842 [(set i32:$dst, (atomic_load_and_i32 ForceXForm:$ptr, i32:$incr))]>; 1843 def ATOMIC_LOAD_OR_I32 : PPCCustomInserterPseudo< 1844 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_OR_I32", 1845 [(set i32:$dst, (atomic_load_or_i32 ForceXForm:$ptr, i32:$incr))]>; 1846 def ATOMIC_LOAD_XOR_I32 : PPCCustomInserterPseudo< 1847 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_XOR_I32", 1848 [(set i32:$dst, (atomic_load_xor_i32 ForceXForm:$ptr, i32:$incr))]>; 1849 def ATOMIC_LOAD_NAND_I32 : PPCCustomInserterPseudo< 1850 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_NAND_I32", 1851 [(set i32:$dst, (atomic_load_nand_i32 ForceXForm:$ptr, i32:$incr))]>; 1852 def ATOMIC_LOAD_MIN_I32 : PPCCustomInserterPseudo< 1853 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MIN_I32", 1854 [(set i32:$dst, (atomic_load_min_i32 ForceXForm:$ptr, i32:$incr))]>; 1855 def ATOMIC_LOAD_MAX_I32 : PPCCustomInserterPseudo< 1856 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_MAX_I32", 1857 [(set i32:$dst, (atomic_load_max_i32 ForceXForm:$ptr, i32:$incr))]>; 1858 def ATOMIC_LOAD_UMIN_I32 : PPCCustomInserterPseudo< 1859 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMIN_I32", 1860 [(set i32:$dst, (atomic_load_umin_i32 ForceXForm:$ptr, i32:$incr))]>; 1861 def ATOMIC_LOAD_UMAX_I32 : PPCCustomInserterPseudo< 1862 (outs gprc:$dst), (ins memrr:$ptr, gprc:$incr), "#ATOMIC_LOAD_UMAX_I32", 1863 [(set i32:$dst, (atomic_load_umax_i32 ForceXForm:$ptr, i32:$incr))]>; 1864 1865 def ATOMIC_CMP_SWAP_I8 : PPCCustomInserterPseudo< 1866 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I8", 1867 [(set i32:$dst, (atomic_cmp_swap_i8 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1868 def ATOMIC_CMP_SWAP_I16 : PPCCustomInserterPseudo< 1869 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I16 $dst $ptr $old $new", 1870 [(set i32:$dst, (atomic_cmp_swap_i16 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1871 def ATOMIC_CMP_SWAP_I32 : PPCCustomInserterPseudo< 1872 (outs gprc:$dst), (ins memrr:$ptr, gprc:$old, gprc:$new), "#ATOMIC_CMP_SWAP_I32 $dst $ptr $old $new", 1873 [(set i32:$dst, (atomic_cmp_swap_i32 ForceXForm:$ptr, i32:$old, i32:$new))]>; 1874 1875 def ATOMIC_SWAP_I8 : PPCCustomInserterPseudo< 1876 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_i8", 1877 [(set i32:$dst, (atomic_swap_i8 ForceXForm:$ptr, i32:$new))]>; 1878 def ATOMIC_SWAP_I16 : PPCCustomInserterPseudo< 1879 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I16", 1880 [(set i32:$dst, (atomic_swap_i16 ForceXForm:$ptr, i32:$new))]>; 1881 def ATOMIC_SWAP_I32 : PPCCustomInserterPseudo< 1882 (outs gprc:$dst), (ins memrr:$ptr, gprc:$new), "#ATOMIC_SWAP_I32", 1883 [(set i32:$dst, (atomic_swap_i32 ForceXForm:$ptr, i32:$new))]>; 1884} 1885 1886def : Pat<(PPCatomicCmpSwap_8 ForceXForm:$ptr, i32:$old, i32:$new), 1887 (ATOMIC_CMP_SWAP_I8 ForceXForm:$ptr, i32:$old, i32:$new)>; 1888def : Pat<(PPCatomicCmpSwap_16 ForceXForm:$ptr, i32:$old, i32:$new), 1889 (ATOMIC_CMP_SWAP_I16 ForceXForm:$ptr, i32:$old, i32:$new)>; 1890 1891// Instructions to support atomic operations 1892let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 1893def LBARX : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1894 "lbarx $RST, $addr", IIC_LdStLWARX, []>, 1895 Requires<[HasPartwordAtomics]>; 1896 1897def LHARX : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1898 "lharx $RST, $addr", IIC_LdStLWARX, []>, 1899 Requires<[HasPartwordAtomics]>; 1900 1901def LWARX : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1902 "lwarx $RST, $addr", IIC_LdStLWARX, []>; 1903 1904// Instructions to support lock versions of atomics 1905// (EH=1 - see Power ISA 2.07 Book II 4.4.2) 1906def LBARXL : XForm_1_memOp<31, 52, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1907 "lbarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1908 Requires<[HasPartwordAtomics]>; 1909 1910def LHARXL : XForm_1_memOp<31, 116, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1911 "lharx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm, 1912 Requires<[HasPartwordAtomics]>; 1913 1914def LWARXL : XForm_1_memOp<31, 20, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 1915 "lwarx $RST, $addr, 1", IIC_LdStLWARX, []>, isRecordForm; 1916 1917// The atomic instructions use the destination register as well as the next one 1918// or two registers in order (modulo 31). 1919let hasExtraSrcRegAllocReq = 1 in 1920def LWAT : X_RD5_RS5_IM5<31, 582, (outs gprc:$RST), (ins gprc:$RA, u5imm:$RB), 1921 "lwat $RST, $RA, $RB", IIC_LdStLoad>, 1922 Requires<[IsISA3_0]>; 1923} 1924 1925let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in { 1926def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1927 "stbcx. $RST, $addr", IIC_LdStSTWCX, []>, 1928 isRecordForm, Requires<[HasPartwordAtomics]>; 1929 1930def STHCX : XForm_1_memOp<31, 726, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1931 "sthcx. $RST, $addr", IIC_LdStSTWCX, []>, 1932 isRecordForm, Requires<[HasPartwordAtomics]>; 1933 1934def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 1935 "stwcx. $RST, $addr", IIC_LdStSTWCX, []>, isRecordForm; 1936} 1937 1938let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 1939def STWAT : X_RD5_RS5_IM5<31, 710, (outs), (ins gprc:$RST, gprc:$RA, u5imm:$RB), 1940 "stwat $RST, $RA, $RB", IIC_LdStStore>, 1941 Requires<[IsISA3_0]>; 1942 1943let isTrap = 1, hasCtrlDep = 1 in 1944def TRAP : XForm_24<31, 4, (outs), (ins), "trap", IIC_LdStLoad, [(trap)]>; 1945 1946def TWI : DForm_base<3, (outs), (ins u5imm:$RST, gprc:$RA, s16imm:$D, variable_ops), 1947 "twi $RST, $RA, $D", IIC_IntTrapW, []>; 1948def TW : XForm_1<31, 4, (outs), (ins u5imm:$RST, gprc:$RA, gprc:$RB, variable_ops), 1949 "tw $RST, $RA, $RB", IIC_IntTrapW, []>; 1950def TDI : DForm_base<2, (outs), (ins u5imm:$RST, g8rc:$RA, s16imm:$D, variable_ops), 1951 "tdi $RST, $RA, $D", IIC_IntTrapD, []>; 1952def TD : XForm_1<31, 68, (outs), (ins u5imm:$RST, g8rc:$RA, g8rc:$RB, variable_ops), 1953 "td $RST, $RA, $RB", IIC_IntTrapD, []>; 1954 1955def POPCNTB : XForm_11<31, 122, (outs gprc:$RA), (ins gprc:$RST), 1956 "popcntb $RA, $RST", IIC_IntGeneral, 1957 [(set i32:$RA, (int_ppc_popcntb i32:$RST))]>; 1958 1959def CDTBCD : XForm_11<31, 282, (outs gprc:$RA), (ins gprc:$RST), 1960 "cdtbcd $RA, $RST", IIC_IntGeneral, 1961 [(set i32:$RA, (int_ppc_cdtbcd i32:$RST))]>; 1962def CBCDTD : XForm_11<31, 314, (outs gprc:$RA), (ins gprc:$RST), 1963 "cbcdtd $RA, $RST", IIC_IntGeneral, 1964 [(set i32:$RA, (int_ppc_cbcdtd i32:$RST))]>; 1965def ADDG6S : XOForm_1<31, 74, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 1966 "addg6s $RT, $RA, $RB", IIC_IntGeneral, 1967 [(set i32:$RT, (int_ppc_addg6s i32:$RA, i32:$RB))]>; 1968 1969//===----------------------------------------------------------------------===// 1970// PPC32 Load Instructions. 1971// 1972 1973// Unindexed (r+i) Loads. 1974let PPC970_Unit = 2 in { 1975def LBZ : DForm_1<34, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1976 "lbz $RST, $addr", IIC_LdStLoad, 1977 [(set i32:$RST, (zextloadi8 DForm:$addr))]>, ZExt32To64, 1978 SExt32To64; 1979def LHA : DForm_1<42, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1980 "lha $RST, $addr", IIC_LdStLHA, 1981 [(set i32:$RST, (sextloadi16 DForm:$addr))]>, 1982 PPC970_DGroup_Cracked, SExt32To64; 1983def LHZ : DForm_1<40, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1984 "lhz $RST, $addr", IIC_LdStLoad, 1985 [(set i32:$RST, (zextloadi16 DForm:$addr))]>, ZExt32To64, 1986 SExt32To64; 1987def LWZ : DForm_1<32, (outs gprc:$RST), (ins (memri $D, $RA):$addr), 1988 "lwz $RST, $addr", IIC_LdStLoad, 1989 [(set i32:$RST, (load DForm:$addr))]>, ZExt32To64; 1990 1991let Predicates = [HasFPU] in { 1992def LFS : DForm_1<48, (outs f4rc:$RST), (ins (memri $D, $RA):$addr), 1993 "lfs $RST, $addr", IIC_LdStLFD, 1994 [(set f32:$RST, (load DForm:$addr))]>; 1995def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), 1996 "lfd $RST, $addr", IIC_LdStLFD, 1997 [(set f64:$RST, (load DForm:$addr))]>; 1998} 1999 2000 2001// Unindexed (r+i) Loads with Update (preinc). 2002let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { 2003def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2004 "lbzu $RST, $addr", IIC_LdStLoadUpd, 2005 []>, RegConstraint<"$RA = $ea_result">; 2006 2007def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2008 "lhau $RST, $addr", IIC_LdStLHAU, 2009 []>, RegConstraint<"$addr.reg = $ea_result">, 2010 NoEncode<"$ea_result">; 2011 2012def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2013 "lhzu $RST, $addr", IIC_LdStLoadUpd, 2014 []>, RegConstraint<"$addr.reg = $ea_result">, 2015 NoEncode<"$ea_result">; 2016 2017def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2018 "lwzu $RST, $addr", IIC_LdStLoadUpd, 2019 []>, RegConstraint<"$addr.reg = $ea_result">, 2020 NoEncode<"$ea_result">; 2021 2022let Predicates = [HasFPU] in { 2023def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2024 "lfsu $RST, $addr", IIC_LdStLFDU, 2025 []>, RegConstraint<"$addr.reg = $ea_result">, 2026 NoEncode<"$ea_result">; 2027 2028def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), 2029 "lfdu $RST, $addr", IIC_LdStLFDU, 2030 []>, RegConstraint<"$addr.reg = $ea_result">, 2031 NoEncode<"$ea_result">; 2032} 2033 2034 2035// Indexed (r+r) Loads with Update (preinc). 2036def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2037 (ins (memrr $RA, $RB):$addr), 2038 "lbzux $RST, $addr", IIC_LdStLoadUpdX, 2039 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2040 NoEncode<"$ea_result">; 2041 2042def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2043 (ins (memrr $RA, $RB):$addr), 2044 "lhaux $RST, $addr", IIC_LdStLHAUX, 2045 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2046 NoEncode<"$ea_result">; 2047 2048def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2049 (ins (memrr $RA, $RB):$addr), 2050 "lhzux $RST, $addr", IIC_LdStLoadUpdX, 2051 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2052 NoEncode<"$ea_result">; 2053 2054def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), 2055 (ins (memrr $RA, $RB):$addr), 2056 "lwzux $RST, $addr", IIC_LdStLoadUpdX, 2057 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2058 NoEncode<"$ea_result">; 2059 2060let Predicates = [HasFPU] in { 2061def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), 2062 (ins (memrr $RA, $RB):$addr), 2063 "lfsux $RST, $addr", IIC_LdStLFDUX, 2064 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2065 NoEncode<"$ea_result">; 2066 2067def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), 2068 (ins (memrr $RA, $RB):$addr), 2069 "lfdux $RST, $addr", IIC_LdStLFDUX, 2070 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 2071 NoEncode<"$ea_result">; 2072} 2073} 2074} 2075 2076// Indexed (r+r) Loads. 2077// 2078let PPC970_Unit = 2, mayLoad = 1, mayStore = 0 in { 2079def LBZX : XForm_1_memOp<31, 87, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2080 "lbzx $RST, $addr", IIC_LdStLoad, 2081 [(set i32:$RST, (zextloadi8 XForm:$addr))]>, ZExt32To64, 2082 SExt32To64; 2083def LHAX : XForm_1_memOp<31, 343, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2084 "lhax $RST, $addr", IIC_LdStLHA, 2085 [(set i32:$RST, (sextloadi16 XForm:$addr))]>, 2086 PPC970_DGroup_Cracked, SExt32To64; 2087def LHZX : XForm_1_memOp<31, 279, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2088 "lhzx $RST, $addr", IIC_LdStLoad, 2089 [(set i32:$RST, (zextloadi16 XForm:$addr))]>, ZExt32To64, 2090 SExt32To64; 2091def LWZX : XForm_1_memOp<31, 23, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2092 "lwzx $RST, $addr", IIC_LdStLoad, 2093 [(set i32:$RST, (load XForm:$addr))]>, ZExt32To64; 2094def LHBRX : XForm_1_memOp<31, 790, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2095 "lhbrx $RST, $addr", IIC_LdStLoad, 2096 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i16))]>, ZExt32To64; 2097def LWBRX : XForm_1_memOp<31, 534, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 2098 "lwbrx $RST, $addr", IIC_LdStLoad, 2099 [(set i32:$RST, (PPClbrx ForceXForm:$addr, i32))]>, ZExt32To64; 2100 2101let Predicates = [HasFPU] in { 2102def LFSX : XForm_25_memOp<31, 535, (outs f4rc:$RST), (ins (memrr $RA, $RB):$addr), 2103 "lfsx $RST, $addr", IIC_LdStLFD, 2104 [(set f32:$RST, (load XForm:$addr))]>; 2105def LFDX : XForm_25_memOp<31, 599, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2106 "lfdx $RST, $addr", IIC_LdStLFD, 2107 [(set f64:$RST, (load XForm:$addr))]>; 2108 2109def LFIWAX : XForm_25_memOp<31, 855, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2110 "lfiwax $RST, $addr", IIC_LdStLFD, 2111 [(set f64:$RST, (PPClfiwax ForceXForm:$addr))]>; 2112def LFIWZX : XForm_25_memOp<31, 887, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 2113 "lfiwzx $RST, $addr", IIC_LdStLFD, 2114 [(set f64:$RST, (PPClfiwzx ForceXForm:$addr))]>; 2115} 2116} 2117 2118// Load Multiple 2119let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in 2120def LMW : DForm_1<46, (outs gprc:$RST), (ins (memri $D, $RA):$src), 2121 "lmw $RST, $src", IIC_LdStLMW, []>; 2122 2123//===----------------------------------------------------------------------===// 2124// PPC32 Store Instructions. 2125// 2126 2127// Unindexed (r+i) Stores. 2128let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2129def STB : DForm_1<38, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2130 "stb $RST, $dst", IIC_LdStStore, 2131 [(truncstorei8 i32:$RST, DForm:$dst)]>; 2132def STH : DForm_1<44, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2133 "sth $RST, $dst", IIC_LdStStore, 2134 [(truncstorei16 i32:$RST, DForm:$dst)]>; 2135def STW : DForm_1<36, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2136 "stw $RST, $dst", IIC_LdStStore, 2137 [(store i32:$RST, DForm:$dst)]>; 2138let Predicates = [HasFPU] in { 2139def STFS : DForm_1<52, (outs), (ins f4rc:$RST, (memri $D, $RA):$dst), 2140 "stfs $RST, $dst", IIC_LdStSTFD, 2141 [(store f32:$RST, DForm:$dst)]>; 2142def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), 2143 "stfd $RST, $dst", IIC_LdStSTFD, 2144 [(store f64:$RST, DForm:$dst)]>; 2145} 2146} 2147 2148// Unindexed (r+i) Stores with Update (preinc). 2149let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2150def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2151 "stbu $RST, $dst", IIC_LdStSTU, []>, 2152 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2153def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2154 "sthu $RST, $dst", IIC_LdStSTU, []>, 2155 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2156def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), 2157 "stwu $RST, $dst", IIC_LdStSTU, []>, 2158 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2159let Predicates = [HasFPU] in { 2160def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), 2161 "stfsu $RST, $dst", IIC_LdStSTFDU, []>, 2162 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2163def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), 2164 "stfdu $RST, $dst", IIC_LdStSTFDU, []>, 2165 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 2166} 2167} 2168 2169// Patterns to match the pre-inc stores. We can't put the patterns on 2170// the instruction definitions directly as ISel wants the address base 2171// and offset to be separate operands, not a single complex operand. 2172def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2173 (STBU $rS, iaddroff:$ptroff, $ptrreg)>; 2174def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2175 (STHU $rS, iaddroff:$ptroff, $ptrreg)>; 2176def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2177 (STWU $rS, iaddroff:$ptroff, $ptrreg)>; 2178def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2179 (STFSU $rS, iaddroff:$ptroff, $ptrreg)>; 2180def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 2181 (STFDU $rS, iaddroff:$ptroff, $ptrreg)>; 2182 2183// Indexed (r+r) Stores. 2184let PPC970_Unit = 2 in { 2185def STBX : XForm_8_memOp<31, 215, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2186 "stbx $RST, $addr", IIC_LdStStore, 2187 [(truncstorei8 i32:$RST, XForm:$addr)]>, 2188 PPC970_DGroup_Cracked; 2189def STHX : XForm_8_memOp<31, 407, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2190 "sthx $RST, $addr", IIC_LdStStore, 2191 [(truncstorei16 i32:$RST, XForm:$addr)]>, 2192 PPC970_DGroup_Cracked; 2193def STWX : XForm_8_memOp<31, 151, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2194 "stwx $RST, $addr", IIC_LdStStore, 2195 [(store i32:$RST, XForm:$addr)]>, 2196 PPC970_DGroup_Cracked; 2197 2198def STHBRX: XForm_8_memOp<31, 918, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2199 "sthbrx $RST, $addr", IIC_LdStStore, 2200 [(PPCstbrx i32:$RST, ForceXForm:$addr, i16)]>, 2201 PPC970_DGroup_Cracked; 2202def STWBRX: XForm_8_memOp<31, 662, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 2203 "stwbrx $RST, $addr", IIC_LdStStore, 2204 [(PPCstbrx i32:$RST, ForceXForm:$addr, i32)]>, 2205 PPC970_DGroup_Cracked; 2206 2207let Predicates = [HasFPU] in { 2208def STFIWX: XForm_28_memOp<31, 983, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2209 "stfiwx $RST, $addr", IIC_LdStSTFD, 2210 [(PPCstfiwx f64:$RST, ForceXForm:$addr)]>; 2211 2212def STFSX : XForm_28_memOp<31, 663, (outs), (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2213 "stfsx $RST, $addr", IIC_LdStSTFD, 2214 [(store f32:$RST, XForm:$addr)]>; 2215def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2216 "stfdx $RST, $addr", IIC_LdStSTFD, 2217 [(store f64:$RST, XForm:$addr)]>; 2218} 2219} 2220 2221// Indexed (r+r) Stores with Update (preinc). 2222let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { 2223def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), 2224 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2225 "stbux $RST, $addr", IIC_LdStSTUX, []>, 2226 RegConstraint<"$addr.ptrreg = $ea_res">, 2227 NoEncode<"$ea_res">, 2228 PPC970_DGroup_Cracked; 2229def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), 2230 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2231 "sthux $RST, $addr", IIC_LdStSTUX, []>, 2232 RegConstraint<"$addr.ptrreg = $ea_res">, 2233 NoEncode<"$ea_res">, 2234 PPC970_DGroup_Cracked; 2235def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), 2236 (ins gprc:$RST, (memrr $RA, $RB):$addr), 2237 "stwux $RST, $addr", IIC_LdStSTUX, []>, 2238 RegConstraint<"$addr.ptrreg = $ea_res">, 2239 NoEncode<"$ea_res">, 2240 PPC970_DGroup_Cracked; 2241let Predicates = [HasFPU] in { 2242def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), 2243 (ins f4rc:$RST, (memrr $RA, $RB):$addr), 2244 "stfsux $RST, $addr", IIC_LdStSTFDU, []>, 2245 RegConstraint<"$addr.ptrreg = $ea_res">, 2246 NoEncode<"$ea_res">, 2247 PPC970_DGroup_Cracked; 2248def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), 2249 (ins f8rc:$RST, (memrr $RA, $RB):$addr), 2250 "stfdux $RST, $addr", IIC_LdStSTFDU, []>, 2251 RegConstraint<"$addr.ptrreg = $ea_res">, 2252 NoEncode<"$ea_res">, 2253 PPC970_DGroup_Cracked; 2254} 2255} 2256 2257// Patterns to match the pre-inc stores. We can't put the patterns on 2258// the instruction definitions directly as ISel wants the address base 2259// and offset to be separate operands, not a single complex operand. 2260def : Pat<(pre_truncsti8 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2261 (STBUX $rS, $ptrreg, $ptroff)>; 2262def : Pat<(pre_truncsti16 i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2263 (STHUX $rS, $ptrreg, $ptroff)>; 2264def : Pat<(pre_store i32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2265 (STWUX $rS, $ptrreg, $ptroff)>; 2266let Predicates = [HasFPU] in { 2267def : Pat<(pre_store f32:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2268 (STFSUX $rS, $ptrreg, $ptroff)>; 2269def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 2270 (STFDUX $rS, $ptrreg, $ptroff)>; 2271} 2272 2273// Store Multiple 2274let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in 2275def STMW : DForm_1<47, (outs), (ins gprc:$RST, (memri $D, $RA):$dst), 2276 "stmw $RST, $dst", IIC_LdStLMW, []>; 2277 2278def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L), 2279 "sync $L", IIC_LdStSync, []>; 2280 2281let isCodeGenOnly = 1 in { 2282 def MSYNC : XForm_24_sync<31, 598, (outs), (ins), 2283 "msync", IIC_LdStSync, []> { 2284 let L = 0; 2285 } 2286} 2287 2288// We used to have EIEIO as value but E[0-9A-Z] is a reserved name 2289def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins), 2290 "eieio", IIC_LdStLoad, []>; 2291 2292def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO", 2293 [(int_ppc_eieio)]>; 2294 2295def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2296def : Pat<(int_ppc_iospace_sync), (SYNC 0)>, Requires<[HasSYNC]>; 2297def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2298def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>; 2299def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2300def : Pat<(int_ppc_iospace_sync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2301def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2302def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 2303def : Pat<(int_ppc_eieio), (PseudoEIEIO)>; 2304def : Pat<(int_ppc_iospace_eieio), (PseudoEIEIO)>; 2305 2306//===----------------------------------------------------------------------===// 2307// PPC32 Arithmetic Instructions. 2308// 2309 2310let PPC970_Unit = 1 in { // FXU Operations. 2311def ADDI : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2312 "addi $RST, $RA, $D", IIC_IntSimple, 2313 [(set i32:$RST, (add i32:$RA, imm32SExt16:$D))]>; 2314let BaseName = "addic" in { 2315let Defs = [CARRY] in 2316def ADDIC : DForm_2<12, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2317 "addic $RST, $RA, $D", IIC_IntGeneral, 2318 [(set i32:$RST, (PPCaddc i32:$RA, imm32SExt16:$D))]>, 2319 RecFormRel, PPC970_DGroup_Cracked; 2320let Defs = [CARRY, CR0] in 2321def ADDIC_rec : DForm_2<13, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2322 "addic. $RST, $RA, $D", IIC_IntGeneral, 2323 []>, isRecordForm, RecFormRel; 2324} 2325def ADDIS : DForm_2<15, (outs gprc:$RST), (ins gprc_nor0:$RA, s17imm:$D), 2326 "addis $RST, $RA, $D", IIC_IntSimple, 2327 [(set i32:$RST, (add i32:$RA, imm16ShiftedSExt:$D))]>; 2328let isCodeGenOnly = 1 in 2329def LA : DForm_2<14, (outs gprc:$RST), (ins gprc_nor0:$RA, s16imm:$D), 2330 "la $RST, $D($RA)", IIC_IntGeneral, 2331 [(set i32:$RST, (add i32:$RA, 2332 (PPClo tglobaladdr:$D, 0)))]>, MemriOp; 2333def MULLI : DForm_2< 7, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2334 "mulli $RST, $RA, $D", IIC_IntMulLI, 2335 [(set i32:$RST, (mul i32:$RA, imm32SExt16:$D))]>; 2336let Defs = [CARRY] in 2337def SUBFIC : DForm_2< 8, (outs gprc:$RST), (ins gprc:$RA, s16imm:$D), 2338 "subfic $RST, $RA, $D", IIC_IntGeneral, 2339 [(set i32:$RST, (PPCsubc imm32SExt16:$D, i32:$RA))]>; 2340 2341let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 2342 def LI : DForm_2_r0<14, (outs gprc:$RST), (ins s16imm:$D), 2343 "li $RST, $D", IIC_IntSimple, 2344 [(set i32:$RST, imm32SExt16:$D)]>, SExt32To64; 2345 def LIS : DForm_2_r0<15, (outs gprc:$RST), (ins s17imm:$D), 2346 "lis $RST, $D", IIC_IntSimple, 2347 [(set i32:$RST, imm16ShiftedSExt:$D)]>, SExt32To64; 2348} 2349} 2350 2351def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>; 2352def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>; 2353 2354let PPC970_Unit = 1 in { // FXU Operations. 2355let Defs = [CR0] in { 2356def ANDI_rec : DForm_4<28, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2357 "andi. $RA, $RST, $D", IIC_IntGeneral, 2358 [(set i32:$RA, (and i32:$RST, immZExt16:$D))]>, 2359 isRecordForm, ZExt32To64, SExt32To64; 2360def ANDIS_rec : DForm_4<29, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2361 "andis. $RA, $RST, $D", IIC_IntGeneral, 2362 [(set i32:$RA, (and i32:$RST, imm16ShiftedZExt:$D))]>, 2363 isRecordForm, ZExt32To64; 2364} 2365def ORI : DForm_4<24, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2366 "ori $RA, $RST, $D", IIC_IntSimple, 2367 [(set i32:$RA, (or i32:$RST, immZExt16:$D))]>; 2368def ORIS : DForm_4<25, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2369 "oris $RA, $RST, $D", IIC_IntSimple, 2370 [(set i32:$RA, (or i32:$RST, imm16ShiftedZExt:$D))]>; 2371def XORI : DForm_4<26, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2372 "xori $RA, $RST, $D", IIC_IntSimple, 2373 [(set i32:$RA, (xor i32:$RST, immZExt16:$D))]>; 2374def XORIS : DForm_4<27, (outs gprc:$RA), (ins gprc:$RST, u16imm:$D), 2375 "xoris $RA, $RST, $D", IIC_IntSimple, 2376 [(set i32:$RA, (xor i32:$RST, imm16ShiftedZExt:$D))]>; 2377 2378def NOP : DForm_4_zero<24, (outs), (ins), "nop", IIC_IntSimple, 2379 []>; 2380let isCodeGenOnly = 1 in { 2381// The POWER6 and POWER7 have special group-terminating nops. 2382def NOP_GT_PWR6 : DForm_4_fixedreg_zero<24, 1, (outs), (ins), 2383 "ori 1, 1, 0", IIC_IntSimple, []>; 2384def NOP_GT_PWR7 : DForm_4_fixedreg_zero<24, 2, (outs), (ins), 2385 "ori 2, 2, 0", IIC_IntSimple, []>; 2386} 2387 2388let isCompare = 1, hasSideEffects = 0 in { 2389 def CMPWI : DForm_5_ext<11, (outs crrc:$BF), (ins gprc:$RA, s16imm:$D), 2390 "cmpwi $BF, $RA, $D", IIC_IntCompare>; 2391 def CMPLWI : DForm_6_ext<10, (outs crrc:$BF), (ins gprc:$RA, u16imm:$D), 2392 "cmplwi $BF, $RA, $D", IIC_IntCompare>; 2393 def CMPRB : X_BF3_L1_RS5_RS5<31, 192, (outs crrc:$BF), 2394 (ins u1imm:$L, gprc:$RA, gprc:$RB), 2395 "cmprb $BF, $L, $RA, $RB", IIC_IntCompare, []>, 2396 Requires<[IsISA3_0]>; 2397} 2398} 2399 2400let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2401let isCommutable = 1 in { 2402defm NAND : XForm_6r<31, 476, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2403 "nand", "$RA, $RST, $RB", IIC_IntSimple, 2404 [(set i32:$RA, (not (and i32:$RST, i32:$RB)))]>; 2405defm AND : XForm_6r<31, 28, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2406 "and", "$RA, $RST, $RB", IIC_IntSimple, 2407 [(set i32:$RA, (and i32:$RST, i32:$RB))]>; 2408} // isCommutable 2409defm ANDC : XForm_6r<31, 60, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2410 "andc", "$RA, $RST, $RB", IIC_IntSimple, 2411 [(set i32:$RA, (and i32:$RST, (not i32:$RB)))]>; 2412let isCommutable = 1 in { 2413defm OR : XForm_6r<31, 444, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2414 "or", "$RA, $RST, $RB", IIC_IntSimple, 2415 [(set i32:$RA, (or i32:$RST, i32:$RB))]>; 2416defm NOR : XForm_6r<31, 124, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2417 "nor", "$RA, $RST, $RB", IIC_IntSimple, 2418 [(set i32:$RA, (not (or i32:$RST, i32:$RB)))]>; 2419} // isCommutable 2420defm ORC : XForm_6r<31, 412, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2421 "orc", "$RA, $RST, $RB", IIC_IntSimple, 2422 [(set i32:$RA, (or i32:$RST, (not i32:$RB)))]>; 2423let isCommutable = 1 in { 2424defm EQV : XForm_6r<31, 284, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2425 "eqv", "$RA, $RST, $RB", IIC_IntSimple, 2426 [(set i32:$RA, (not (xor i32:$RST, i32:$RB)))]>; 2427defm XOR : XForm_6r<31, 316, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2428 "xor", "$RA, $RST, $RB", IIC_IntSimple, 2429 [(set i32:$RA, (xor i32:$RST, i32:$RB))]>; 2430} // isCommutable 2431defm SLW : XForm_6r<31, 24, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2432 "slw", "$RA, $RST, $RB", IIC_IntGeneral, 2433 [(set i32:$RA, (PPCshl i32:$RST, i32:$RB))]>, ZExt32To64; 2434defm SRW : XForm_6r<31, 536, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2435 "srw", "$RA, $RST, $RB", IIC_IntGeneral, 2436 [(set i32:$RA, (PPCsrl i32:$RST, i32:$RB))]>, ZExt32To64; 2437defm SRAW : XForm_6rc<31, 792, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2438 "sraw", "$RA, $RST, $RB", IIC_IntShift, 2439 [(set i32:$RA, (PPCsra i32:$RST, i32:$RB))]>, SExt32To64; 2440} 2441 2442def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>; 2443def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>; 2444 2445def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>; 2446def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>; 2447 2448def : InstAlias<"nop", (ORI R0, R0, 0)>; 2449 2450let PPC970_Unit = 1 in { // FXU Operations. 2451let hasSideEffects = 0 in { 2452defm SRAWI : XForm_10rc<31, 824, (outs gprc:$RA), (ins gprc:$RST, u5imm:$RB), 2453 "srawi", "$RA, $RST, $RB", IIC_IntShift, 2454 [(set i32:$RA, (sra i32:$RST, (i32 imm:$RB)))]>, 2455 SExt32To64; 2456defm CNTLZW : XForm_11r<31, 26, (outs gprc:$RA), (ins gprc:$RST), 2457 "cntlzw", "$RA, $RST", IIC_IntGeneral, 2458 [(set i32:$RA, (ctlz i32:$RST))]>, ZExt32To64; 2459defm CNTTZW : XForm_11r<31, 538, (outs gprc:$RA), (ins gprc:$RST), 2460 "cnttzw", "$RA, $RST", IIC_IntGeneral, 2461 [(set i32:$RA, (cttz i32:$RST))]>, Requires<[IsISA3_0]>, 2462 ZExt32To64; 2463defm EXTSB : XForm_11r<31, 954, (outs gprc:$RA), (ins gprc:$RST), 2464 "extsb", "$RA, $RST", IIC_IntSimple, 2465 [(set i32:$RA, (sext_inreg i32:$RST, i8))]>, SExt32To64; 2466defm EXTSH : XForm_11r<31, 922, (outs gprc:$RA), (ins gprc:$RST), 2467 "extsh", "$RA, $RST", IIC_IntSimple, 2468 [(set i32:$RA, (sext_inreg i32:$RST, i16))]>, SExt32To64; 2469 2470let isCommutable = 1 in 2471def CMPB : XForm_6<31, 508, (outs gprc:$RA), (ins gprc:$RST, gprc:$RB), 2472 "cmpb $RA, $RST, $RB", IIC_IntGeneral, 2473 [(set i32:$RA, (PPCcmpb i32:$RST, i32:$RB))]>; 2474} 2475let isCompare = 1, hasSideEffects = 0 in { 2476 def CMPW : XForm_16_ext<31, 0, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2477 "cmpw $BF, $RA, $RB", IIC_IntCompare>; 2478 def CMPLW : XForm_16_ext<31, 32, (outs crrc:$BF), (ins gprc:$RA, gprc:$RB), 2479 "cmplw $BF, $RA, $RB", IIC_IntCompare>; 2480} 2481} 2482let PPC970_Unit = 3, Predicates = [HasFPU] in { // FPU Operations. 2483let isCompare = 1, mayRaiseFPException = 1, hasSideEffects = 0 in { 2484 def FCMPUS : XForm_17<63, 0, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2485 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2486 def FCMPOS : XForm_17<63, 32, (outs crrc:$BF), (ins f4rc:$RA, f4rc:$RB), 2487 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2488 let Interpretation64Bit = 1, isCodeGenOnly = 1 in { 2489 def FCMPUD : XForm_17<63, 0, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2490 "fcmpu $BF, $RA, $RB", IIC_FPCompare>; 2491 def FCMPOD : XForm_17<63, 32, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2492 "fcmpo $BF, $RA, $RB", IIC_FPCompare>; 2493 } 2494} 2495 2496def FTDIV: XForm_17<63, 128, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB), 2497 "ftdiv $BF, $RA, $RB", IIC_FPCompare>; 2498def FTSQRT: XForm_17a<63, 160, (outs crrc:$BF), (ins f8rc:$RB), 2499 "ftsqrt $BF, $RB", IIC_FPCompare, 2500 [(set i32:$BF, (PPCftsqrt f64:$RB))]>; 2501 2502let mayRaiseFPException = 1, hasSideEffects = 0 in { 2503 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2504 defm FRIND : XForm_26r<63, 392, (outs f8rc:$RST), (ins f8rc:$RB), 2505 "frin", "$RST, $RB", IIC_FPGeneral, 2506 [(set f64:$RST, (any_fround f64:$RB))]>; 2507 defm FRINS : XForm_26r<63, 392, (outs f4rc:$RST), (ins f4rc:$RB), 2508 "frin", "$RST, $RB", IIC_FPGeneral, 2509 [(set f32:$RST, (any_fround f32:$RB))]>; 2510 2511 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2512 defm FRIPD : XForm_26r<63, 456, (outs f8rc:$RST), (ins f8rc:$RB), 2513 "frip", "$RST, $RB", IIC_FPGeneral, 2514 [(set f64:$RST, (any_fceil f64:$RB))]>; 2515 defm FRIPS : XForm_26r<63, 456, (outs f4rc:$RST), (ins f4rc:$RB), 2516 "frip", "$RST, $RB", IIC_FPGeneral, 2517 [(set f32:$RST, (any_fceil f32:$RB))]>; 2518 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2519 defm FRIZD : XForm_26r<63, 424, (outs f8rc:$RST), (ins f8rc:$RB), 2520 "friz", "$RST, $RB", IIC_FPGeneral, 2521 [(set f64:$RST, (any_ftrunc f64:$RB))]>; 2522 defm FRIZS : XForm_26r<63, 424, (outs f4rc:$RST), (ins f4rc:$RB), 2523 "friz", "$RST, $RB", IIC_FPGeneral, 2524 [(set f32:$RST, (any_ftrunc f32:$RB))]>; 2525 let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2526 defm FRIMD : XForm_26r<63, 488, (outs f8rc:$RST), (ins f8rc:$RB), 2527 "frim", "$RST, $RB", IIC_FPGeneral, 2528 [(set f64:$RST, (any_ffloor f64:$RB))]>; 2529 defm FRIMS : XForm_26r<63, 488, (outs f4rc:$RST), (ins f4rc:$RB), 2530 "frim", "$RST, $RB", IIC_FPGeneral, 2531 [(set f32:$RST, (any_ffloor f32:$RB))]>; 2532} 2533 2534let Uses = [RM], mayRaiseFPException = 1, hasSideEffects = 0 in { 2535 defm FCTIW : XForm_26r<63, 14, (outs f8rc:$RST), (ins f8rc:$RB), 2536 "fctiw", "$RST, $RB", IIC_FPGeneral, 2537 []>; 2538 defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$RST), (ins f8rc:$RB), 2539 "fctiwu", "$RST, $RB", IIC_FPGeneral, 2540 []>; 2541 defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$RST), (ins f8rc:$RB), 2542 "fctiwz", "$RST, $RB", IIC_FPGeneral, 2543 [(set f64:$RST, (PPCany_fctiwz f64:$RB))]>; 2544 2545 defm FRSP : XForm_26r<63, 12, (outs f4rc:$RST), (ins f8rc:$RB), 2546 "frsp", "$RST, $RB", IIC_FPGeneral, 2547 [(set f32:$RST, (any_fpround f64:$RB))]>; 2548 2549 defm FSQRT : XForm_26r<63, 22, (outs f8rc:$RST), (ins f8rc:$RB), 2550 "fsqrt", "$RST, $RB", IIC_FPSqrtD, 2551 [(set f64:$RST, (any_fsqrt f64:$RB))]>; 2552 defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$RST), (ins f4rc:$RB), 2553 "fsqrts", "$RST, $RB", IIC_FPSqrtS, 2554 [(set f32:$RST, (any_fsqrt f32:$RB))]>; 2555} 2556} 2557 2558def : Pat<(PPCfsqrt f64:$frA), (FSQRT $frA)>; 2559 2560/// Note that FMR is defined as pseudo-ops on the PPC970 because they are 2561/// often coalesced away and we don't want the dispatch group builder to think 2562/// that they will fill slots (which could cause the load of a LSU reject to 2563/// sneak into a d-group with a store). 2564let hasSideEffects = 0, Predicates = [HasFPU] in 2565defm FMR : XForm_26r<63, 72, (outs f4rc:$RST), (ins f4rc:$RB), 2566 "fmr", "$RST, $RB", IIC_FPGeneral, 2567 []>, // (set f32:$RST, f32:$RB) 2568 PPC970_Unit_Pseudo; 2569 2570let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 2571// These are artificially split into two different forms, for 4/8 byte FP. 2572defm FABSS : XForm_26r<63, 264, (outs f4rc:$RST), (ins f4rc:$RB), 2573 "fabs", "$RST, $RB", IIC_FPGeneral, 2574 [(set f32:$RST, (fabs f32:$RB))]>; 2575let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2576defm FABSD : XForm_26r<63, 264, (outs f8rc:$RST), (ins f8rc:$RB), 2577 "fabs", "$RST, $RB", IIC_FPGeneral, 2578 [(set f64:$RST, (fabs f64:$RB))]>; 2579defm FNABSS : XForm_26r<63, 136, (outs f4rc:$RST), (ins f4rc:$RB), 2580 "fnabs", "$RST, $RB", IIC_FPGeneral, 2581 [(set f32:$RST, (fneg (fabs f32:$RB)))]>; 2582let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2583defm FNABSD : XForm_26r<63, 136, (outs f8rc:$RST), (ins f8rc:$RB), 2584 "fnabs", "$RST, $RB", IIC_FPGeneral, 2585 [(set f64:$RST, (fneg (fabs f64:$RB)))]>; 2586defm FNEGS : XForm_26r<63, 40, (outs f4rc:$RST), (ins f4rc:$RB), 2587 "fneg", "$RST, $RB", IIC_FPGeneral, 2588 [(set f32:$RST, (fneg f32:$RB))]>; 2589let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2590defm FNEGD : XForm_26r<63, 40, (outs f8rc:$RST), (ins f8rc:$RB), 2591 "fneg", "$RST, $RB", IIC_FPGeneral, 2592 [(set f64:$RST, (fneg f64:$RB))]>; 2593 2594defm FCPSGNS : XForm_28r<63, 8, (outs f4rc:$RST), (ins f4rc:$RA, f4rc:$RB), 2595 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2596 [(set f32:$RST, (fcopysign f32:$RB, f32:$RA))]>; 2597let Interpretation64Bit = 1, isCodeGenOnly = 1 in 2598defm FCPSGND : XForm_28r<63, 8, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB), 2599 "fcpsgn", "$RST, $RA, $RB", IIC_FPGeneral, 2600 [(set f64:$RST, (fcopysign f64:$RB, f64:$RA))]>; 2601 2602// Reciprocal estimates. 2603let mayRaiseFPException = 1 in { 2604defm FRE : XForm_26r<63, 24, (outs f8rc:$RST), (ins f8rc:$RB), 2605 "fre", "$RST, $RB", IIC_FPGeneral, 2606 [(set f64:$RST, (PPCfre f64:$RB))]>; 2607defm FRES : XForm_26r<59, 24, (outs f4rc:$RST), (ins f4rc:$RB), 2608 "fres", "$RST, $RB", IIC_FPGeneral, 2609 [(set f32:$RST, (PPCfre f32:$RB))]>; 2610defm FRSQRTE : XForm_26r<63, 26, (outs f8rc:$RST), (ins f8rc:$RB), 2611 "frsqrte", "$RST, $RB", IIC_FPGeneral, 2612 [(set f64:$RST, (PPCfrsqrte f64:$RB))]>; 2613defm FRSQRTES : XForm_26r<59, 26, (outs f4rc:$RST), (ins f4rc:$RB), 2614 "frsqrtes", "$RST, $RB", IIC_FPGeneral, 2615 [(set f32:$RST, (PPCfrsqrte f32:$RB))]>; 2616} 2617} 2618 2619// XL-Form instructions. condition register logical ops. 2620// 2621let hasSideEffects = 0 in 2622def MCRF : XLForm_3<19, 0, (outs crrc:$BF), (ins crrc:$BFA), 2623 "mcrf $BF, $BFA", IIC_BrMCR>, 2624 PPC970_DGroup_First, PPC970_Unit_CRU; 2625 2626// FIXME: According to the ISA (section 2.5.1 of version 2.06), the 2627// condition-register logical instructions have preferred forms. Specifically, 2628// it is preferred that the bit specified by the BT field be in the same 2629// condition register as that specified by the bit BB. We might want to account 2630// for this via hinting the register allocator and anti-dep breakers, or we 2631// could constrain the register class to force this constraint and then loosen 2632// it during register allocation via convertToThreeAddress or some similar 2633// mechanism. 2634 2635let isCommutable = 1 in { 2636def CRAND : XLForm_1<19, 257, (outs crbitrc:$CRD), 2637 (ins crbitrc:$CRA, crbitrc:$CRB), 2638 "crand $CRD, $CRA, $CRB", IIC_BrCR, 2639 [(set i1:$CRD, (and i1:$CRA, i1:$CRB))]>; 2640 2641def CRNAND : XLForm_1<19, 225, (outs crbitrc:$CRD), 2642 (ins crbitrc:$CRA, crbitrc:$CRB), 2643 "crnand $CRD, $CRA, $CRB", IIC_BrCR, 2644 [(set i1:$CRD, (not (and i1:$CRA, i1:$CRB)))]>; 2645 2646def CROR : XLForm_1<19, 449, (outs crbitrc:$CRD), 2647 (ins crbitrc:$CRA, crbitrc:$CRB), 2648 "cror $CRD, $CRA, $CRB", IIC_BrCR, 2649 [(set i1:$CRD, (or i1:$CRA, i1:$CRB))]>; 2650 2651def CRXOR : XLForm_1<19, 193, (outs crbitrc:$CRD), 2652 (ins crbitrc:$CRA, crbitrc:$CRB), 2653 "crxor $CRD, $CRA, $CRB", IIC_BrCR, 2654 [(set i1:$CRD, (xor i1:$CRA, i1:$CRB))]>; 2655 2656def CRNOR : XLForm_1<19, 33, (outs crbitrc:$CRD), 2657 (ins crbitrc:$CRA, crbitrc:$CRB), 2658 "crnor $CRD, $CRA, $CRB", IIC_BrCR, 2659 [(set i1:$CRD, (not (or i1:$CRA, i1:$CRB)))]>; 2660def CREQV : XLForm_1<19, 289, (outs crbitrc:$CRD), 2661 (ins crbitrc:$CRA, crbitrc:$CRB), 2662 "creqv $CRD, $CRA, $CRB", IIC_BrCR, 2663 [(set i1:$CRD, (not (xor i1:$CRA, i1:$CRB)))]>; 2664} // isCommutable 2665 2666let isCodeGenOnly = 1 in 2667def CRNOT : XLForm_1s<19, 33, (outs crbitrc:$CRD), (ins crbitrc:$CRA), 2668 "crnot $CRD, $CRA", IIC_BrCR, 2669 [(set i1:$CRD, (not i1:$CRA))]>; 2670 2671def CRANDC : XLForm_1<19, 129, (outs crbitrc:$CRD), 2672 (ins crbitrc:$CRA, crbitrc:$CRB), 2673 "crandc $CRD, $CRA, $CRB", IIC_BrCR, 2674 [(set i1:$CRD, (and i1:$CRA, (not i1:$CRB)))]>; 2675 2676def CRORC : XLForm_1<19, 417, (outs crbitrc:$CRD), 2677 (ins crbitrc:$CRA, crbitrc:$CRB), 2678 "crorc $CRD, $CRA, $CRB", IIC_BrCR, 2679 [(set i1:$CRD, (or i1:$CRA, (not i1:$CRB)))]>; 2680 2681let isCodeGenOnly = 1 in { 2682let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 2683def CRSET : XLForm_1_ext<19, 289, (outs crbitrc:$CRD), (ins), 2684 "creqv $CRD, $CRD, $CRD", IIC_BrCR, 2685 [(set i1:$CRD, 1)]>; 2686 2687def CRUNSET: XLForm_1_ext<19, 193, (outs crbitrc:$CRD), (ins), 2688 "crxor $CRD, $CRD, $CRD", IIC_BrCR, 2689 [(set i1:$CRD, 0)]>; 2690} 2691 2692let Defs = [CR1EQ], CRD = 6 in { 2693def CR6SET : XLForm_1_ext<19, 289, (outs), (ins), 2694 "creqv 6, 6, 6", IIC_BrCR, 2695 [(PPCcr6set)]>; 2696 2697def CR6UNSET: XLForm_1_ext<19, 193, (outs), (ins), 2698 "crxor 6, 6, 6", IIC_BrCR, 2699 [(PPCcr6unset)]>; 2700} 2701} 2702 2703// XFX-Form instructions. Instructions that deal with SPRs. 2704// 2705 2706def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR), 2707 "mfspr $RST, $SPR", IIC_SprMFSPR>; 2708def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST), 2709 "mtspr $SPR, $RST", IIC_SprMTSPR>; 2710 2711def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR), 2712 "mftb $RST, $SPR", IIC_SprMFTB>; 2713 2714def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR), 2715 "mfpmr $RST, $SPR", IIC_SprMFPMR>; 2716 2717def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST), 2718 "mtpmr $SPR, $RST", IIC_SprMTPMR>; 2719 2720 2721// A pseudo-instruction used to implement the read of the 64-bit cycle counter 2722// on a 32-bit target. 2723let hasSideEffects = 1 in 2724def ReadTB : PPCCustomInserterPseudo<(outs gprc:$lo, gprc:$hi), (ins), 2725 "#ReadTB", []>; 2726 2727let Uses = [CTR] in { 2728def MFCTR : XFXForm_1_ext<31, 339, 9, (outs gprc:$RST), (ins), 2729 "mfctr $RST", IIC_SprMFSPR>, 2730 PPC970_DGroup_First, PPC970_Unit_FXU; 2731} 2732let Defs = [CTR], Pattern = [(PPCmtctr i32:$RST)] in { 2733def MTCTR : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2734 "mtctr $RST", IIC_SprMTSPR>, 2735 PPC970_DGroup_First, PPC970_Unit_FXU; 2736} 2737let hasSideEffects = 1, isCodeGenOnly = 1, isNotDuplicable = 1, Defs = [CTR] in { 2738let Pattern = [(int_set_loop_iterations i32:$RST)] in 2739def MTCTRloop : XFXForm_1_ext<31, 467, 9, (outs), (ins gprc:$RST), 2740 "mtctr $RST", IIC_SprMTSPR>, 2741 PPC970_DGroup_First, PPC970_Unit_FXU; 2742} 2743 2744let hasSideEffects = 1, hasNoSchedulingInfo = 1, isNotDuplicable = 1, Uses = [CTR], Defs = [CTR] in 2745def DecreaseCTRloop : PPCEmitTimePseudo<(outs crbitrc:$rT), (ins i32imm:$stride), 2746 "#DecreaseCTRloop", [(set i1:$rT, (int_loop_decrement (i32 imm:$stride)))]>; 2747 2748let hasSideEffects = 0 in { 2749let Defs = [LR] in { 2750def MTLR : XFXForm_1_ext<31, 467, 8, (outs), (ins gprc:$RST), 2751 "mtlr $RST", IIC_SprMTSPR>, 2752 PPC970_DGroup_First, PPC970_Unit_FXU; 2753} 2754let Uses = [LR] in { 2755def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$RST), (ins), 2756 "mflr $RST", IIC_SprMFSPR>, 2757 PPC970_DGroup_First, PPC970_Unit_FXU; 2758} 2759} 2760 2761let hasSideEffects = 1 in { 2762 def MTUDSCR : XFXForm_1_ext<31, 467, 3, (outs), (ins gprc:$RST), 2763 "mtspr 3, $RST", IIC_SprMTSPR>, 2764 PPC970_DGroup_Single, PPC970_Unit_FXU; 2765 def MFUDSCR : XFXForm_1_ext<31, 339, 3, (outs gprc:$RST), (ins), 2766 "mfspr $RST, 3", IIC_SprMFSPR>, 2767 PPC970_DGroup_First, PPC970_Unit_FXU; 2768} 2769 2770// Disable these alias on AIX since they are not supported. 2771let Predicates = [ModernAs] in { 2772// Aliases for moving to/from dscr to mtspr/mfspr 2773def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>; 2774def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>; 2775} 2776 2777let isCodeGenOnly = 1 in { 2778 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed 2779 // like a GPR on the PPC970. As such, copies in and out have the same 2780 // performance characteristics as an OR instruction. 2781 def MTVRSAVE : XFXForm_1_ext<31, 467, 256, (outs), (ins gprc:$RST), 2782 "mtspr 256, $RST", IIC_IntGeneral>, 2783 PPC970_DGroup_Single, PPC970_Unit_FXU; 2784 def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), (ins), 2785 "mfspr $RST, 256", IIC_IntGeneral>, 2786 PPC970_DGroup_First, PPC970_Unit_FXU; 2787 2788 def MTVRSAVEv : XFXForm_1_ext<31, 467, 256, 2789 (outs VRSAVERC:$SPR), (ins gprc:$RST), 2790 "mtspr 256, $RST", IIC_IntGeneral>, 2791 PPC970_DGroup_Single, PPC970_Unit_FXU; 2792 def MFVRSAVEv : XFXForm_1_ext<31, 339, 256, (outs gprc:$RST), 2793 (ins VRSAVERC:$SPR), 2794 "mfspr $RST, 256", IIC_IntGeneral>, 2795 PPC970_DGroup_First, PPC970_Unit_FXU; 2796} 2797 2798// Aliases for mtvrsave/mfvrsave to mfspr/mtspr. 2799def : InstAlias<"mtvrsave $rS", (MTVRSAVE gprc:$rS)>; 2800def : InstAlias<"mfvrsave $rS", (MFVRSAVE gprc:$rS)>; 2801 2802let hasSideEffects = 0 in { 2803// mtocrf's input needs to be prepared by shifting by an amount dependent 2804// on the cr register selected. Thus, post-ra anti-dep breaking must not 2805// later change that register assignment. 2806let hasExtraDefRegAllocReq = 1 in { 2807def MTOCRF: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins gprc:$RST), 2808 "mtocrf $FXM, $RST", IIC_BrMCRX>, 2809 PPC970_DGroup_First, PPC970_Unit_CRU; 2810 2811// Similarly to mtocrf, the mask for mtcrf must be prepared in a way that 2812// is dependent on the cr fields being set. 2813def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$RST), 2814 "mtcrf $FXM, $RST", IIC_BrMCRX>, 2815 PPC970_MicroCode, PPC970_Unit_CRU; 2816} // hasExtraDefRegAllocReq = 1 2817 2818// mfocrf's input needs to be prepared by shifting by an amount dependent 2819// on the cr register selected. Thus, post-ra anti-dep breaking must not 2820// later change that register assignment. 2821let hasExtraSrcRegAllocReq = 1 in { 2822def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$RST), (ins crbitm:$FXM), 2823 "mfocrf $RST, $FXM", IIC_SprMFCRF>, 2824 PPC970_DGroup_First, PPC970_Unit_CRU; 2825 2826// Similarly to mfocrf, the mask for mfcrf must be prepared in a way that 2827// is dependent on the cr fields being copied. 2828def MFCR : XFXForm_3<31, 19, (outs gprc:$RT), (ins), 2829 "mfcr $RT", IIC_SprMFCR>, 2830 PPC970_MicroCode, PPC970_Unit_CRU; 2831} // hasExtraSrcRegAllocReq = 1 2832 2833def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins), 2834 "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>; 2835} // hasSideEffects = 0 2836 2837def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>; 2838 2839let Predicates = [HasFPU] in { 2840// Custom inserter instruction to perform FADD in round-to-zero mode. 2841let Uses = [RM], mayRaiseFPException = 1 in { 2842 def FADDrtz: PPCCustomInserterPseudo<(outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), "", 2843 [(set f64:$FRT, (PPCany_faddrtz f64:$FRA, f64:$FRB))]>; 2844} 2845 2846// The above pseudo gets expanded to make use of the following instructions 2847// to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level. 2848 2849// When FM is 30/31, we are setting the 62/63 bit of FPSCR, the implicit-def 2850// RM should be set. 2851let hasSideEffects = 1, Defs = [RM] in { 2852def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM), 2853 "mtfsb0 $FM", IIC_IntMTFSB0, 2854 [(int_ppc_mtfsb0 timm:$FM)]>, 2855 PPC970_DGroup_Single, PPC970_Unit_FPU; 2856def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM), 2857 "mtfsb1 $FM", IIC_IntMTFSB0, 2858 [(int_ppc_mtfsb1 timm:$FM)]>, 2859 PPC970_DGroup_Single, PPC970_Unit_FPU; 2860} 2861 2862let Defs = [RM], hasSideEffects = 1 in { 2863 let isCodeGenOnly = 1 in 2864 def MTFSFb : XFLForm<63, 711, (outs), (ins i32imm:$FM, f8rc:$RT), 2865 "mtfsf $FM, $RT", IIC_IntMTFSB0, 2866 [(int_ppc_mtfsf timm:$FM, f64:$RT)]>, 2867 PPC970_DGroup_Single, PPC970_Unit_FPU; 2868} 2869let Uses = [RM], hasSideEffects = 1 in { 2870 def MFFS : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2871 "mffs $RST", IIC_IntMFFS, 2872 [(set f64:$RST, (PPCmffs))]>, 2873 PPC970_DGroup_Single, PPC970_Unit_FPU; 2874 2875 let Defs = [CR1] in 2876 def MFFS_rec : XForm_42<63, 583, (outs f8rc:$RST), (ins), 2877 "mffs. $RST", IIC_IntMFFS, []>, isRecordForm; 2878 2879 def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$RST), (ins), 2880 "mffsce $RST", IIC_IntMFFS, []>, 2881 PPC970_DGroup_Single, PPC970_Unit_FPU; 2882 2883 def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$RST), 2884 (ins f8rc:$FRB), "mffscdrn $RST, $FRB", 2885 IIC_IntMFFS, []>, 2886 PPC970_DGroup_Single, PPC970_Unit_FPU; 2887 2888 def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$RST), 2889 (ins u3imm:$DRM), 2890 "mffscdrni $RST, $DRM", 2891 IIC_IntMFFS, []>, 2892 PPC970_DGroup_Single, PPC970_Unit_FPU; 2893 2894 def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$RST), 2895 (ins f8rc:$FRB), "mffscrn $RST, $FRB", 2896 IIC_IntMFFS, []>, 2897 PPC970_DGroup_Single, PPC970_Unit_FPU; 2898 2899 def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$RST), 2900 (ins u2imm:$RM), "mffscrni $RST, $RM", 2901 IIC_IntMFFS, []>, 2902 PPC970_DGroup_Single, PPC970_Unit_FPU; 2903 2904 def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$RST), (ins), 2905 "mffsl $RST", IIC_IntMFFS, []>, 2906 PPC970_DGroup_Single, PPC970_Unit_FPU; 2907} 2908} 2909 2910let Predicates = [IsISA3_0] in { 2911def MODSW : XForm_8<31, 779, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2912 "modsw $RST, $RA, $RB", IIC_IntDivW, 2913 [(set i32:$RST, (srem i32:$RA, i32:$RB))]>; 2914def MODUW : XForm_8<31, 267, (outs gprc:$RST), (ins gprc:$RA, gprc:$RB), 2915 "moduw $RST, $RA, $RB", IIC_IntDivW, 2916 [(set i32:$RST, (urem i32:$RA, i32:$RB))]>; 2917let hasSideEffects = 1 in 2918def ADDEX : Z23Form_RTAB5_CY2<31, 170, (outs gprc:$RT), 2919 (ins gprc:$RA, gprc:$RB, u2imm:$CY), 2920 "addex $RT, $RA, $RB, $CY", IIC_IntGeneral, []>; 2921} 2922 2923let PPC970_Unit = 1, hasSideEffects = 0 in { // FXU Operations. 2924// XO-Form instructions. Arithmetic instructions that can set overflow bit 2925let isCommutable = 1 in 2926defm ADD4 : XOForm_1rx<31, 266, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2927 "add", "$RT, $RA, $RB", IIC_IntSimple, 2928 [(set i32:$RT, (add i32:$RA, i32:$RB))]>; 2929let isCodeGenOnly = 1 in 2930def ADD4TLS : XOForm_1<31, 266, 0, (outs gprc:$RT), (ins gprc:$RA, tlsreg32:$RB), 2931 "add $RT, $RA, $RB", IIC_IntSimple, 2932 [(set i32:$RT, (add i32:$RA, tglobaltlsaddr:$RB))]>; 2933let isCommutable = 1 in 2934defm ADDC : XOForm_1rc<31, 10, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2935 "addc", "$RT, $RA, $RB", IIC_IntGeneral, 2936 [(set i32:$RT, (PPCaddc i32:$RA, i32:$RB))]>, 2937 PPC970_DGroup_Cracked; 2938 2939defm DIVW : XOForm_1rcr<31, 491, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2940 "divw", "$RT, $RA, $RB", IIC_IntDivW, 2941 [(set i32:$RT, (sdiv i32:$RA, i32:$RB))]>; 2942defm DIVWU : XOForm_1rcr<31, 459, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2943 "divwu", "$RT, $RA, $RB", IIC_IntDivW, 2944 [(set i32:$RT, (udiv i32:$RA, i32:$RB))]>; 2945defm DIVWE : XOForm_1rcr<31, 427, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2946 "divwe", "$RT, $RA, $RB", IIC_IntDivW, 2947 [(set i32:$RT, (int_ppc_divwe gprc:$RA, gprc:$RB))]>, 2948 Requires<[HasExtDiv]>; 2949defm DIVWEU : XOForm_1rcr<31, 395, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2950 "divweu", "$RT, $RA, $RB", IIC_IntDivW, 2951 [(set i32:$RT, (int_ppc_divweu gprc:$RA, gprc:$RB))]>, 2952 Requires<[HasExtDiv]>; 2953let isCommutable = 1 in { 2954defm MULHW : XOForm_1r<31, 75, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2955 "mulhw", "$RT, $RA, $RB", IIC_IntMulHW, 2956 [(set i32:$RT, (mulhs i32:$RA, i32:$RB))]>; 2957defm MULHWU : XOForm_1r<31, 11, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2958 "mulhwu", "$RT, $RA, $RB", IIC_IntMulHWU, 2959 [(set i32:$RT, (mulhu i32:$RA, i32:$RB))]>; 2960defm MULLW : XOForm_1rx<31, 235, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2961 "mullw", "$RT, $RA, $RB", IIC_IntMulHW, 2962 [(set i32:$RT, (mul i32:$RA, i32:$RB))]>; 2963} // isCommutable 2964defm SUBF : XOForm_1rx<31, 40, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2965 "subf", "$RT, $RA, $RB", IIC_IntGeneral, 2966 [(set i32:$RT, (sub i32:$RB, i32:$RA))]>; 2967defm SUBFC : XOForm_1rc<31, 8, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2968 "subfc", "$RT, $RA, $RB", IIC_IntGeneral, 2969 [(set i32:$RT, (PPCsubc i32:$RB, i32:$RA))]>, 2970 PPC970_DGroup_Cracked; 2971defm NEG : XOForm_3r<31, 104, 0, (outs gprc:$RT), (ins gprc:$RA), 2972 "neg", "$RT, $RA", IIC_IntSimple, 2973 [(set i32:$RT, (ineg i32:$RA))]>; 2974let Uses = [CARRY] in { 2975let isCommutable = 1 in 2976defm ADDE : XOForm_1rc<31, 138, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2977 "adde", "$RT, $RA, $RB", IIC_IntGeneral, 2978 [(set i32:$RT, (PPCadde i32:$RA, i32:$RB, CARRY))]>; 2979defm ADDME : XOForm_3rc<31, 234, 0, (outs gprc:$RT), (ins gprc:$RA), 2980 "addme", "$RT, $RA", IIC_IntGeneral, 2981 [(set i32:$RT, (PPCadde i32:$RA, -1, CARRY))]>; 2982defm ADDZE : XOForm_3rc<31, 202, 0, (outs gprc:$RT), (ins gprc:$RA), 2983 "addze", "$RT, $RA", IIC_IntGeneral, 2984 [(set i32:$RT, (PPCadde i32:$RA, 0, CARRY))]>; 2985defm SUBFE : XOForm_1rc<31, 136, 0, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB), 2986 "subfe", "$RT, $RA, $RB", IIC_IntGeneral, 2987 [(set i32:$RT, (PPCsube i32:$RB, i32:$RA, CARRY))]>; 2988defm SUBFME : XOForm_3rc<31, 232, 0, (outs gprc:$RT), (ins gprc:$RA), 2989 "subfme", "$RT, $RA", IIC_IntGeneral, 2990 [(set i32:$RT, (PPCsube -1, i32:$RA, CARRY))]>; 2991defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$RT), (ins gprc:$RA), 2992 "subfze", "$RT, $RA", IIC_IntGeneral, 2993 [(set i32:$RT, (PPCsube 0, i32:$RA, CARRY))]>; 2994} 2995} 2996 2997def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>; 2998def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 2999def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>; 3000def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>; 3001 3002// A-Form instructions. Most of the instructions executed in the FPU are of 3003// this type. 3004// 3005let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in { // FPU Operations. 3006let mayRaiseFPException = 1, Uses = [RM] in { 3007let isCommutable = 1 in { 3008 defm FMADD : AForm_1r<63, 29, 3009 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3010 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3011 [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>; 3012 defm FMADDS : AForm_1r<59, 29, 3013 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3014 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3015 [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>; 3016 defm FMSUB : AForm_1r<63, 28, 3017 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3018 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3019 [(set f64:$FRT, 3020 (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>; 3021 defm FMSUBS : AForm_1r<59, 28, 3022 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3023 "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3024 [(set f32:$FRT, 3025 (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>; 3026 defm FNMADD : AForm_1r<63, 31, 3027 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3028 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3029 [(set f64:$FRT, 3030 (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>; 3031 defm FNMADDS : AForm_1r<59, 31, 3032 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3033 "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3034 [(set f32:$FRT, 3035 (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>; 3036 defm FNMSUB : AForm_1r<63, 30, 3037 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3038 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused, 3039 [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC, 3040 (fneg f64:$FRB))))]>; 3041 defm FNMSUBS : AForm_1r<59, 30, 3042 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3043 "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3044 [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC, 3045 (fneg f32:$FRB))))]>; 3046} // isCommutable 3047} 3048// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid 3049// having 4 of these, force the comparison to always be an 8-byte double (code 3050// should use an FMRSD if the input comparison value really wants to be a float) 3051// and 4/8 byte forms for the result and operand type.. 3052let Interpretation64Bit = 1, isCodeGenOnly = 1 in 3053defm FSELD : AForm_1r<63, 23, 3054 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), 3055 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3056 [(set f64:$FRT, (PPCfsel f64:$FRA, f64:$FRC, f64:$FRB))]>; 3057defm FSELS : AForm_1r<63, 23, 3058 (outs f4rc:$FRT), (ins f8rc:$FRA, f4rc:$FRC, f4rc:$FRB), 3059 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral, 3060 [(set f32:$FRT, (PPCfsel f64:$FRA, f32:$FRC, f32:$FRB))]>; 3061let Uses = [RM], mayRaiseFPException = 1 in { 3062 let isCommutable = 1 in { 3063 defm FADD : AForm_2r<63, 21, 3064 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3065 "fadd", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3066 [(set f64:$FRT, (any_fadd f64:$FRA, f64:$FRB))]>; 3067 defm FADDS : AForm_2r<59, 21, 3068 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3069 "fadds", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3070 [(set f32:$FRT, (any_fadd f32:$FRA, f32:$FRB))]>; 3071 } // isCommutable 3072 defm FDIV : AForm_2r<63, 18, 3073 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3074 "fdiv", "$FRT, $FRA, $FRB", IIC_FPDivD, 3075 [(set f64:$FRT, (any_fdiv f64:$FRA, f64:$FRB))]>; 3076 defm FDIVS : AForm_2r<59, 18, 3077 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3078 "fdivs", "$FRT, $FRA, $FRB", IIC_FPDivS, 3079 [(set f32:$FRT, (any_fdiv f32:$FRA, f32:$FRB))]>; 3080 let isCommutable = 1 in { 3081 defm FMUL : AForm_3r<63, 25, 3082 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC), 3083 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused, 3084 [(set f64:$FRT, (any_fmul f64:$FRA, f64:$FRC))]>; 3085 defm FMULS : AForm_3r<59, 25, 3086 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC), 3087 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral, 3088 [(set f32:$FRT, (any_fmul f32:$FRA, f32:$FRC))]>; 3089 } // isCommutable 3090 defm FSUB : AForm_2r<63, 20, 3091 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRB), 3092 "fsub", "$FRT, $FRA, $FRB", IIC_FPAddSub, 3093 [(set f64:$FRT, (any_fsub f64:$FRA, f64:$FRB))]>; 3094 defm FSUBS : AForm_2r<59, 20, 3095 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRB), 3096 "fsubs", "$FRT, $FRA, $FRB", IIC_FPGeneral, 3097 [(set f32:$FRT, (any_fsub f32:$FRA, f32:$FRB))]>; 3098 } 3099} 3100 3101let hasSideEffects = 0 in { 3102let PPC970_Unit = 1 in { // FXU Operations. 3103 let isSelect = 1 in 3104 def ISEL : AForm_4<31, 15, 3105 (outs gprc:$RT), (ins gprc_nor0:$RA, gprc:$RB, crbitrc:$COND), 3106 "isel $RT, $RA, $RB, $COND", IIC_IntISEL, 3107 []>; 3108} 3109 3110let PPC970_Unit = 1 in { // FXU Operations. 3111// M-Form instructions. rotate and mask instructions. 3112// 3113let isCommutable = 1 in { 3114// RLWIMI can be commuted if the rotate amount is zero. 3115defm RLWIMI : MForm_2r<20, (outs gprc:$RA), 3116 (ins gprc:$RAi, gprc:$RS, u5imm:$SH, u5imm:$MB, 3117 u5imm:$ME), "rlwimi", "$RA, $RS, $SH, $MB, $ME", 3118 IIC_IntRotate, []>, PPC970_DGroup_Cracked, 3119 RegConstraint<"$RAi = $RA">, NoEncode<"$RAi">; 3120} 3121let BaseName = "rlwinm" in { 3122def RLWINM : MForm_2<21, 3123 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3124 "rlwinm $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3125 []>, RecFormRel; 3126let Defs = [CR0] in 3127def RLWINM_rec : MForm_2<21, 3128 (outs gprc:$RA), (ins gprc:$RS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 3129 "rlwinm. $RA, $RS, $SH, $MB, $ME", IIC_IntGeneral, 3130 []>, isRecordForm, RecFormRel, PPC970_DGroup_Cracked; 3131} 3132defm RLWNM : MForm_1r<23, (outs gprc:$RA), 3133 (ins gprc:$RS, gprc:$RB, u5imm:$MB, u5imm:$ME), 3134 "rlwnm", "$RA, $RS, $RB, $MB, $ME", IIC_IntGeneral, 3135 []>; 3136} 3137} // hasSideEffects = 0 3138 3139//===----------------------------------------------------------------------===// 3140// PowerPC Instruction Patterns 3141// 3142 3143// Arbitrary immediate support. Implement in terms of LIS/ORI. 3144def : Pat<(i32 imm:$imm), 3145 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>; 3146 3147// Implement the 'not' operation with the NOR instruction. 3148def i32not : OutPatFrag<(ops node:$in), 3149 (NOR $in, $in)>; 3150def : Pat<(not i32:$in), 3151 (i32not $in)>; 3152 3153// ADD an arbitrary immediate. 3154def : Pat<(add i32:$in, imm:$imm), 3155 (ADDIS (ADDI $in, (LO16 imm:$imm)), (HA16 imm:$imm))>; 3156// OR an arbitrary immediate. 3157def : Pat<(or i32:$in, imm:$imm), 3158 (ORIS (ORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3159// XOR an arbitrary immediate. 3160def : Pat<(xor i32:$in, imm:$imm), 3161 (XORIS (XORI $in, (LO16 imm:$imm)), (HI16 imm:$imm))>; 3162// SUBFIC 3163def : Pat<(sub imm32SExt16:$imm, i32:$in), 3164 (SUBFIC $in, imm:$imm)>; 3165 3166// SHL/SRL 3167def : Pat<(shl i32:$in, (i32 imm:$imm)), 3168 (RLWINM $in, imm:$imm, 0, (SHL32 imm:$imm))>; 3169def : Pat<(srl i32:$in, (i32 imm:$imm)), 3170 (RLWINM $in, (SRL32 imm:$imm), imm:$imm, 31)>; 3171 3172// ROTL 3173def : Pat<(rotl i32:$in, i32:$sh), 3174 (RLWNM $in, $sh, 0, 31)>; 3175def : Pat<(rotl i32:$in, (i32 imm:$imm)), 3176 (RLWINM $in, imm:$imm, 0, 31)>; 3177 3178// RLWNM 3179def : Pat<(and (rotl i32:$in, i32:$sh), maskimm32:$imm), 3180 (RLWNM $in, $sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>; 3181 3182// Calls 3183def : Pat<(PPCcall (i32 tglobaladdr:$dst)), 3184 (BL tglobaladdr:$dst)>; 3185 3186def : Pat<(PPCcall (i32 texternalsym:$dst)), 3187 (BL texternalsym:$dst)>; 3188 3189def : Pat<(PPCcall_rm (i32 tglobaladdr:$dst)), 3190 (BL_RM tglobaladdr:$dst)>; 3191 3192def : Pat<(PPCcall_rm (i32 texternalsym:$dst)), 3193 (BL_RM texternalsym:$dst)>; 3194 3195// Calls for AIX only 3196def : Pat<(PPCcall (i32 mcsym:$dst)), 3197 (BL mcsym:$dst)>; 3198 3199def : Pat<(PPCcall_nop (i32 mcsym:$dst)), 3200 (BL_NOP mcsym:$dst)>; 3201 3202def : Pat<(PPCcall_nop (i32 texternalsym:$dst)), 3203 (BL_NOP texternalsym:$dst)>; 3204 3205def : Pat<(PPCcall_rm (i32 mcsym:$dst)), 3206 (BL_RM mcsym:$dst)>; 3207 3208def : Pat<(PPCcall_nop_rm (i32 mcsym:$dst)), 3209 (BL_NOP_RM mcsym:$dst)>; 3210 3211def : Pat<(PPCcall_nop_rm (i32 texternalsym:$dst)), 3212 (BL_NOP_RM texternalsym:$dst)>; 3213 3214def : Pat<(PPCtc_return (i32 tglobaladdr:$dst), imm:$imm), 3215 (TCRETURNdi tglobaladdr:$dst, imm:$imm)>; 3216 3217def : Pat<(PPCtc_return (i32 texternalsym:$dst), imm:$imm), 3218 (TCRETURNdi texternalsym:$dst, imm:$imm)>; 3219 3220def : Pat<(PPCtc_return CTRRC:$dst, imm:$imm), 3221 (TCRETURNri CTRRC:$dst, imm:$imm)>; 3222 3223def : Pat<(int_ppc_fence), (FENCE)>; 3224def : Pat<(int_ppc_readflm), (MFFS)>; 3225def : Pat<(int_ppc_mffsl), (MFFSL)>; 3226 3227// Hi and Lo for Darwin Global Addresses. 3228def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>; 3229def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>; 3230def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>; 3231def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>; 3232def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>; 3233def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>; 3234def : Pat<(PPChi tblockaddress:$in, 0), (LIS tblockaddress:$in)>; 3235def : Pat<(PPClo tblockaddress:$in, 0), (LI tblockaddress:$in)>; 3236def : Pat<(PPChi tglobaltlsaddr:$g, i32:$in), 3237 (ADDIS $in, tglobaltlsaddr:$g)>; 3238def : Pat<(PPClo tglobaltlsaddr:$g, i32:$in), 3239 (ADDI $in, tglobaltlsaddr:$g)>; 3240def : Pat<(add i32:$in, (PPChi tglobaladdr:$g, 0)), 3241 (ADDIS $in, tglobaladdr:$g)>; 3242def : Pat<(add i32:$in, (PPChi tconstpool:$g, 0)), 3243 (ADDIS $in, tconstpool:$g)>; 3244def : Pat<(add i32:$in, (PPChi tjumptable:$g, 0)), 3245 (ADDIS $in, tjumptable:$g)>; 3246def : Pat<(add i32:$in, (PPChi tblockaddress:$g, 0)), 3247 (ADDIS $in, tblockaddress:$g)>; 3248 3249// Support for thread-local storage. 3250def PPC32GOT: PPCEmitTimePseudo<(outs gprc:$rD), (ins), "#PPC32GOT", 3251 [(set i32:$rD, (PPCppc32GOT))]>; 3252 3253// Get the _GLOBAL_OFFSET_TABLE_ in PIC mode. 3254// This uses two output registers, the first as the real output, the second as a 3255// temporary register, used internally in code generation. A "bl" also clobbers LR. 3256let Defs = [LR] in 3257def PPC32PICGOT: PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins), "#PPC32PICGOT", 3258 []>, NoEncode<"$rT">; 3259 3260def LDgotTprelL32: PPCEmitTimePseudo<(outs gprc_nor0:$rD), (ins s16imm:$disp, gprc_nor0:$reg), 3261 "#LDgotTprelL32", 3262 [(set i32:$rD, 3263 (PPCldGotTprelL tglobaltlsaddr:$disp, i32:$reg))]>; 3264def : Pat<(PPCaddTls i32:$in, tglobaltlsaddr:$g), 3265 (ADD4TLS $in, tglobaltlsaddr:$g)>; 3266 3267def ADDItlsgdL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3268 "#ADDItlsgdL32", 3269 [(set i32:$rD, 3270 (PPCaddiTlsgdL i32:$reg, tglobaltlsaddr:$disp))]>; 3271// LR is a true define, while the rest of the Defs are clobbers. R3 is 3272// explicitly defined when this op is created, so not mentioned here. 3273let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3274 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3275def GETtlsADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3276 "GETtlsADDR32", 3277 [(set i32:$rD, 3278 (PPCgetTlsAddr i32:$reg, tglobaltlsaddr:$sym))]>; 3279// R3 is explicitly defined when this op is created, so not mentioned here. 3280// The rest of the Defs are the exact set of registers that will be clobbered by 3281// the call. 3282let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3283 Defs = [R0,R4,R5,R11,LR,CR0] in { 3284def GETtlsADDR32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3285 "GETtlsADDR32AIX", 3286 [(set i32:$rD, 3287 (PPCgetTlsAddr i32:$offset, i32:$handle))]>; 3288def GETtlsMOD32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3289 "GETtlsMOD32AIX", 3290 [(set i32:$rD, 3291 (PPCgetTlsMod i32:$handle))]>; 3292} 3293 3294// For local-exec accesses on 32-bit AIX, a call to .__get_tpointer is 3295// generated to retrieve the thread pointer. GETtlsTpointer32AIX clobbers both 3296// R3 and the LR (link register). 3297let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3298 Defs = [R3,LR] in 3299def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins), 3300 "GETtlsTpointer32AIX", 3301 [(set i32:$rD, (PPCgetTpointer))]>; 3302 3303// The following pattern matches local- and initial-exec TLS accesses on 32-bit AIX. 3304// PPCaddTls is used in local- and initial-exec accesses in order to: 3305// - Get the address of a variable (add the variable offset to the thread 3306// pointer, retrieved by calling .__get_tpointer). 3307// - Create an opportunity to optimize the user of the loaded address. 3308def : Pat<(PPCaddTls i32:$in, i32:$addr), 3309 (ADD4TLS $in, $addr)>; 3310 3311// Combined op for ADDItlsgdL32 and GETtlsADDR32, late expanded. R3 and LR 3312// are true defines while the rest of the Defs are clobbers. 3313let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3314 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3315def ADDItlsgdLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3316 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3317 "#ADDItlsgdLADDR32", 3318 [(set i32:$rD, 3319 (PPCaddiTlsgdLAddr i32:$reg, 3320 tglobaltlsaddr:$disp, 3321 tglobaltlsaddr:$sym))]>; 3322def ADDItlsldL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3323 "#ADDItlsldL32", 3324 [(set i32:$rD, 3325 (PPCaddiTlsldL i32:$reg, tglobaltlsaddr:$disp))]>; 3326// This pseudo is expanded to two copies to put the variable offset in R4 and 3327// the region handle in R3 and GETtlsADDR32AIX. 3328def TLSGDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$offset, gprc:$handle), 3329 "#TLSGDAIX", 3330 [(set i32:$rD, 3331 (PPCTlsgdAIX i32:$offset, i32:$handle))]>; 3332// This pseudo is expanded to the call to GETtlsMOD32AIX. 3333def TLSLDAIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$handle), 3334 "#TLSLDAIX", [(set i32:$rD, (PPCTlsldAIX i32:$handle))]>; 3335// LR is a true define, while the rest of the Defs are clobbers. R3 is 3336// explicitly defined when this op is created, so not mentioned here. 3337let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3338 Defs = [R0,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3339def GETtlsldADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tlsgd32:$sym), 3340 "GETtlsldADDR32", 3341 [(set i32:$rD, 3342 (PPCgetTlsldAddr i32:$reg, 3343 tglobaltlsaddr:$sym))]>; 3344// Combined op for ADDItlsldL32 and GETtlsADDR32, late expanded. R3 and LR 3345// are true defines while the rest of the Defs are clobbers. 3346let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, 3347 Defs = [R0,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,LR,CTR,CR0,CR1,CR5,CR6,CR7] in 3348def ADDItlsldLADDR32 : PPCEmitTimePseudo<(outs gprc:$rD), 3349 (ins gprc_nor0:$reg, s16imm:$disp, tlsgd32:$sym), 3350 "#ADDItlsldLADDR32", 3351 [(set i32:$rD, 3352 (PPCaddiTlsldLAddr i32:$reg, 3353 tglobaltlsaddr:$disp, 3354 tglobaltlsaddr:$sym))]>; 3355def ADDIdtprelL32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3356 "#ADDIdtprelL32", 3357 [(set i32:$rD, 3358 (PPCaddiDtprelL i32:$reg, tglobaltlsaddr:$disp))]>; 3359def ADDISdtprelHA32 : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, s16imm:$disp), 3360 "#ADDISdtprelHA32", 3361 [(set i32:$rD, 3362 (PPCaddisDtprelHA i32:$reg, 3363 tglobaltlsaddr:$disp))]>; 3364 3365// Support for Position-independent code 3366def LWZtoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg), 3367 "#LWZtoc", 3368 [(set i32:$rD, 3369 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3370def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor0:$reg), 3371 "#LWZtocL", 3372 [(set i32:$rD, 3373 (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>; 3374def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3375 "#ADDIStocHA", []>; 3376// TOC Data Transform on AIX 3377def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp), 3378 "#ADDItoc", []>; 3379def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp), 3380 "#ADDItocL", []>; 3381 3382// Get Global (GOT) Base Register offset, from the word immediately preceding 3383// the function label. 3384def UpdateGBR : PPCEmitTimePseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>; 3385 3386// Pseudo-instruction marked for deletion. When deleting the instruction would 3387// cause iterator invalidation in MIR transformation passes, this pseudo can be 3388// used instead. It will be removed unconditionally at pre-emit time (prior to 3389// branch selection). 3390def UNENCODED_NOP: PPCEmitTimePseudo<(outs), (ins), "#UNENCODED_NOP", []>; 3391 3392// Standard shifts. These are represented separately from the real shifts above 3393// so that we can distinguish between shifts that allow 5-bit and 6-bit shift 3394// amounts. 3395def : Pat<(sra i32:$rS, i32:$rB), 3396 (SRAW $rS, $rB)>; 3397def : Pat<(srl i32:$rS, i32:$rB), 3398 (SRW $rS, $rB)>; 3399def : Pat<(shl i32:$rS, i32:$rB), 3400 (SLW $rS, $rB)>; 3401 3402def : Pat<(i32 (zextloadi1 DForm:$src)), 3403 (LBZ DForm:$src)>; 3404def : Pat<(i32 (zextloadi1 XForm:$src)), 3405 (LBZX XForm:$src)>; 3406def : Pat<(i32 (extloadi1 DForm:$src)), 3407 (LBZ DForm:$src)>; 3408def : Pat<(i32 (extloadi1 XForm:$src)), 3409 (LBZX XForm:$src)>; 3410def : Pat<(i32 (extloadi8 DForm:$src)), 3411 (LBZ DForm:$src)>; 3412def : Pat<(i32 (extloadi8 XForm:$src)), 3413 (LBZX XForm:$src)>; 3414def : Pat<(i32 (extloadi16 DForm:$src)), 3415 (LHZ DForm:$src)>; 3416def : Pat<(i32 (extloadi16 XForm:$src)), 3417 (LHZX XForm:$src)>; 3418let Predicates = [HasFPU] in { 3419def : Pat<(f64 (extloadf32 DForm:$src)), 3420 (COPY_TO_REGCLASS (LFS DForm:$src), F8RC)>; 3421def : Pat<(f64 (extloadf32 XForm:$src)), 3422 (COPY_TO_REGCLASS (LFSX XForm:$src), F8RC)>; 3423 3424def : Pat<(f64 (any_fpextend f32:$src)), 3425 (COPY_TO_REGCLASS $src, F8RC)>; 3426} 3427 3428// Only seq_cst fences require the heavyweight sync (SYNC 0). 3429// All others can use the lightweight sync (SYNC 1). 3430// source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html 3431// The rule for seq_cst is duplicated to work with both 64 bits and 32 bits 3432// versions of Power. 3433def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3434def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>; 3435def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>; 3436def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>; 3437 3438let Predicates = [HasFPU] in { 3439// Additional fnmsub patterns for custom node 3440def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C), 3441 (FNMSUB $A, $B, $C)>; 3442def : Pat<(PPCfnmsub f32:$A, f32:$B, f32:$C), 3443 (FNMSUBS $A, $B, $C)>; 3444def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)), 3445 (FMSUB $A, $B, $C)>; 3446def : Pat<(fneg (PPCfnmsub f32:$A, f32:$B, f32:$C)), 3447 (FMSUBS $A, $B, $C)>; 3448def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)), 3449 (FNMADD $A, $B, $C)>; 3450def : Pat<(PPCfnmsub f32:$A, f32:$B, (fneg f32:$C)), 3451 (FNMADDS $A, $B, $C)>; 3452 3453// FCOPYSIGN's operand types need not agree. 3454def : Pat<(fcopysign f64:$frB, f32:$frA), 3455 (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>; 3456def : Pat<(fcopysign f32:$frB, f64:$frA), 3457 (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>; 3458} 3459 3460// XL Compat intrinsics. 3461def : Pat<(int_ppc_fmsub f64:$A, f64:$B, f64:$C), (FMSUB $A, $B, $C)>; 3462def : Pat<(int_ppc_fmsubs f32:$A, f32:$B, f32:$C), (FMSUBS $A, $B, $C)>; 3463def : Pat<(int_ppc_fnmadd f64:$A, f64:$B, f64:$C), (FNMADD $A, $B, $C)>; 3464def : Pat<(int_ppc_fnmadds f32:$A, f32:$B, f32:$C), (FNMADDS $A, $B, $C)>; 3465def : Pat<(int_ppc_fre f64:$A), (FRE $A)>; 3466def : Pat<(int_ppc_fres f32:$A), (FRES $A)>; 3467def : Pat<(int_ppc_fnabs f64:$A), (FNABSD $A)>; 3468def : Pat<(int_ppc_fnabss f32:$A), (FNABSS $A)>; 3469 3470include "PPCInstrAltivec.td" 3471include "PPCInstrSPE.td" 3472include "PPCInstr64Bit.td" 3473include "PPCInstrVSX.td" 3474include "PPCInstrHTM.td" 3475 3476def crnot : OutPatFrag<(ops node:$in), 3477 (CRNOT $in)>; 3478def : Pat<(not i1:$in), 3479 (crnot $in)>; 3480 3481// Pseudo-instructions for alternate assembly syntax (never used by codegen). 3482// These are aliases that require C++ handling to convert to the target 3483// instruction, while InstAliases can be handled directly by tblgen. 3484class PPCAsmPseudo<string asm, dag iops> 3485 : Instruction { 3486 let Namespace = "PPC"; 3487 bit PPC64 = 0; // Default value, override with isPPC64 3488 3489 let OutOperandList = (outs); 3490 let InOperandList = iops; 3491 let Pattern = []; 3492 let AsmString = asm; 3493 let isAsmParserOnly = 1; 3494 let isPseudo = 1; 3495 let hasNoSchedulingInfo = 1; 3496 3497 // Indicate that this instruction takes a register+immediate memory operand. 3498 bits<1> MemriOp = 0; 3499 let TSFlags{10} = MemriOp; 3500} 3501 3502// Mask immediates for MMA instructions (2, 4 and 8 bits). 3503def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>; 3504def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>; 3505def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>; 3506 3507def MMA : Predicate<"Subtarget->hasMMA()">; 3508 3509// Prefixed instructions may require access to the above defs at a later 3510// time so we include this after the def. 3511include "PPCInstrP10.td" 3512include "PPCInstrFutureMMA.td" 3513include "PPCInstrFuture.td" 3514include "PPCInstrMMA.td" 3515include "PPCInstrDFP.td" 3516 3517// Patterns for arithmetic i1 operations. 3518def : Pat<(add i1:$a, i1:$b), 3519 (CRXOR $a, $b)>; 3520def : Pat<(sub i1:$a, i1:$b), 3521 (CRXOR $a, $b)>; 3522def : Pat<(mul i1:$a, i1:$b), 3523 (CRAND $a, $b)>; 3524 3525// We're sometimes asked to materialize i1 -1, which is just 1 in this case 3526// (-1 is used to mean all bits set). 3527def : Pat<(i1 -1), (CRSET)>; 3528 3529// i1 extensions, implemented in terms of isel. 3530def : Pat<(i32 (zext i1:$in)), 3531 (SELECT_I4 $in, (LI 1), (LI 0))>; 3532def : Pat<(i32 (sext i1:$in)), 3533 (SELECT_I4 $in, (LI -1), (LI 0))>; 3534 3535def : Pat<(i64 (zext i1:$in)), 3536 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3537def : Pat<(i64 (sext i1:$in)), 3538 (SELECT_I8 $in, (LI8 -1), (LI8 0))>; 3539 3540// FIXME: We should choose either a zext or a sext based on other constants 3541// already around. 3542def : Pat<(i32 (anyext i1:$in)), 3543 (SELECT_I4 $in, (LI 1), (LI 0))>; 3544def : Pat<(i64 (anyext i1:$in)), 3545 (SELECT_I8 $in, (LI8 1), (LI8 0))>; 3546 3547// match setcc on i1 variables. 3548// CRANDC is: 3549// 1 1 : F 3550// 1 0 : T 3551// 0 1 : F 3552// 0 0 : F 3553// 3554// LT is: 3555// -1 -1 : F 3556// -1 0 : T 3557// 0 -1 : F 3558// 0 0 : F 3559// 3560// ULT is: 3561// 1 1 : F 3562// 1 0 : F 3563// 0 1 : T 3564// 0 0 : F 3565def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLT)), 3566 (CRANDC $s1, $s2)>; 3567def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)), 3568 (CRANDC $s2, $s1)>; 3569// CRORC is: 3570// 1 1 : T 3571// 1 0 : T 3572// 0 1 : F 3573// 0 0 : T 3574// 3575// LE is: 3576// -1 -1 : T 3577// -1 0 : T 3578// 0 -1 : F 3579// 0 0 : T 3580// 3581// ULE is: 3582// 1 1 : T 3583// 1 0 : F 3584// 0 1 : T 3585// 0 0 : T 3586def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETLE)), 3587 (CRORC $s1, $s2)>; 3588def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)), 3589 (CRORC $s2, $s1)>; 3590 3591def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETEQ)), 3592 (CREQV $s1, $s2)>; 3593 3594// GE is: 3595// -1 -1 : T 3596// -1 0 : F 3597// 0 -1 : T 3598// 0 0 : T 3599// 3600// UGE is: 3601// 1 1 : T 3602// 1 0 : T 3603// 0 1 : F 3604// 0 0 : T 3605def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGE)), 3606 (CRORC $s2, $s1)>; 3607def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)), 3608 (CRORC $s1, $s2)>; 3609 3610// GT is: 3611// -1 -1 : F 3612// -1 0 : F 3613// 0 -1 : T 3614// 0 0 : F 3615// 3616// UGT is: 3617// 1 1 : F 3618// 1 0 : T 3619// 0 1 : F 3620// 0 0 : F 3621def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)), 3622 (CRANDC $s2, $s1)>; 3623def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)), 3624 (CRANDC $s1, $s2)>; 3625 3626def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)), 3627 (CRXOR $s1, $s2)>; 3628 3629// match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE, 3630// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for 3631// floating-point types. 3632 3633multiclass CRNotPat<dag pattern, dag result> { 3634 def : Pat<pattern, (crnot result)>; 3635 def : Pat<(not pattern), result>; 3636 3637 // We can also fold the crnot into an extension: 3638 def : Pat<(i32 (zext pattern)), 3639 (SELECT_I4 result, (LI 0), (LI 1))>; 3640 def : Pat<(i32 (sext pattern)), 3641 (SELECT_I4 result, (LI 0), (LI -1))>; 3642 3643 // We can also fold the crnot into an extension: 3644 def : Pat<(i64 (zext pattern)), 3645 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3646 def : Pat<(i64 (sext pattern)), 3647 (SELECT_I8 result, (LI8 0), (LI8 -1))>; 3648 3649 // FIXME: We should choose either a zext or a sext based on other constants 3650 // already around. 3651 def : Pat<(i32 (anyext pattern)), 3652 (SELECT_I4 result, (LI 0), (LI 1))>; 3653 3654 def : Pat<(i64 (anyext pattern)), 3655 (SELECT_I8 result, (LI8 0), (LI8 1))>; 3656} 3657 3658// FIXME: Because of what seems like a bug in TableGen's type-inference code, 3659// we need to write imm:$imm in the output patterns below, not just $imm, or 3660// else the resulting matcher will not correctly add the immediate operand 3661// (making it a register operand instead). 3662 3663// extended SETCC. 3664multiclass ExtSetCCPat<CondCode cc, PatFrag pfrag, 3665 OutPatFrag rfrag, OutPatFrag rfrag8> { 3666 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, cc)))), 3667 (rfrag $s1)>; 3668 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, cc)))), 3669 (rfrag8 $s1)>; 3670 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, cc)))), 3671 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3672 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, cc)))), 3673 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3674 3675 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, cc)))), 3676 (rfrag $s1)>; 3677 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, cc)))), 3678 (rfrag8 $s1)>; 3679 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, cc)))), 3680 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1), sub_32)>; 3681 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, cc)))), 3682 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>; 3683} 3684 3685// Note that we do all inversions below with i(32|64)not, instead of using 3686// (xori x, 1) because on the A2 nor has single-cycle latency while xori 3687// has 2-cycle latency. 3688 3689defm : ExtSetCCPat<SETEQ, 3690 PatFrag<(ops node:$in, node:$cc), 3691 (setcc $in, 0, $cc)>, 3692 OutPatFrag<(ops node:$in), 3693 (RLWINM (CNTLZW $in), 27, 31, 31)>, 3694 OutPatFrag<(ops node:$in), 3695 (RLDICL (CNTLZD $in), 58, 63)> >; 3696 3697defm : ExtSetCCPat<SETNE, 3698 PatFrag<(ops node:$in, node:$cc), 3699 (setcc $in, 0, $cc)>, 3700 OutPatFrag<(ops node:$in), 3701 (RLWINM (i32not (CNTLZW $in)), 27, 31, 31)>, 3702 OutPatFrag<(ops node:$in), 3703 (RLDICL (i64not (CNTLZD $in)), 58, 63)> >; 3704 3705defm : ExtSetCCPat<SETLT, 3706 PatFrag<(ops node:$in, node:$cc), 3707 (setcc $in, 0, $cc)>, 3708 OutPatFrag<(ops node:$in), 3709 (RLWINM $in, 1, 31, 31)>, 3710 OutPatFrag<(ops node:$in), 3711 (RLDICL $in, 1, 63)> >; 3712 3713defm : ExtSetCCPat<SETGE, 3714 PatFrag<(ops node:$in, node:$cc), 3715 (setcc $in, 0, $cc)>, 3716 OutPatFrag<(ops node:$in), 3717 (RLWINM (i32not $in), 1, 31, 31)>, 3718 OutPatFrag<(ops node:$in), 3719 (RLDICL (i64not $in), 1, 63)> >; 3720 3721defm : ExtSetCCPat<SETGT, 3722 PatFrag<(ops node:$in, node:$cc), 3723 (setcc $in, 0, $cc)>, 3724 OutPatFrag<(ops node:$in), 3725 (RLWINM (ANDC (NEG $in), $in), 1, 31, 31)>, 3726 OutPatFrag<(ops node:$in), 3727 (RLDICL (ANDC8 (NEG8 $in), $in), 1, 63)> >; 3728 3729defm : ExtSetCCPat<SETLE, 3730 PatFrag<(ops node:$in, node:$cc), 3731 (setcc $in, 0, $cc)>, 3732 OutPatFrag<(ops node:$in), 3733 (RLWINM (ORC $in, (NEG $in)), 1, 31, 31)>, 3734 OutPatFrag<(ops node:$in), 3735 (RLDICL (ORC8 $in, (NEG8 $in)), 1, 63)> >; 3736 3737defm : ExtSetCCPat<SETLT, 3738 PatFrag<(ops node:$in, node:$cc), 3739 (setcc $in, -1, $cc)>, 3740 OutPatFrag<(ops node:$in), 3741 (RLWINM (AND $in, (ADDI $in, 1)), 1, 31, 31)>, 3742 OutPatFrag<(ops node:$in), 3743 (RLDICL (AND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3744 3745defm : ExtSetCCPat<SETGE, 3746 PatFrag<(ops node:$in, node:$cc), 3747 (setcc $in, -1, $cc)>, 3748 OutPatFrag<(ops node:$in), 3749 (RLWINM (NAND $in, (ADDI $in, 1)), 1, 31, 31)>, 3750 OutPatFrag<(ops node:$in), 3751 (RLDICL (NAND8 $in, (ADDI8 $in, 1)), 1, 63)> >; 3752 3753defm : ExtSetCCPat<SETGT, 3754 PatFrag<(ops node:$in, node:$cc), 3755 (setcc $in, -1, $cc)>, 3756 OutPatFrag<(ops node:$in), 3757 (RLWINM (i32not $in), 1, 31, 31)>, 3758 OutPatFrag<(ops node:$in), 3759 (RLDICL (i64not $in), 1, 63)> >; 3760 3761defm : ExtSetCCPat<SETLE, 3762 PatFrag<(ops node:$in, node:$cc), 3763 (setcc $in, -1, $cc)>, 3764 OutPatFrag<(ops node:$in), 3765 (RLWINM $in, 1, 31, 31)>, 3766 OutPatFrag<(ops node:$in), 3767 (RLDICL $in, 1, 63)> >; 3768 3769// An extended SETCC with shift amount. 3770multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, 3771 OutPatFrag rfrag, OutPatFrag rfrag8> { 3772 def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3773 (rfrag $s1, $sa)>; 3774 def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3775 (rfrag8 $s1, $sa)>; 3776 def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3777 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3778 def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3779 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3780 3781 def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3782 (rfrag $s1, $sa)>; 3783 def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3784 (rfrag8 $s1, $sa)>; 3785 def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), 3786 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; 3787 def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), 3788 (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; 3789} 3790 3791defm : ExtSetCCShiftPat<SETNE, 3792 PatFrag<(ops node:$in, node:$sa, node:$cc), 3793 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3794 OutPatFrag<(ops node:$in, node:$sa), 3795 (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, 3796 OutPatFrag<(ops node:$in, node:$sa), 3797 (RLDCL $in, (SUBFIC $sa, 64), 63)> >; 3798 3799defm : ExtSetCCShiftPat<SETEQ, 3800 PatFrag<(ops node:$in, node:$sa, node:$cc), 3801 (setcc (and $in, (shl 1, $sa)), 0, $cc)>, 3802 OutPatFrag<(ops node:$in, node:$sa), 3803 (RLWNM (i32not $in), 3804 (SUBFIC $sa, 32), 31, 31)>, 3805 OutPatFrag<(ops node:$in, node:$sa), 3806 (RLDCL (i64not $in), 3807 (SUBFIC $sa, 64), 63)> >; 3808 3809// SETCC for i32. 3810def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), 3811 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3812def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLT)), 3813 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3814def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)), 3815 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3816def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGT)), 3817 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3818def : Pat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETEQ)), 3819 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3820def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETEQ)), 3821 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3822 3823// For non-equality comparisons, the default code would materialize the 3824// constant, then compare against it, like this: 3825// lis r2, 4660 3826// ori r2, r2, 22136 3827// cmpw cr0, r3, r2 3828// beq cr0,L6 3829// Since we are just comparing for equality, we can emit this instead: 3830// xoris r0,r3,0x1234 3831// cmplwi cr0,r0,0x5678 3832// beq cr0,L6 3833 3834def : Pat<(i1 (setcc i32:$s1, imm:$imm, SETEQ)), 3835 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3836 (LO16 imm:$imm)), sub_eq)>; 3837 3838def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)), 3839 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3840def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETLT)), 3841 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3842def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)), 3843 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3844def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETGT)), 3845 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3846def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETEQ)), 3847 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3848 3849// SETCC for i64. 3850def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)), 3851 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3852def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLT)), 3853 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3854def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)), 3855 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3856def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGT)), 3857 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3858def : Pat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETEQ)), 3859 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3860def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETEQ)), 3861 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3862 3863// For non-equality comparisons, the default code would materialize the 3864// constant, then compare against it, like this: 3865// lis r2, 4660 3866// ori r2, r2, 22136 3867// cmpd cr0, r3, r2 3868// beq cr0,L6 3869// Since we are just comparing for equality, we can emit this instead: 3870// xoris r0,r3,0x1234 3871// cmpldi cr0,r0,0x5678 3872// beq cr0,L6 3873 3874def : Pat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETEQ)), 3875 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3876 (LO16 imm:$imm)), sub_eq)>; 3877 3878def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)), 3879 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3880def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETLT)), 3881 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3882def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)), 3883 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3884def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETGT)), 3885 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3886def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETEQ)), 3887 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3888 3889let Predicates = [IsNotISA3_1] in { 3890// Instantiations of CRNotPat for i32. 3891defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)), 3892 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; 3893defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETGE)), 3894 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>; 3895defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)), 3896 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>; 3897defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETLE)), 3898 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>; 3899defm : CRNotPat<(i1 (setcc i32:$s1, imm32SExt16:$imm, SETNE)), 3900 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>; 3901defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETNE)), 3902 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>; 3903 3904defm : CRNotPat<(i1 (setcc i32:$s1, imm:$imm, SETNE)), 3905 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)), 3906 (LO16 imm:$imm)), sub_eq)>; 3907 3908defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)), 3909 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_lt)>; 3910defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETGE)), 3911 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_lt)>; 3912defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)), 3913 (EXTRACT_SUBREG (CMPLW $s1, $s2), sub_gt)>; 3914defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETLE)), 3915 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_gt)>; 3916defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETNE)), 3917 (EXTRACT_SUBREG (CMPW $s1, $s2), sub_eq)>; 3918 3919// Instantiations of CRNotPat for i64. 3920defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)), 3921 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_lt)>; 3922defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETGE)), 3923 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_lt)>; 3924defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)), 3925 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_gt)>; 3926defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETLE)), 3927 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_gt)>; 3928defm : CRNotPat<(i1 (setcc i64:$s1, imm64SExt16:$imm, SETNE)), 3929 (EXTRACT_SUBREG (CMPDI $s1, imm:$imm), sub_eq)>; 3930defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETNE)), 3931 (EXTRACT_SUBREG (CMPLDI $s1, imm:$imm), sub_eq)>; 3932 3933defm : CRNotPat<(i1 (setcc i64:$s1, imm64ZExt32:$imm, SETNE)), 3934 (EXTRACT_SUBREG (CMPLDI (XORIS8 $s1, (HI16 imm:$imm)), 3935 (LO16 imm:$imm)), sub_eq)>; 3936 3937defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)), 3938 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_lt)>; 3939defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETGE)), 3940 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_lt)>; 3941defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)), 3942 (EXTRACT_SUBREG (CMPLD $s1, $s2), sub_gt)>; 3943defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETLE)), 3944 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_gt)>; 3945defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETNE)), 3946 (EXTRACT_SUBREG (CMPD $s1, $s2), sub_eq)>; 3947} 3948 3949multiclass FSetCCPat<SDPatternOperator SetCC, ValueType Ty, I FCmp> { 3950 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)), 3951 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3952 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGE)), 3953 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3954 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)), 3955 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3956 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLE)), 3957 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3958 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUNE)), 3959 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3960 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETNE)), 3961 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3962 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETO)), 3963 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3964 3965 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOLT)), 3966 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3967 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETLT)), 3968 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_lt)>; 3969 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3970 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3971 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETGT)), 3972 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_gt)>; 3973 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOEQ)), 3974 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3975 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETEQ)), 3976 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_eq)>; 3977 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUO)), 3978 (EXTRACT_SUBREG (FCmp $s1, $s2), sub_un)>; 3979} 3980 3981let Predicates = [HasFPU] in { 3982// FCMPU: If either of the operands is a Signaling NaN, then VXSNAN is set. 3983// SETCC for f32. 3984defm : FSetCCPat<any_fsetcc, f32, FCMPUS>; 3985 3986// SETCC for f64. 3987defm : FSetCCPat<any_fsetcc, f64, FCMPUD>; 3988 3989// SETCC for f128. 3990defm : FSetCCPat<any_fsetcc, f128, XSCMPUQP>; 3991 3992// FCMPO: If either of the operands is a Signaling NaN, then VXSNAN is set and, 3993// if neither operand is a Signaling NaN but at least one operand is a Quiet NaN, 3994// then VXVC is set. 3995// SETCCS for f32. 3996defm : FSetCCPat<strict_fsetccs, f32, FCMPOS>; 3997 3998// SETCCS for f64. 3999defm : FSetCCPat<strict_fsetccs, f64, FCMPOD>; 4000 4001// SETCCS for f128. 4002defm : FSetCCPat<strict_fsetccs, f128, XSCMPOQP>; 4003} 4004 4005// This must be in this file because it relies on patterns defined in this file 4006// after the inclusion of the instruction sets. 4007let Predicates = [HasSPE] in { 4008// SETCC for f32. 4009def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOLT)), 4010 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4011def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLT)), 4012 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4013def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 4014 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4015def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGT)), 4016 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4017def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOEQ)), 4018 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4019def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETEQ)), 4020 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4021 4022defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)), 4023 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4024defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETGE)), 4025 (EXTRACT_SUBREG (EFSCMPLT $s1, $s2), sub_gt)>; 4026defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)), 4027 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4028defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETLE)), 4029 (EXTRACT_SUBREG (EFSCMPGT $s1, $s2), sub_gt)>; 4030defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUNE)), 4031 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4032defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETNE)), 4033 (EXTRACT_SUBREG (EFSCMPEQ $s1, $s2), sub_gt)>; 4034 4035// SETCC for f64. 4036def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOLT)), 4037 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4038def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLT)), 4039 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4040def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)), 4041 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4042def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGT)), 4043 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4044def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOEQ)), 4045 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4046def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETEQ)), 4047 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4048 4049defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)), 4050 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4051defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETGE)), 4052 (EXTRACT_SUBREG (EFDCMPLT $s1, $s2), sub_gt)>; 4053defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)), 4054 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4055defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETLE)), 4056 (EXTRACT_SUBREG (EFDCMPGT $s1, $s2), sub_gt)>; 4057defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUNE)), 4058 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4059defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETNE)), 4060 (EXTRACT_SUBREG (EFDCMPEQ $s1, $s2), sub_gt)>; 4061} 4062// match select on i1 variables: 4063def : Pat<(i1 (select i1:$cond, i1:$tval, i1:$fval)), 4064 (CROR (CRAND $cond , $tval), 4065 (CRAND (crnot $cond), $fval))>; 4066 4067// match selectcc on i1 variables: 4068// select (lhs == rhs), tval, fval is: 4069// ((lhs == rhs) & tval) | (!(lhs == rhs) & fval) 4070def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), 4071 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4072 (CRAND (CRORC $rhs, $lhs), $fval))>; 4073def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)), 4074 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4075 (CRAND (CRORC $lhs, $rhs), $fval))>; 4076def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLE)), 4077 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4078 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4079def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)), 4080 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4081 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4082def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETEQ)), 4083 (CROR (CRAND (CREQV $lhs, $rhs), $tval), 4084 (CRAND (CRXOR $lhs, $rhs), $fval))>; 4085def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGE)), 4086 (CROR (CRAND (CRORC $rhs, $lhs), $tval), 4087 (CRAND (CRANDC $lhs, $rhs), $fval))>; 4088def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)), 4089 (CROR (CRAND (CRORC $lhs, $rhs), $tval), 4090 (CRAND (CRANDC $rhs, $lhs), $fval))>; 4091def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETGT)), 4092 (CROR (CRAND (CRANDC $rhs, $lhs), $tval), 4093 (CRAND (CRORC $lhs, $rhs), $fval))>; 4094def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)), 4095 (CROR (CRAND (CRANDC $lhs, $rhs), $tval), 4096 (CRAND (CRORC $rhs, $lhs), $fval))>; 4097def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETNE)), 4098 (CROR (CRAND (CREQV $lhs, $rhs), $fval), 4099 (CRAND (CRXOR $lhs, $rhs), $tval))>; 4100 4101// match selectcc on i1 variables with non-i1 output. 4102def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLT)), 4103 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4104def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)), 4105 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4106def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETLE)), 4107 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4108def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)), 4109 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4110def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETEQ)), 4111 (SELECT_I4 (CREQV $lhs, $rhs), $tval, $fval)>; 4112def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGE)), 4113 (SELECT_I4 (CRORC $rhs, $lhs), $tval, $fval)>; 4114def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)), 4115 (SELECT_I4 (CRORC $lhs, $rhs), $tval, $fval)>; 4116def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETGT)), 4117 (SELECT_I4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4118def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)), 4119 (SELECT_I4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4120def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETNE)), 4121 (SELECT_I4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4122 4123def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLT)), 4124 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4125def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)), 4126 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4127def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETLE)), 4128 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4129def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULE)), 4130 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4131def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETEQ)), 4132 (SELECT_I8 (CREQV $lhs, $rhs), $tval, $fval)>; 4133def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGE)), 4134 (SELECT_I8 (CRORC $rhs, $lhs), $tval, $fval)>; 4135def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGE)), 4136 (SELECT_I8 (CRORC $lhs, $rhs), $tval, $fval)>; 4137def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETGT)), 4138 (SELECT_I8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4139def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)), 4140 (SELECT_I8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4141def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETNE)), 4142 (SELECT_I8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4143 4144let Predicates = [HasFPU] in { 4145def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLT)), 4146 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4147def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)), 4148 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4149def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETLE)), 4150 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4151def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)), 4152 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4153def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETEQ)), 4154 (SELECT_F4 (CREQV $lhs, $rhs), $tval, $fval)>; 4155def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGE)), 4156 (SELECT_F4 (CRORC $rhs, $lhs), $tval, $fval)>; 4157def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)), 4158 (SELECT_F4 (CRORC $lhs, $rhs), $tval, $fval)>; 4159def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETGT)), 4160 (SELECT_F4 (CRANDC $rhs, $lhs), $tval, $fval)>; 4161def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)), 4162 (SELECT_F4 (CRANDC $lhs, $rhs), $tval, $fval)>; 4163def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETNE)), 4164 (SELECT_F4 (CRXOR $lhs, $rhs), $tval, $fval)>; 4165 4166def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLT)), 4167 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4168def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)), 4169 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4170def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETLE)), 4171 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4172def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)), 4173 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4174def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETEQ)), 4175 (SELECT_F8 (CREQV $lhs, $rhs), $tval, $fval)>; 4176def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGE)), 4177 (SELECT_F8 (CRORC $rhs, $lhs), $tval, $fval)>; 4178def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)), 4179 (SELECT_F8 (CRORC $lhs, $rhs), $tval, $fval)>; 4180def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETGT)), 4181 (SELECT_F8 (CRANDC $rhs, $lhs), $tval, $fval)>; 4182def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)), 4183 (SELECT_F8 (CRANDC $lhs, $rhs), $tval, $fval)>; 4184def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETNE)), 4185 (SELECT_F8 (CRXOR $lhs, $rhs), $tval, $fval)>; 4186} 4187 4188def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLT)), 4189 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4190def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULT)), 4191 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4192def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETLE)), 4193 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4194def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETULE)), 4195 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4196def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETEQ)), 4197 (SELECT_F16 (CREQV $lhs, $rhs), $tval, $fval)>; 4198def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGE)), 4199 (SELECT_F16 (CRORC $rhs, $lhs), $tval, $fval)>; 4200def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGE)), 4201 (SELECT_F16 (CRORC $lhs, $rhs), $tval, $fval)>; 4202def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETGT)), 4203 (SELECT_F16 (CRANDC $rhs, $lhs), $tval, $fval)>; 4204def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETUGT)), 4205 (SELECT_F16 (CRANDC $lhs, $rhs), $tval, $fval)>; 4206def : Pat<(f128 (selectcc i1:$lhs, i1:$rhs, f128:$tval, f128:$fval, SETNE)), 4207 (SELECT_F16 (CRXOR $lhs, $rhs), $tval, $fval)>; 4208 4209def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLT)), 4210 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4211def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULT)), 4212 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4213def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETLE)), 4214 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4215def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETULE)), 4216 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4217def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETEQ)), 4218 (SELECT_VRRC (CREQV $lhs, $rhs), $tval, $fval)>; 4219def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGE)), 4220 (SELECT_VRRC (CRORC $rhs, $lhs), $tval, $fval)>; 4221def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGE)), 4222 (SELECT_VRRC (CRORC $lhs, $rhs), $tval, $fval)>; 4223def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETGT)), 4224 (SELECT_VRRC (CRANDC $rhs, $lhs), $tval, $fval)>; 4225def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETUGT)), 4226 (SELECT_VRRC (CRANDC $lhs, $rhs), $tval, $fval)>; 4227def : Pat<(v4i32 (selectcc i1:$lhs, i1:$rhs, v4i32:$tval, v4i32:$fval, SETNE)), 4228 (SELECT_VRRC (CRXOR $lhs, $rhs), $tval, $fval)>; 4229 4230let Defs = [CR0] in { 4231def ANDI_rec_1_EQ_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4232 "#ANDI_rec_1_EQ_BIT", 4233 [(set i1:$dst, (trunc (not i32:$in)))]>; 4234def ANDI_rec_1_GT_BIT : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins gprc:$in), 4235 "#ANDI_rec_1_GT_BIT", 4236 [(set i1:$dst, (trunc i32:$in))]>; 4237 4238def ANDI_rec_1_EQ_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4239 "#ANDI_rec_1_EQ_BIT8", 4240 [(set i1:$dst, (trunc (not i64:$in)))]>; 4241def ANDI_rec_1_GT_BIT8 : PPCCustomInserterPseudo<(outs crbitrc:$dst), (ins g8rc:$in), 4242 "#ANDI_rec_1_GT_BIT8", 4243 [(set i1:$dst, (trunc i64:$in))]>; 4244} 4245 4246def : Pat<(i1 (not (trunc i32:$in))), 4247 (ANDI_rec_1_EQ_BIT $in)>; 4248def : Pat<(i1 (not (trunc i64:$in))), 4249 (ANDI_rec_1_EQ_BIT8 $in)>; 4250 4251def : Pat<(int_ppc_fsel f8rc:$FRA, f8rc:$FRC, f8rc:$FRB), (FSELD $FRA, $FRC, $FRB)>; 4252def : Pat<(int_ppc_frsqrte f8rc:$frB), (FRSQRTE $frB)>; 4253def : Pat<(int_ppc_frsqrtes f4rc:$frB), (FRSQRTES $frB)>; 4254 4255//===----------------------------------------------------------------------===// 4256// PowerPC Instructions used for assembler/disassembler only 4257// 4258 4259// FIXME: For B=0 or B > 8, the registers following RT are used. 4260// WARNING: Do not add patterns for this instruction without fixing this. 4261def LSWI : XForm_base_r3xo_memOp<31, 597, (outs gprc:$RST), 4262 (ins gprc:$RA, u5imm:$RB), 4263 "lswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4264 4265// FIXME: For B=0 or B > 8, the registers following RT are used. 4266// WARNING: Do not add patterns for this instruction without fixing this. 4267def STSWI : XForm_base_r3xo_memOp<31, 725, (outs), 4268 (ins gprc:$RST, gprc:$RA, u5imm:$RB), 4269 "stswi $RST, $RA, $RB", IIC_LdStLoad, []>; 4270 4271def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins), 4272 "isync", IIC_SprISYNC, []>; 4273 4274def ICBI : XForm_1a<31, 982, (outs), (ins (memrr $RA, $RB):$addr), 4275 "icbi $addr", IIC_LdStICBI, []>; 4276 4277def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L), 4278 "wait $L", IIC_LdStLoad, []>; 4279 4280def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO), 4281 "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>; 4282 4283def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR), 4284 "mtsr $SR, $RS", IIC_SprMTSR>; 4285 4286def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR), 4287 "mfsr $RS, $SR", IIC_SprMFSR>; 4288 4289def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB), 4290 "mtsrin $RS, $RB", IIC_SprMTSR>; 4291 4292def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB), 4293 "mfsrin $RS, $RB", IIC_SprMFSR>; 4294 4295def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L), 4296 "mtmsr $RS, $L", IIC_SprMTMSR>; 4297 4298def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS), 4299 "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> { 4300 let L = 0; 4301} 4302 4303def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>, 4304 Requires<[IsBookE]> { 4305 bits<1> E; 4306 4307 let Inst{16} = E; 4308 let Inst{21-30} = 163; 4309} 4310 4311def DCCCI : XForm_tlb<454, (outs), (ins gprc:$RA, gprc:$RB), 4312 "dccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4313def ICCCI : XForm_tlb<966, (outs), (ins gprc:$RA, gprc:$RB), 4314 "iccci $RA, $RB", IIC_LdStLoad>, Requires<[IsPPC4xx]>; 4315 4316def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4317def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>; 4318def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4319def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>; 4320 4321def MFMSR : XForm_rs<31, 83, (outs gprc:$RST), (ins), 4322 "mfmsr $RST", IIC_SprMFMSR, []>; 4323 4324def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L), 4325 "mtmsrd $RS, $L", IIC_SprMTMSRD>; 4326 4327def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA), 4328 "mcrfs $BF, $BFA", IIC_BrMCR>; 4329 4330// All MTFSF variants may change the rounding mode so conservatively set it 4331// as an implicit def for all of them. 4332let Predicates = [HasFPU] in { 4333let Defs = [RM], hasSideEffects = 1 in { 4334let isCodeGenOnly = 1, 4335 Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in 4336def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U), 4337 "mtfsfi $BF, $U", IIC_IntMFFS>; 4338def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W), 4339 "mtfsfi $BF, $U, $W", IIC_IntMFFS>; 4340let Defs = [CR1] in 4341def MTFSFI_rec : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, u1imm:$W), 4342 "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm; 4343 4344def MTFSF : XFLForm_1<63, 711, (outs), 4345 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4346 "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>; 4347let Defs = [CR1] in 4348def MTFSF_rec : XFLForm_1<63, 711, (outs), 4349 (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W), 4350 "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm; 4351} 4352 4353def : InstAlias<"mtfsfi $BF, $U", (MTFSFI u3imm:$BF, u4imm:$U, 0)>; 4354def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec u3imm:$BF, u4imm:$U, 0)>; 4355def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4356def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>; 4357} 4358 4359def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB), 4360 "slbie $RB", IIC_SprSLBIE, []>; 4361 4362def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RST, gprc:$RB), 4363 "slbmte $RST, $RB", IIC_SprSLBMTE, []>; 4364 4365def SLBMFEE : XForm_26<31, 915, (outs gprc:$RST), (ins gprc:$RB), 4366 "slbmfee $RST, $RB", IIC_SprSLBMFEE, []>; 4367 4368def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), 4369 "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; 4370 4371def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; 4372 4373let Defs = [CR0] in 4374def SLBFEE_rec : XForm_26<31, 979, (outs gprc:$RST), (ins gprc:$RB), 4375 "slbfee. $RST, $RB", IIC_SprSLBFEE, []>, isRecordForm; 4376 4377def TLBIA : XForm_0<31, 370, (outs), (ins), 4378 "tlbia", IIC_SprTLBIA, []>; 4379 4380def TLBSYNC : XForm_0<31, 566, (outs), (ins), 4381 "tlbsync", IIC_SprTLBSYNC, []>; 4382 4383def TLBIEL : XForm_16b<31, 274, (outs), (ins gprc:$RB), 4384 "tlbiel $RB", IIC_SprTLBIEL, []>; 4385 4386def TLBLD : XForm_16b<31, 978, (outs), (ins gprc:$RB), 4387 "tlbld $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4388def TLBLI : XForm_16b<31, 1010, (outs), (ins gprc:$RB), 4389 "tlbli $RB", IIC_LdStLoad, []>, Requires<[IsPPC6xx]>; 4390 4391def TLBIE : XForm_26<31, 306, (outs), (ins gprc:$RST, gprc:$RB), 4392 "tlbie $RB,$RST", IIC_SprTLBIE, []>; 4393 4394def TLBSX : XForm_tlb<914, (outs), (ins gprc:$RA, gprc:$RB), "tlbsx $RA, $RB", 4395 IIC_LdStLoad>, Requires<[IsBookE]>; 4396 4397def TLBIVAX : XForm_tlb<786, (outs), (ins gprc:$RA, gprc:$RB), "tlbivax $RA, $RB", 4398 IIC_LdStLoad>, Requires<[IsBookE]>; 4399 4400def TLBILX : XForm_tlbilx<18, (outs), (ins u2imm:$T, gprc:$RA, gprc:$RB), 4401 "tlbilx $T, $RA, $RB", IIC_LdStLoad>, Requires<[IsBookE]>; 4402 4403def TLBRE : XForm_24_eieio<31, 946, (outs), (ins), 4404 "tlbre", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4405 4406def TLBWE : XForm_24_eieio<31, 978, (outs), (ins), 4407 "tlbwe", IIC_LdStLoad, []>, Requires<[IsBookE]>; 4408 4409def TLBRE2 : XForm_tlbws<31, 946, (outs gprc:$RST), (ins gprc:$RA, i1imm:$WS), 4410 "tlbre $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4411 4412def TLBWE2 : XForm_tlbws<31, 978, (outs), (ins gprc:$RST, gprc:$RA, i1imm:$WS), 4413 "tlbwe $RST, $RA, $WS", IIC_LdStLoad, []>, Requires<[IsPPC4xx]>; 4414 4415def TLBSX2 : XForm_base_r3xo<31, 914, (outs), (ins gprc:$RST, gprc:$RA, gprc:$RB), 4416 "tlbsx $RST, $RA, $RB", IIC_LdStLoad, []>, 4417 Requires<[IsPPC4xx]>; 4418def TLBSX2D : XForm_base_r3xo<31, 914, (outs), 4419 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4420 "tlbsx. $RST, $RA, $RB", IIC_LdStLoad, []>, 4421 Requires<[IsPPC4xx]>, isRecordForm; 4422 4423def RFID : XForm_0<19, 18, (outs), (ins), "rfid", IIC_IntRFID, []>; 4424 4425def RFI : XForm_0<19, 50, (outs), (ins), "rfi", IIC_SprRFI, []>, 4426 Requires<[IsBookE]>; 4427def RFCI : XForm_0<19, 51, (outs), (ins), "rfci", IIC_BrB, []>, 4428 Requires<[IsBookE]>; 4429 4430def RFDI : XForm_0<19, 39, (outs), (ins), "rfdi", IIC_BrB, []>, 4431 Requires<[IsE500]>; 4432def RFMCI : XForm_0<19, 38, (outs), (ins), "rfmci", IIC_BrB, []>, 4433 Requires<[IsE500]>; 4434 4435def MFDCR : XFXForm_1<31, 323, (outs gprc:$RST), (ins i32imm:$SPR), 4436 "mfdcr $RST, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>; 4437def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RST, i32imm:$SPR), 4438 "mtdcr $SPR, $RST", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; 4439 4440def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; 4441def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; 4442 4443def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; 4444 4445def LBZCIX : XForm_base_r3xo_memOp<31, 853, (outs gprc:$RST), 4446 (ins gprc:$RA, gprc:$RB), 4447 "lbzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4448def LHZCIX : XForm_base_r3xo_memOp<31, 821, (outs gprc:$RST), 4449 (ins gprc:$RA, gprc:$RB), 4450 "lhzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4451def LWZCIX : XForm_base_r3xo_memOp<31, 789, (outs gprc:$RST), 4452 (ins gprc:$RA, gprc:$RB), 4453 "lwzcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4454def LDCIX : XForm_base_r3xo_memOp<31, 885, (outs gprc:$RST), 4455 (ins gprc:$RA, gprc:$RB), 4456 "ldcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4457 4458def STBCIX : XForm_base_r3xo_memOp<31, 981, (outs), 4459 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4460 "stbcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4461def STHCIX : XForm_base_r3xo_memOp<31, 949, (outs), 4462 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4463 "sthcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4464def STWCIX : XForm_base_r3xo_memOp<31, 917, (outs), 4465 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4466 "stwcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4467def STDCIX : XForm_base_r3xo_memOp<31, 1013, (outs), 4468 (ins gprc:$RST, gprc:$RA, gprc:$RB), 4469 "stdcix $RST, $RA, $RB", IIC_LdStLoad, []>; 4470 4471// External PID Load Store Instructions 4472 4473def LBEPX : XForm_1<31, 95, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4474 "lbepx $RST, $addr", IIC_LdStLoad, []>, 4475 Requires<[IsE500]>; 4476 4477def LFDEPX : XForm_25<31, 607, (outs f8rc:$RST), (ins (memrr $RA, $RB):$addr), 4478 "lfdepx $RST, $addr", IIC_LdStLFD, []>, 4479 Requires<[IsE500]>; 4480 4481def LHEPX : XForm_1<31, 287, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4482 "lhepx $RST, $addr", IIC_LdStLoad, []>, 4483 Requires<[IsE500]>; 4484 4485def LWEPX : XForm_1<31, 31, (outs gprc:$RST), (ins (memrr $RA, $RB):$addr), 4486 "lwepx $RST, $addr", IIC_LdStLoad, []>, 4487 Requires<[IsE500]>; 4488 4489def STBEPX : XForm_8<31, 223, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4490 "stbepx $RST, $addr", IIC_LdStStore, []>, 4491 Requires<[IsE500]>; 4492 4493def STFDEPX : XForm_28_memOp<31, 735, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$addr), 4494 "stfdepx $RST, $addr", IIC_LdStSTFD, []>, 4495 Requires<[IsE500]>; 4496 4497def STHEPX : XForm_8<31, 415, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4498 "sthepx $RST, $addr", IIC_LdStStore, []>, 4499 Requires<[IsE500]>; 4500 4501def STWEPX : XForm_8<31, 159, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr), 4502 "stwepx $RST, $addr", IIC_LdStStore, []>, 4503 Requires<[IsE500]>; 4504 4505def DCBFEP : DCB_Form<127, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbfep $addr", 4506 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4507 4508def DCBSTEP : DCB_Form<63, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbstep $addr", 4509 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4510 4511def DCBTEP : DCB_Form_hint<319, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4512 "dcbtep $TH, $addr", IIC_LdStDCBF, []>, 4513 Requires<[IsE500]>; 4514 4515def DCBTSTEP : DCB_Form_hint<255, (outs), (ins (memrr $RA, $RB):$addr, u5imm:$TH), 4516 "dcbtstep $TH, $addr", IIC_LdStDCBF, []>, 4517 Requires<[IsE500]>; 4518 4519def DCBZEP : DCB_Form<1023, 0, (outs), (ins (memrr $RA, $RB):$addr), "dcbzep $addr", 4520 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4521 4522def DCBZLEP : DCB_Form<1023, 1, (outs), (ins (memrr $RA, $RB):$addr), "dcbzlep $addr", 4523 IIC_LdStDCBF, []>, Requires<[IsE500]>; 4524 4525def ICBIEP : XForm_1a<31, 991, (outs), (ins (memrr $RA, $RB):$addr), "icbiep $addr", 4526 IIC_LdStICBI, []>, Requires<[IsE500]>; 4527 4528//===----------------------------------------------------------------------===// 4529// PowerPC Assembler Instruction Aliases 4530// 4531 4532def : InstAlias<"sc", (SC 0)>; 4533 4534def : InstAlias<"sync", (SYNC 0)>, Requires<[HasSYNC]>; 4535def : InstAlias<"hwsync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4536def : InstAlias<"msync", (SYNC 0), 0>, Requires<[HasSYNC]>; 4537def : InstAlias<"lwsync", (SYNC 1)>, Requires<[HasSYNC]>; 4538def : InstAlias<"ptesync", (SYNC 2)>, Requires<[HasSYNC]>; 4539 4540def : InstAlias<"wait", (WAIT 0)>; 4541def : InstAlias<"waitrsv", (WAIT 1)>; 4542def : InstAlias<"waitimpl", (WAIT 2)>; 4543 4544def : InstAlias<"mbar", (MBAR 0)>, Requires<[IsBookE]>; 4545 4546def DCBTx : PPCAsmPseudo<"dcbt $dst", (ins memrr:$dst)>; 4547def DCBTSTx : PPCAsmPseudo<"dcbtst $dst", (ins memrr:$dst)>; 4548 4549def DCBTCT : PPCAsmPseudo<"dcbtct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4550def DCBTDS : PPCAsmPseudo<"dcbtds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4551def DCBTT : PPCAsmPseudo<"dcbtt $dst", (ins memrr:$dst)>; 4552 4553def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4554def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; 4555def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; 4556 4557def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; 4558def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; 4559def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; 4560 4561def : Pat<(int_ppc_isync), (ISYNC)>; 4562def : Pat<(int_ppc_dcbfl xoaddr:$dst), 4563 (DCBF 1, xoaddr:$dst)>; 4564def : Pat<(int_ppc_dcbflp xoaddr:$dst), 4565 (DCBF 3, xoaddr:$dst)>; 4566 4567let Predicates = [IsISA3_1] in { 4568 def DCBFPS : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>; 4569 def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>; 4570 4571 def : Pat<(int_ppc_dcbfps xoaddr:$dst), 4572 (DCBF 4, xoaddr:$dst)>; 4573 def : Pat<(int_ppc_dcbstps xoaddr:$dst), 4574 (DCBF 6, xoaddr:$dst)>; 4575} 4576 4577def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4578def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; 4579def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4580def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; 4581 4582def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>; 4583def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>; 4584def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>; 4585 4586def : InstAlias<"xnop", (XORI R0, R0, 0)>; 4587 4588def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>; 4589def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>; 4590 4591//Disable this alias on AIX for now because as does not support them. 4592let Predicates = [ModernAs] in { 4593 4594foreach BR = 0-7 in { 4595 def : InstAlias<"mfbr"#BR#" $Rx", 4596 (MFDCR gprc:$Rx, !add(BR, 0x80))>, 4597 Requires<[IsPPC4xx]>; 4598 def : InstAlias<"mtbr"#BR#" $Rx", 4599 (MTDCR gprc:$Rx, !add(BR, 0x80))>, 4600 Requires<[IsPPC4xx]>; 4601} 4602 4603def : InstAlias<"mtmsrd $RS", (MTMSRD gprc:$RS, 0)>; 4604def : InstAlias<"mtmsr $RS", (MTMSR gprc:$RS, 0)>; 4605def : InstAlias<"mtudscr $Rx", (MTSPR 3, gprc:$Rx)>; 4606def : InstAlias<"mfudscr $Rx", (MFSPR gprc:$Rx, 3)>; 4607 4608def : InstAlias<"mfrtcu $Rx", (MFSPR gprc:$Rx, 4)>; 4609def : InstAlias<"mfrtcl $Rx", (MFSPR gprc:$Rx, 5)>; 4610 4611def : InstAlias<"mtlr $Rx", (MTSPR 8, gprc:$Rx)>; 4612def : InstAlias<"mflr $Rx", (MFSPR gprc:$Rx, 8)>; 4613 4614def : InstAlias<"mtctr $Rx", (MTSPR 9, gprc:$Rx)>; 4615def : InstAlias<"mfctr $Rx", (MFSPR gprc:$Rx, 9)>; 4616 4617def : InstAlias<"mtuamr $Rx", (MTSPR 13, gprc:$Rx)>; 4618def : InstAlias<"mfuamr $Rx", (MFSPR gprc:$Rx, 13)>; 4619 4620def : InstAlias<"mtdscr $Rx", (MTSPR 17, gprc:$Rx)>; 4621def : InstAlias<"mfdscr $Rx", (MFSPR gprc:$Rx, 17)>; 4622 4623def : InstAlias<"mtdsisr $Rx", (MTSPR 18, gprc:$Rx)>; 4624def : InstAlias<"mfdsisr $Rx", (MFSPR gprc:$Rx, 18)>; 4625 4626def : InstAlias<"mtdar $Rx", (MTSPR 19, gprc:$Rx)>; 4627def : InstAlias<"mfdar $Rx", (MFSPR gprc:$Rx, 19)>; 4628 4629def : InstAlias<"mtdec $Rx", (MTSPR 22, gprc:$Rx)>; 4630def : InstAlias<"mfdec $Rx", (MFSPR gprc:$Rx, 22)>; 4631 4632def : InstAlias<"mtsdr1 $Rx", (MTSPR 25, gprc:$Rx)>; 4633def : InstAlias<"mfsdr1 $Rx", (MFSPR gprc:$Rx, 25)>; 4634 4635def : InstAlias<"mtsrr0 $Rx", (MTSPR 26, gprc:$Rx)>; 4636def : InstAlias<"mfsrr0 $Rx", (MFSPR gprc:$Rx, 26)>; 4637 4638def : InstAlias<"mtsrr1 $Rx", (MTSPR 27, gprc:$Rx)>; 4639def : InstAlias<"mfsrr1 $Rx", (MFSPR gprc:$Rx, 27)>; 4640 4641def : InstAlias<"mtcfar $Rx", (MTSPR 28, gprc:$Rx)>; 4642def : InstAlias<"mfcfar $Rx", (MFSPR gprc:$Rx, 28)>; 4643 4644def : InstAlias<"mtamr $Rx", (MTSPR 29, gprc:$Rx)>; 4645def : InstAlias<"mfamr $Rx", (MFSPR gprc:$Rx, 29)>; 4646 4647def : InstAlias<"mtpid $Rx", (MTSPR 48, gprc:$Rx)>, Requires<[IsBookE]>; 4648def : InstAlias<"mfpid $Rx", (MFSPR gprc:$Rx, 48)>, Requires<[IsBookE]>; 4649 4650foreach SPRG = 4-7 in { 4651 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 256))>, 4652 Requires<[IsBookE]>; 4653 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 256))>, 4654 Requires<[IsBookE]>; 4655 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4656 Requires<[IsBookE]>; 4657 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 256), gprc:$RT)>, 4658 Requires<[IsBookE]>; 4659} 4660 4661foreach SPRG = 0-3 in { 4662 def : InstAlias<"mfsprg $RT, "#SPRG, (MFSPR gprc:$RT, !add(SPRG, 272))>; 4663 def : InstAlias<"mfsprg"#SPRG#" $RT", (MFSPR gprc:$RT, !add(SPRG, 272))>; 4664 def : InstAlias<"mtsprg "#SPRG#", $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4665 def : InstAlias<"mtsprg"#SPRG#" $RT", (MTSPR !add(SPRG, 272), gprc:$RT)>; 4666} 4667 4668def : InstAlias<"mfasr $RT", (MFSPR gprc:$RT, 280)>; 4669def : InstAlias<"mtasr $RT", (MTSPR 280, gprc:$RT)>; 4670 4671def : InstAlias<"mttbl $Rx", (MTSPR 284, gprc:$Rx)>; 4672def : InstAlias<"mttbu $Rx", (MTSPR 285, gprc:$Rx)>; 4673 4674def : InstAlias<"mfpvr $RT", (MFSPR gprc:$RT, 287)>; 4675 4676def : InstAlias<"mfspefscr $Rx", (MFSPR gprc:$Rx, 512)>; 4677def : InstAlias<"mtspefscr $Rx", (MTSPR 512, gprc:$Rx)>; 4678 4679foreach BATR = 0-3 in { 4680 def : InstAlias<"mtdbatu "#BATR#", $Rx", 4681 (MTSPR !add(BATR, !add(BATR, 536)), gprc:$Rx)>, 4682 Requires<[IsPPC6xx]>; 4683 def : InstAlias<"mfdbatu $Rx, "#BATR, 4684 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 536)))>, 4685 Requires<[IsPPC6xx]>; 4686 def : InstAlias<"mtdbatl "#BATR#", $Rx", 4687 (MTSPR !add(BATR, !add(BATR, 537)), gprc:$Rx)>, 4688 Requires<[IsPPC6xx]>; 4689 def : InstAlias<"mfdbatl $Rx, "#BATR, 4690 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 537)))>, 4691 Requires<[IsPPC6xx]>; 4692 def : InstAlias<"mtibatu "#BATR#", $Rx", 4693 (MTSPR !add(BATR, !add(BATR, 528)), gprc:$Rx)>, 4694 Requires<[IsPPC6xx]>; 4695 def : InstAlias<"mfibatu $Rx, "#BATR, 4696 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 528)))>, 4697 Requires<[IsPPC6xx]>; 4698 def : InstAlias<"mtibatl "#BATR#", $Rx", 4699 (MTSPR !add(BATR, !add(BATR, 529)), gprc:$Rx)>, 4700 Requires<[IsPPC6xx]>; 4701 def : InstAlias<"mfibatl $Rx, "#BATR, 4702 (MFSPR gprc:$Rx, !add(BATR, !add(BATR, 529)))>, 4703 Requires<[IsPPC6xx]>; 4704} 4705 4706def : InstAlias<"mtppr $RT", (MTSPR 896, gprc:$RT)>; 4707def : InstAlias<"mfppr $RT", (MFSPR gprc:$RT, 896)>; 4708 4709def : InstAlias<"mtesr $Rx", (MTSPR 980, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4710def : InstAlias<"mfesr $Rx", (MFSPR gprc:$Rx, 980)>, Requires<[IsPPC4xx]>; 4711 4712def : InstAlias<"mtdear $Rx", (MTSPR 981, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4713def : InstAlias<"mfdear $Rx", (MFSPR gprc:$Rx, 981)>, Requires<[IsPPC4xx]>; 4714 4715def : InstAlias<"mttcr $Rx", (MTSPR 986, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4716def : InstAlias<"mftcr $Rx", (MFSPR gprc:$Rx, 986)>, Requires<[IsPPC4xx]>; 4717 4718def : InstAlias<"mftbhi $Rx", (MFSPR gprc:$Rx, 988)>, Requires<[IsPPC4xx]>; 4719def : InstAlias<"mttbhi $Rx", (MTSPR 988, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4720 4721def : InstAlias<"mftblo $Rx", (MFSPR gprc:$Rx, 989)>, Requires<[IsPPC4xx]>; 4722def : InstAlias<"mttblo $Rx", (MTSPR 989, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4723 4724def : InstAlias<"mtsrr2 $Rx", (MTSPR 990, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4725def : InstAlias<"mfsrr2 $Rx", (MFSPR gprc:$Rx, 990)>, Requires<[IsPPC4xx]>; 4726 4727def : InstAlias<"mtsrr3 $Rx", (MTSPR 991, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4728def : InstAlias<"mfsrr3 $Rx", (MFSPR gprc:$Rx, 991)>, Requires<[IsPPC4xx]>; 4729 4730def : InstAlias<"mtdccr $Rx", (MTSPR 1018, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4731def : InstAlias<"mfdccr $Rx", (MFSPR gprc:$Rx, 1018)>, Requires<[IsPPC4xx]>; 4732 4733def : InstAlias<"mticcr $Rx", (MTSPR 1019, gprc:$Rx)>, Requires<[IsPPC4xx]>; 4734def : InstAlias<"mficcr $Rx", (MFSPR gprc:$Rx, 1019)>, Requires<[IsPPC4xx]>; 4735 4736} 4737 4738def : InstAlias<"tlbie $RB", (TLBIE R0, gprc:$RB)>; 4739 4740def : InstAlias<"tlbrehi $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 0)>, 4741 Requires<[IsPPC4xx]>; 4742def : InstAlias<"tlbrelo $RS, $A", (TLBRE2 gprc:$RS, gprc:$A, 1)>, 4743 Requires<[IsPPC4xx]>; 4744def : InstAlias<"tlbwehi $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 0)>, 4745 Requires<[IsPPC4xx]>; 4746def : InstAlias<"tlbwelo $RS, $A", (TLBWE2 gprc:$RS, gprc:$A, 1)>, 4747 Requires<[IsPPC4xx]>; 4748 4749def : InstAlias<"tlbilxlpid", (TLBILX 0, R0, R0)>, Requires<[IsBookE]>; 4750def : InstAlias<"tlbilxpid", (TLBILX 1, R0, R0)>, Requires<[IsBookE]>; 4751def : InstAlias<"tlbilxva $RA, $RB", (TLBILX 3, gprc:$RA, gprc:$RB)>, 4752 Requires<[IsBookE]>; 4753def : InstAlias<"tlbilxva $RB", (TLBILX 3, R0, gprc:$RB)>, Requires<[IsBookE]>; 4754 4755def LAx : PPCAsmPseudo<"la $rA, $addr", (ins gprc:$rA, memri:$addr)>, MemriOp; 4756 4757def SUBI : PPCAsmPseudo<"subi $rA, $rB, $imm", 4758 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4759def SUBIS : PPCAsmPseudo<"subis $rA, $rB, $imm", 4760 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4761def SUBIC : PPCAsmPseudo<"subic $rA, $rB, $imm", 4762 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4763def SUBIC_rec : PPCAsmPseudo<"subic. $rA, $rB, $imm", 4764 (ins gprc:$rA, gprc:$rB, s16imm:$imm)>; 4765 4766def EXTLWI : PPCAsmPseudo<"extlwi $rA, $rS, $n, $b", 4767 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4768 ZExt32To64; 4769def EXTLWI_rec : PPCAsmPseudo<"extlwi. $rA, $rS, $n, $b", 4770 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>, 4771 ZExt32To64; 4772def EXTRWI : PPCAsmPseudo<"extrwi $rA, $rS, $n, $b", 4773 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4774def EXTRWI_rec : PPCAsmPseudo<"extrwi. $rA, $rS, $n, $b", 4775 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4776def INSLWI : PPCAsmPseudo<"inslwi $rA, $rS, $n, $b", 4777 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4778def INSLWI_rec : PPCAsmPseudo<"inslwi. $rA, $rS, $n, $b", 4779 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4780def INSRWI : PPCAsmPseudo<"insrwi $rA, $rS, $n, $b", 4781 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4782def INSRWI_rec : PPCAsmPseudo<"insrwi. $rA, $rS, $n, $b", 4783 (ins gprc:$rA, gprc:$rS, u5imm:$n, u5imm:$b)>; 4784def ROTRWI : PPCAsmPseudo<"rotrwi $rA, $rS, $n", 4785 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4786def ROTRWI_rec : PPCAsmPseudo<"rotrwi. $rA, $rS, $n", 4787 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4788def SLWI : PPCAsmPseudo<"slwi $rA, $rS, $n", 4789 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4790def SLWI_rec : PPCAsmPseudo<"slwi. $rA, $rS, $n", 4791 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4792def SRWI : PPCAsmPseudo<"srwi $rA, $rS, $n", 4793 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4794def SRWI_rec : PPCAsmPseudo<"srwi. $rA, $rS, $n", 4795 (ins gprc:$rA, gprc:$rS, u5imm:$n)>, ZExt32To64; 4796def CLRRWI : PPCAsmPseudo<"clrrwi $rA, $rS, $n", 4797 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4798def CLRRWI_rec : PPCAsmPseudo<"clrrwi. $rA, $rS, $n", 4799 (ins gprc:$rA, gprc:$rS, u5imm:$n)>; 4800def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n", 4801 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4802def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n", 4803 (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>; 4804 4805def : InstAlias<"isellt $rT, $rA, $rB", 4806 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>; 4807def : InstAlias<"iselgt $rT, $rA, $rB", 4808 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>; 4809def : InstAlias<"iseleq $rT, $rA, $rB", 4810 (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>; 4811 4812def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4813def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>; 4814def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4815def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>; 4816def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4817def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31)>; 4818 4819def : InstAlias<"cntlzw $rA, $rS", (CNTLZW gprc:$rA, gprc:$rS)>; 4820def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW_rec gprc:$rA, gprc:$rS)>; 4821// The POWER variant 4822def : MnemonicAlias<"cntlz", "cntlzw">; 4823def : MnemonicAlias<"cntlz.", "cntlzw.">; 4824 4825def EXTLDI : PPCAsmPseudo<"extldi $rA, $rS, $n, $b", 4826 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4827def EXTLDI_rec : PPCAsmPseudo<"extldi. $rA, $rS, $n, $b", 4828 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4829def EXTRDI : PPCAsmPseudo<"extrdi $rA, $rS, $n, $b", 4830 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4831def EXTRDI_rec : PPCAsmPseudo<"extrdi. $rA, $rS, $n, $b", 4832 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4833def INSRDI : PPCAsmPseudo<"insrdi $rA, $rS, $n, $b", 4834 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4835def INSRDI_rec : PPCAsmPseudo<"insrdi. $rA, $rS, $n, $b", 4836 (ins g8rc:$rA, g8rc:$rS, u6imm:$n, u6imm:$b)>; 4837def ROTRDI : PPCAsmPseudo<"rotrdi $rA, $rS, $n", 4838 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4839def ROTRDI_rec : PPCAsmPseudo<"rotrdi. $rA, $rS, $n", 4840 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4841def SLDI : PPCAsmPseudo<"sldi $rA, $rS, $n", 4842 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4843def SLDI_rec : PPCAsmPseudo<"sldi. $rA, $rS, $n", 4844 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4845def SRDI : PPCAsmPseudo<"srdi $rA, $rS, $n", 4846 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4847def SRDI_rec : PPCAsmPseudo<"srdi. $rA, $rS, $n", 4848 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4849def CLRRDI : PPCAsmPseudo<"clrrdi $rA, $rS, $n", 4850 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4851def CLRRDI_rec : PPCAsmPseudo<"clrrdi. $rA, $rS, $n", 4852 (ins g8rc:$rA, g8rc:$rS, u6imm:$n)>; 4853def CLRLSLDI : PPCAsmPseudo<"clrlsldi $rA, $rS, $b, $n", 4854 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4855def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n", 4856 (ins g8rc:$rA, g8rc:$rS, u6imm:$b, u6imm:$n)>; 4857def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>; 4858 4859def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4860def : InstAlias<"rotldi $rA, $rS, $n", 4861 (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>; 4862def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>; 4863def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4864def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>; 4865def : InstAlias<"clrldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4866def : InstAlias<"clrldi $rA, $rS, $n", 4867 (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n)>; 4868def : InstAlias<"clrldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n)>; 4869def : InstAlias<"lnia $RT", (ADDPCIS g8rc:$RT, 0)>; 4870 4871def RLWINMbm : PPCAsmPseudo<"rlwinm $rA, $rS, $n, $b", 4872 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4873def RLWINMbm_rec : PPCAsmPseudo<"rlwinm. $rA, $rS, $n, $b", 4874 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4875def RLWIMIbm : PPCAsmPseudo<"rlwimi $rA, $rS, $n, $b", 4876 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4877def RLWIMIbm_rec : PPCAsmPseudo<"rlwimi. $rA, $rS, $n, $b", 4878 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4879def RLWNMbm : PPCAsmPseudo<"rlwnm $rA, $rS, $n, $b", 4880 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4881def RLWNMbm_rec : PPCAsmPseudo<"rlwnm. $rA, $rS, $n, $b", 4882 (ins g8rc:$rA, g8rc:$rS, u5imm:$n, i32imm:$b)>; 4883def PPCLdFixedAddr : 4884 PPCPostRAExpPseudo<(outs gprc:$rT), (ins i32imm:$imm), "#FA_LOAD", 4885 [(set i32:$rT, (int_ppc_fixed_addr_ld timm:$imm))]>; 4886 4887// These generic branch instruction forms are used for the assembler parser only. 4888// Defs and Uses are conservative, since we don't know the BO value. 4889let PPC970_Unit = 7, isBranch = 1, hasSideEffects = 0 in { 4890 let Defs = [CTR], Uses = [CTR, RM] in { 4891 def gBC : BForm_3<16, 0, 0, (outs), 4892 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4893 "bc $BO, $BI, $BD">; 4894 def gBCA : BForm_3<16, 1, 0, (outs), 4895 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4896 "bca $BO, $BI, $BD">; 4897 let isAsmParserOnly = 1 in { 4898 def gBCat : BForm_3_at<16, 0, 0, (outs), 4899 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4900 condbrtarget:$BD), 4901 "bc$at $BO, $BI, $BD">; 4902 def gBCAat : BForm_3_at<16, 1, 0, (outs), 4903 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4904 abscondbrtarget:$BD), 4905 "bca$at $BO, $BI, $BD">; 4906 } // isAsmParserOnly = 1 4907 } 4908 let Defs = [LR, CTR], Uses = [CTR, RM] in { 4909 def gBCL : BForm_3<16, 0, 1, (outs), 4910 (ins u5imm:$BO, crbitrc:$BI, condbrtarget:$BD), 4911 "bcl $BO, $BI, $BD">; 4912 def gBCLA : BForm_3<16, 1, 1, (outs), 4913 (ins u5imm:$BO, crbitrc:$BI, abscondbrtarget:$BD), 4914 "bcla $BO, $BI, $BD">; 4915 let isAsmParserOnly = 1 in { 4916 def gBCLat : BForm_3_at<16, 0, 1, (outs), 4917 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4918 condbrtarget:$BD), 4919 "bcl$at $BO, $BI, $BD">; 4920 def gBCLAat : BForm_3_at<16, 1, 1, (outs), 4921 (ins u5imm:$BO, atimm:$at, crbitrc:$BI, 4922 abscondbrtarget:$BD), 4923 "bcla$at $BO, $BI, $BD">; 4924 } // // isAsmParserOnly = 1 4925 } 4926 let Defs = [CTR], Uses = [CTR, LR, RM] in 4927 def gBCLR : XLForm_2<19, 16, 0, (outs), 4928 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4929 "bclr $BO, $BI, $BH", IIC_BrB, []>; 4930 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4931 def gBCLRL : XLForm_2<19, 16, 1, (outs), 4932 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4933 "bclrl $BO, $BI, $BH", IIC_BrB, []>; 4934 let Defs = [CTR], Uses = [CTR, LR, RM] in 4935 def gBCCTR : XLForm_2<19, 528, 0, (outs), 4936 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4937 "bcctr $BO, $BI, $BH", IIC_BrB, []>; 4938 let Defs = [LR, CTR], Uses = [CTR, LR, RM] in 4939 def gBCCTRL : XLForm_2<19, 528, 1, (outs), 4940 (ins u5imm:$BO, crbitrc:$BI, i32imm:$BH), 4941 "bcctrl $BO, $BI, $BH", IIC_BrB, []>; 4942} 4943 4944multiclass BranchSimpleMnemonicAT<string pm, int at> { 4945 def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, 4946 condbrtarget:$dst)>; 4947 def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, 4948 condbrtarget:$dst)>; 4949 def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, 4950 condbrtarget:$dst)>; 4951 def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, 4952 condbrtarget:$dst)>; 4953} 4954defm : BranchSimpleMnemonicAT<"+", 3>; 4955defm : BranchSimpleMnemonicAT<"-", 2>; 4956 4957def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; 4958def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; 4959def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; 4960def : InstAlias<"bcctrl $bo, $bi", (gBCCTRL u5imm:$bo, crbitrc:$bi, 0)>; 4961 4962multiclass BranchSimpleMnemonic1<string name, string pm, int bo> { 4963 def : InstAlias<"b"#name#pm#" $bi, $dst", (gBC bo, crbitrc:$bi, condbrtarget:$dst)>; 4964 def : InstAlias<"b"#name#"a"#pm#" $bi, $dst", (gBCA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4965 def : InstAlias<"b"#name#"lr"#pm#" $bi", (gBCLR bo, crbitrc:$bi, 0)>; 4966 def : InstAlias<"b"#name#"l"#pm#" $bi, $dst", (gBCL bo, crbitrc:$bi, condbrtarget:$dst)>; 4967 def : InstAlias<"b"#name#"la"#pm#" $bi, $dst", (gBCLA bo, crbitrc:$bi, abscondbrtarget:$dst)>; 4968 def : InstAlias<"b"#name#"lrl"#pm#" $bi", (gBCLRL bo, crbitrc:$bi, 0)>; 4969} 4970multiclass BranchSimpleMnemonic2<string name, string pm, int bo> 4971 : BranchSimpleMnemonic1<name, pm, bo> { 4972 def : InstAlias<"b"#name#"ctr"#pm#" $bi", (gBCCTR bo, crbitrc:$bi, 0)>; 4973 def : InstAlias<"b"#name#"ctrl"#pm#" $bi", (gBCCTRL bo, crbitrc:$bi, 0)>; 4974} 4975defm : BranchSimpleMnemonic2<"t", "", 12>; 4976defm : BranchSimpleMnemonic2<"f", "", 4>; 4977defm : BranchSimpleMnemonic2<"t", "-", 14>; 4978defm : BranchSimpleMnemonic2<"f", "-", 6>; 4979defm : BranchSimpleMnemonic2<"t", "+", 15>; 4980defm : BranchSimpleMnemonic2<"f", "+", 7>; 4981defm : BranchSimpleMnemonic1<"dnzt", "", 8>; 4982defm : BranchSimpleMnemonic1<"dnzf", "", 0>; 4983defm : BranchSimpleMnemonic1<"dzt", "", 10>; 4984defm : BranchSimpleMnemonic1<"dzf", "", 2>; 4985 4986multiclass BranchExtendedMnemonicPM<string name, string pm, int bibo> { 4987 def : InstAlias<"b"#name#pm#" $cc, $dst", 4988 (BCC bibo, crrc:$cc, condbrtarget:$dst)>; 4989 def : InstAlias<"b"#name#pm#" $dst", 4990 (BCC bibo, CR0, condbrtarget:$dst)>; 4991 4992 def : InstAlias<"b"#name#"a"#pm#" $cc, $dst", 4993 (BCCA bibo, crrc:$cc, abscondbrtarget:$dst)>; 4994 def : InstAlias<"b"#name#"a"#pm#" $dst", 4995 (BCCA bibo, CR0, abscondbrtarget:$dst)>; 4996 4997 def : InstAlias<"b"#name#"lr"#pm#" $cc", 4998 (BCCLR bibo, crrc:$cc)>; 4999 def : InstAlias<"b"#name#"lr"#pm, 5000 (BCCLR bibo, CR0)>; 5001 5002 def : InstAlias<"b"#name#"ctr"#pm#" $cc", 5003 (BCCCTR bibo, crrc:$cc)>; 5004 def : InstAlias<"b"#name#"ctr"#pm, 5005 (BCCCTR bibo, CR0)>; 5006 5007 def : InstAlias<"b"#name#"l"#pm#" $cc, $dst", 5008 (BCCL bibo, crrc:$cc, condbrtarget:$dst)>; 5009 def : InstAlias<"b"#name#"l"#pm#" $dst", 5010 (BCCL bibo, CR0, condbrtarget:$dst)>; 5011 5012 def : InstAlias<"b"#name#"la"#pm#" $cc, $dst", 5013 (BCCLA bibo, crrc:$cc, abscondbrtarget:$dst)>; 5014 def : InstAlias<"b"#name#"la"#pm#" $dst", 5015 (BCCLA bibo, CR0, abscondbrtarget:$dst)>; 5016 5017 def : InstAlias<"b"#name#"lrl"#pm#" $cc", 5018 (BCCLRL bibo, crrc:$cc)>; 5019 def : InstAlias<"b"#name#"lrl"#pm, 5020 (BCCLRL bibo, CR0)>; 5021 5022 def : InstAlias<"b"#name#"ctrl"#pm#" $cc", 5023 (BCCCTRL bibo, crrc:$cc)>; 5024 def : InstAlias<"b"#name#"ctrl"#pm, 5025 (BCCCTRL bibo, CR0)>; 5026} 5027multiclass BranchExtendedMnemonic<string name, int bibo> { 5028 defm : BranchExtendedMnemonicPM<name, "", bibo>; 5029 defm : BranchExtendedMnemonicPM<name, "-", !add(bibo, 2)>; 5030 defm : BranchExtendedMnemonicPM<name, "+", !add(bibo, 3)>; 5031} 5032defm : BranchExtendedMnemonic<"lt", 12>; 5033defm : BranchExtendedMnemonic<"gt", 44>; 5034defm : BranchExtendedMnemonic<"eq", 76>; 5035defm : BranchExtendedMnemonic<"un", 108>; 5036defm : BranchExtendedMnemonic<"so", 108>; 5037defm : BranchExtendedMnemonic<"ge", 4>; 5038defm : BranchExtendedMnemonic<"nl", 4>; 5039defm : BranchExtendedMnemonic<"le", 36>; 5040defm : BranchExtendedMnemonic<"ng", 36>; 5041defm : BranchExtendedMnemonic<"ne", 68>; 5042defm : BranchExtendedMnemonic<"nu", 100>; 5043defm : BranchExtendedMnemonic<"ns", 100>; 5044 5045def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>; 5046def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>; 5047def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>; 5048def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>; 5049def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm64:$imm)>; 5050def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>; 5051def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm64:$imm)>; 5052def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>; 5053 5054def : InstAlias<"cmpi $bf, 0, $rA, $imm", (CMPWI crrc:$bf, gprc:$rA, s16imm:$imm)>; 5055def : InstAlias<"cmp $bf, 0, $rA, $rB", (CMPW crrc:$bf, gprc:$rA, gprc:$rB)>; 5056def : InstAlias<"cmpli $bf, 0, $rA, $imm", (CMPLWI crrc:$bf, gprc:$rA, u16imm:$imm)>; 5057def : InstAlias<"cmpl $bf, 0, $rA, $rB", (CMPLW crrc:$bf, gprc:$rA, gprc:$rB)>; 5058def : InstAlias<"cmpi $bf, 1, $rA, $imm", (CMPDI crrc:$bf, g8rc:$rA, s16imm64:$imm)>; 5059def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5060def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>; 5061def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>; 5062 5063def : InstAlias<"trap", (TW 31, R0, R0)>; 5064 5065multiclass TrapExtendedMnemonic<string name, int to> { 5066 def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>; 5067 def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>; 5068 def : InstAlias<"tw"#name#"i $rA, $imm", (TWI to, gprc:$rA, s16imm:$imm)>; 5069 def : InstAlias<"tw"#name#" $rA, $rB", (TW to, gprc:$rA, gprc:$rB)>; 5070} 5071defm : TrapExtendedMnemonic<"lt", 16>; 5072defm : TrapExtendedMnemonic<"le", 20>; 5073defm : TrapExtendedMnemonic<"eq", 4>; 5074defm : TrapExtendedMnemonic<"ge", 12>; 5075defm : TrapExtendedMnemonic<"gt", 8>; 5076defm : TrapExtendedMnemonic<"nl", 12>; 5077defm : TrapExtendedMnemonic<"ne", 24>; 5078defm : TrapExtendedMnemonic<"ng", 20>; 5079defm : TrapExtendedMnemonic<"llt", 2>; 5080defm : TrapExtendedMnemonic<"lle", 6>; 5081defm : TrapExtendedMnemonic<"lge", 5>; 5082defm : TrapExtendedMnemonic<"lgt", 1>; 5083defm : TrapExtendedMnemonic<"lnl", 5>; 5084defm : TrapExtendedMnemonic<"lng", 6>; 5085defm : TrapExtendedMnemonic<"u", 31>; 5086 5087// Atomic loads 5088def : Pat<(i32 (atomic_load_azext_8 DForm:$src)), (LBZ memri:$src)>; 5089def : Pat<(i32 (atomic_load_azext_16 DForm:$src)), (LHZ memri:$src)>; 5090def : Pat<(i32 (atomic_load_nonext_32 DForm:$src)), (LWZ memri:$src)>; 5091def : Pat<(i32 (atomic_load_azext_8 XForm:$src)), (LBZX memrr:$src)>; 5092def : Pat<(i32 (atomic_load_azext_16 XForm:$src)), (LHZX memrr:$src)>; 5093def : Pat<(i32 (atomic_load_nonext_32 XForm:$src)), (LWZX memrr:$src)>; 5094 5095// Atomic stores 5096def : Pat<(atomic_store_8 i32:$val, DForm:$ptr), (STB gprc:$val, memri:$ptr)>; 5097def : Pat<(atomic_store_16 i32:$val, DForm:$ptr), (STH gprc:$val, memri:$ptr)>; 5098def : Pat<(atomic_store_32 i32:$val, DForm:$ptr), (STW gprc:$val, memri:$ptr)>; 5099def : Pat<(atomic_store_8 i32:$val, XForm:$ptr), (STBX gprc:$val, memrr:$ptr)>; 5100def : Pat<(atomic_store_16 i32:$val, XForm:$ptr), (STHX gprc:$val, memrr:$ptr)>; 5101def : Pat<(atomic_store_32 i32:$val, XForm:$ptr), (STWX gprc:$val, memrr:$ptr)>; 5102 5103let Predicates = [IsISA3_0] in { 5104 5105// Copy-Paste Facility 5106// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to 5107// PASTE for naming consistency. 5108let mayLoad = 1 in 5109def CP_COPY : X_RA5_RB5<31, 774, "copy" , gprc, IIC_LdStCOPY, []>; 5110 5111let mayStore = 1, Defs = [CR0] in 5112def CP_PASTE_rec : X_L1_RA5_RB5<31, 902, "paste.", gprc, IIC_LdStPASTE, []>, isRecordForm; 5113 5114def : InstAlias<"paste. $RA, $RB", (CP_PASTE_rec gprc:$RA, gprc:$RB, 1)>; 5115def CP_ABORT : XForm_0<31, 838, (outs), (ins), "cpabort", IIC_SprABORT, []>; 5116 5117// Message Synchronize 5118def MSGSYNC : XForm_0<31, 886, (outs), (ins), "msgsync", IIC_SprMSGSYNC, []>; 5119 5120// Power-Saving Mode Instruction: 5121def STOP : XForm_0<19, 370, (outs), (ins), "stop", IIC_SprSTOP, []>; 5122 5123def SETB : XForm_44<31, 128, (outs gprc:$RT), (ins crrc:$BFA), 5124 "setb $RT, $BFA", IIC_IntGeneral>, SExt32To64; 5125} // IsISA3_0 5126 5127let Predicates = [IsISA3_0] in { 5128def : Pat<(i32 (int_ppc_cmprb i32:$a, gprc:$b, gprc:$c)), 5129 (i32 (SETB (CMPRB u1imm:$a, $b, $c)))>; 5130} 5131def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)), 5132 (i32 (MULHW $a, $b))>; 5133def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)), 5134 (i32 (MULHWU $a, $b))>; 5135def : Pat<(i32 (int_ppc_cmpb gprc:$a, gprc:$b)), 5136 (i32 (CMPB $a, $b))>; 5137 5138def : Pat<(int_ppc_load2r ForceXForm:$ptr), 5139 (LHBRX ForceXForm:$ptr)>; 5140def : Pat<(int_ppc_load4r ForceXForm:$ptr), 5141 (LWBRX ForceXForm:$ptr)>; 5142def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr), 5143 (STHBRX gprc:$a, ForceXForm:$ptr)>; 5144def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr), 5145 (STWBRX gprc:$a, ForceXForm:$ptr)>; 5146 5147// Fast 32-bit reverse bits algorithm: 5148// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5149// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA); 5150// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5151// n = ((n >> 2) & 0x33333333) | ((n << 2) & 0xCCCCCCCC); 5152// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5153// n = ((n >> 4) & 0x0F0F0F0F) | ((n << 4) & 0xF0F0F0F0); 5154// Step 4: byte reverse (Suppose n = [B1,B2,B3,B4]): 5155// Step 4.1: Put B4,B2 in the right position (rotate left 3 bytes): 5156// n' = (n rotl 24); After which n' = [B4, B1, B2, B3] 5157// Step 4.2: Insert B3 to the right position: 5158// n' = rlwimi n', n, 8, 8, 15; After which n' = [B4, B3, B2, B3] 5159// Step 4.3: Insert B1 to the right position: 5160// n' = rlwimi n', n, 8, 24, 31; After which n' = [B4, B3, B2, B1] 5161def MaskValues { 5162 dag Lo1 = (ORI (LIS 0x5555), 0x5555); 5163 dag Hi1 = (ORI (LIS 0xAAAA), 0xAAAA); 5164 dag Lo2 = (ORI (LIS 0x3333), 0x3333); 5165 dag Hi2 = (ORI (LIS 0xCCCC), 0xCCCC); 5166 dag Lo4 = (ORI (LIS 0x0F0F), 0x0F0F); 5167 dag Hi4 = (ORI (LIS 0xF0F0), 0xF0F0); 5168} 5169 5170def Shift1 { 5171 dag Right = (RLWINM $A, 31, 1, 31); 5172 dag Left = (RLWINM $A, 1, 0, 30); 5173} 5174 5175def Swap1 { 5176 dag Bit = (OR (AND Shift1.Right, MaskValues.Lo1), 5177 (AND Shift1.Left, MaskValues.Hi1)); 5178} 5179 5180def Shift2 { 5181 dag Right = (RLWINM Swap1.Bit, 30, 2, 31); 5182 dag Left = (RLWINM Swap1.Bit, 2, 0, 29); 5183} 5184 5185def Swap2 { 5186 dag Bits = (OR (AND Shift2.Right, MaskValues.Lo2), 5187 (AND Shift2.Left, MaskValues.Hi2)); 5188} 5189 5190def Shift4 { 5191 dag Right = (RLWINM Swap2.Bits, 28, 4, 31); 5192 dag Left = (RLWINM Swap2.Bits, 4, 0, 27); 5193} 5194 5195def Swap4 { 5196 dag Bits = (OR (AND Shift4.Right, MaskValues.Lo4), 5197 (AND Shift4.Left, MaskValues.Hi4)); 5198} 5199 5200def Rotate { 5201 dag Left3Bytes = (RLWINM Swap4.Bits, 24, 0, 31); 5202} 5203 5204def RotateInsertByte3 { 5205 dag Left = (RLWIMI Rotate.Left3Bytes, Swap4.Bits, 8, 8, 15); 5206} 5207 5208def RotateInsertByte1 { 5209 dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31); 5210} 5211 5212// Clear the upper half of the register when in 64-bit mode 5213let Predicates = [In64BitMode] in 5214def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>; 5215let Predicates = [In32BitMode] in 5216def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>; 5217 5218// Fast 64-bit reverse bits algorithm: 5219// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit): 5220// n = ((n >> 1) & 0x5555555555555555) | ((n << 1) & 0xAAAAAAAAAAAAAAAA); 5221// Step 2: 2-bit swap (swap odd 2-bit and even 2-bit): 5222// n = ((n >> 2) & 0x3333333333333333) | ((n << 2) & 0xCCCCCCCCCCCCCCCC); 5223// Step 3: 4-bit swap (swap odd 4-bit and even 4-bit): 5224// n = ((n >> 4) & 0x0F0F0F0F0F0F0F0F) | ((n << 4) & 0xF0F0F0F0F0F0F0F0); 5225// Step 4: byte reverse (Suppose n = [B0,B1,B2,B3,B4,B5,B6,B7]): 5226// Apply the same byte reverse algorithm mentioned above for the fast 32-bit 5227// reverse to both the high 32 bit and low 32 bit of the 64 bit value. And 5228// then OR them together to get the final result. 5229def MaskValues64 { 5230 dag Lo1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo1, sub_32)); 5231 dag Hi1 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi1, sub_32)); 5232 dag Lo2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo2, sub_32)); 5233 dag Hi2 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi2, sub_32)); 5234 dag Lo4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Lo4, sub_32)); 5235 dag Hi4 = (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), MaskValues.Hi4, sub_32)); 5236} 5237 5238def DWMaskValues { 5239 dag Lo1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo1, 32, 31), 0x5555), 0x5555); 5240 dag Hi1 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi1, 32, 31), 0xAAAA), 0xAAAA); 5241 dag Lo2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo2, 32, 31), 0x3333), 0x3333); 5242 dag Hi2 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi2, 32, 31), 0xCCCC), 0xCCCC); 5243 dag Lo4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Lo4, 32, 31), 0x0F0F), 0x0F0F); 5244 dag Hi4 = (ORI8 (ORIS8 (RLDICR MaskValues64.Hi4, 32, 31), 0xF0F0), 0xF0F0); 5245} 5246 5247def DWSwapInByte { 5248 dag Swap1 = (OR8 (AND8 (RLDICL $A, 63, 1), DWMaskValues.Lo1), 5249 (AND8 (RLDICR $A, 1, 62), DWMaskValues.Hi1)); 5250 dag Swap2 = (OR8 (AND8 (RLDICL Swap1, 62, 2), DWMaskValues.Lo2), 5251 (AND8 (RLDICR Swap1, 2, 61), DWMaskValues.Hi2)); 5252 dag Swap4 = (OR8 (AND8 (RLDICL Swap2, 60, 4), DWMaskValues.Lo4), 5253 (AND8 (RLDICR Swap2, 4, 59), DWMaskValues.Hi4)); 5254} 5255 5256// Intra-byte swap is done, now start inter-byte swap. 5257def DWBytes4567 { 5258 dag Word = (i32 (EXTRACT_SUBREG DWSwapInByte.Swap4, sub_32)); 5259} 5260 5261def DWBytes7456 { 5262 dag Word = (RLWINM DWBytes4567.Word, 24, 0, 31); 5263} 5264 5265def DWBytes7656 { 5266 dag Word = (RLWIMI DWBytes7456.Word, DWBytes4567.Word, 8, 8, 15); 5267} 5268 5269// B7 B6 B5 B4 in the right order 5270def DWBytes7654 { 5271 dag Word = (RLWIMI DWBytes7656.Word, DWBytes4567.Word, 8, 24, 31); 5272 dag DWord = 5273 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5274} 5275 5276def DWBytes0123 { 5277 dag Word = (i32 (EXTRACT_SUBREG (RLDICL DWSwapInByte.Swap4, 32, 32), sub_32)); 5278} 5279 5280def DWBytes3012 { 5281 dag Word = (RLWINM DWBytes0123.Word, 24, 0, 31); 5282} 5283 5284def DWBytes3212 { 5285 dag Word = (RLWIMI DWBytes3012.Word, DWBytes0123.Word, 8, 8, 15); 5286} 5287 5288// B3 B2 B1 B0 in the right order 5289def DWBytes3210 { 5290 dag Word = (RLWIMI DWBytes3212.Word, DWBytes0123.Word, 8, 24, 31); 5291 dag DWord = 5292 (i64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), Word, sub_32)); 5293} 5294 5295// These instructions store a hash computed from the value of the link register 5296// and the value of the stack pointer. 5297let mayStore = 1 in { 5298def HASHST : XForm_XD6_RA5_RB5<31, 722, (outs), 5299 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5300 "hashst $RB, $addr", IIC_IntGeneral, []>; 5301def HASHSTP : XForm_XD6_RA5_RB5<31, 658, (outs), 5302 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5303 "hashstp $RB, $addr", IIC_IntGeneral, []>; 5304} 5305 5306// These instructions check a hash computed from the value of the link register 5307// and the value of the stack pointer. The hasSideEffects flag is needed as the 5308// instruction may TRAP if the hash does not match the hash stored at the 5309// specified address. 5310let mayLoad = 1, hasSideEffects = 1 in { 5311def HASHCHK : XForm_XD6_RA5_RB5<31, 754, (outs), 5312 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5313 "hashchk $RB, $addr", IIC_IntGeneral, []>; 5314def HASHCHKP : XForm_XD6_RA5_RB5<31, 690, (outs), 5315 (ins gprc:$RB, (memrihash $D, $RA):$addr), 5316 "hashchkp $RB, $addr", IIC_IntGeneral, []>; 5317} 5318 5319let Defs = [CR7], Itinerary = IIC_LdStSync in 5320def CFENCE : PPCPostRAExpPseudo<(outs), (ins gprc:$cr), "#CFENCE", []>; 5321 5322// Now both high word and low word are reversed, next 5323// swap the high word and low word. 5324def : Pat<(i64 (bitreverse i64:$A)), 5325 (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>; 5326 5327def : Pat<(int_ppc_lwarx ForceXForm:$ptr), 5328 (LWARX ForceXForm:$ptr)>; 5329def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A), 5330 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5331def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 4), 5332 (RLWINM (STWCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5333def : Pat<(int_ppc_lbarx ForceXForm:$ptr), 5334 (LBARX ForceXForm:$ptr)>; 5335def : Pat<(int_ppc_stbcx ForceXForm:$dst, gprc:$A), 5336 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5337def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 1), 5338 (RLWINM (STBCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5339 5340def : Pat<(int_ppc_fcfid f64:$A), 5341 (XSCVSXDDP $A)>; 5342def : Pat<(int_ppc_fcfud f64:$A), 5343 (XSCVUXDDP $A)>; 5344def : Pat<(int_ppc_fctid f64:$A), 5345 (FCTID $A)>; 5346def : Pat<(int_ppc_fctidz f64:$A), 5347 (XSCVDPSXDS $A)>; 5348def : Pat<(int_ppc_fctiw f64:$A), 5349 (FCTIW $A)>; 5350def : Pat<(int_ppc_fctiwz f64:$A), 5351 (XSCVDPSXWS $A)>; 5352def : Pat<(int_ppc_fctudz f64:$A), 5353 (XSCVDPUXDS $A)>; 5354def : Pat<(int_ppc_fctuwz f64:$A), 5355 (XSCVDPUXWS $A)>; 5356 5357def : Pat<(int_ppc_mfmsr), (MFMSR)>; 5358def : Pat<(int_ppc_mftbu), (MFTB 269)>; 5359def : Pat<(i32 (int_ppc_mfspr timm:$SPR)), 5360 (MFSPR $SPR)>; 5361def : Pat<(int_ppc_mtspr timm:$SPR, gprc:$RT), 5362 (MTSPR $SPR, $RT)>; 5363def : Pat<(int_ppc_mtmsr gprc:$RS), 5364 (MTMSR $RS, 0)>; 5365 5366let Predicates = [IsISA2_07] in { 5367 def : Pat<(int_ppc_lharx ForceXForm:$ptr), 5368 (LHARX ForceXForm:$ptr)>; 5369 5370 def : Pat<(int_ppc_sthcx ForceXForm:$dst, gprc:$A), 5371 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5372 def : Pat<(PPCStoreCond ForceXForm:$dst, gprc:$A, 2), 5373 (RLWINM (STHCX gprc:$A, ForceXForm:$dst), 31, 31, 31)>; 5374} 5375def : Pat<(int_ppc_dcbtstt ForceXForm:$dst), 5376 (DCBTST 16, ForceXForm:$dst)>; 5377def : Pat<(int_ppc_dcbtt ForceXForm:$dst), 5378 (DCBT 16, ForceXForm:$dst)>; 5379 5380def : Pat<(int_ppc_stfiw ForceXForm:$dst, f64:$XT), 5381 (STFIWX f64:$XT, ForceXForm:$dst)>; 5382