1//===-- PPCInstrFutureMMA.td - Future Instruction Set ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the instructions introduced for the Future CPU for MMA. 11// 12//===----------------------------------------------------------------------===// 13 14class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 15 string asmstr, list<dag> pattern> 16 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 17 bits<3> AT; 18 bits<5> XAp; 19 bits<5> XBp; 20 bits<1> P; 21 22 let Pattern = pattern; 23 24 let Inst{6-8} = AT{2-0}; 25 let Inst{9-10} = 0; 26 let Inst{11-14} = XAp{3-0}; 27 let Inst{15} = P; 28 let Inst{16-19} = XBp{3-0}; 29 let Inst{20} = 0; 30 let Inst{21-28} = xo; 31 let Inst{29} = XAp{4}; 32 let Inst{30} = XBp{4}; 33 let Inst{31} = 0; 34} 35 36class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 37 string asmstr, list<dag> pattern> 38 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 39 bits<3> AT; 40 bits<5> XBp; 41 bits<2> P; 42 43 let Pattern = pattern; 44 45 let Inst{6-8} = AT{2-0}; 46 let Inst{9-14} = 0; 47 let Inst{15} = P{0}; 48 let Inst{16-19} = XBp{3-0}; 49 let Inst{20} = P{1}; 50 let Inst{21-29} = xo; 51 let Inst{30} = XBp{4}; 52 let Inst{31} = 0; 53} 54 55class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL, 56 string asmstr, list<dag> pattern> 57 : I <opcode, OOL, IOL, asmstr, NoItinerary> { 58 bits<3> AT; 59 bits<3> AB; 60 61 let Pattern = pattern; 62 63 let Inst{6-8} = AT{2-0}; 64 let Inst{9-10} = 0; 65 let Inst{11-15} = o; 66 let Inst{16-18} = AB{2-0}; 67 let Inst{19-20} = 0; 68 let Inst{21-30} = xo; 69 let Inst{31} = 0; 70} 71 72class XX3Form_AT3_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 73 string asmstr, InstrItinClass itin, 74 list<dag> pattern> 75 : I<opcode, OOL, IOL, asmstr, itin> { 76 bits<3> AT; 77 bits<5> XAp; 78 bits<6> XB; 79 80 let Pattern = pattern; 81 82 let Inst{6-8} = AT; 83 let Inst{9-10} = 0; 84 let Inst{11-14} = XAp{3-0}; 85 let Inst{15} = 0; 86 let Inst{16-20} = XB{4-0}; 87 let Inst{21-28} = xo; 88 let Inst{29} = XAp{4}; 89 let Inst{30} = XB{5}; 90 let Inst{31} = 0; 91} 92 93class MMIRR_XX3Form_X8YP4_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 94 string asmstr, InstrItinClass itin, 95 list<dag> pattern> 96 : PI<1, opcode, OOL, IOL, asmstr, itin> { 97 bits<3> AT; 98 bits<5> XAp; 99 bits<6> XB; 100 bits<8> XMSK; 101 bits<4> YMSK; 102 bits<4> PMSK; 103 104 let Pattern = pattern; 105 106 // The prefix. 107 let Inst{6-7} = 3; 108 let Inst{8-11} = 9; 109 let Inst{12-15} = 0; 110 let Inst{16-19} = PMSK; 111 let Inst{20-27} = XMSK; 112 let Inst{28-31} = YMSK; 113 114 // The instruction. 115 let Inst{38-40} = AT; 116 let Inst{41-42} = 0; 117 let Inst{43-46} = XAp{3-0}; 118 let Inst{47} = 0; 119 let Inst{48-52} = XB{4-0}; 120 let Inst{53-60} = xo; 121 let Inst{61} = XAp{4}; 122 let Inst{62} = XB{5}; 123 let Inst{63} = 0; 124} 125 126class MMIRR_XX3Form_X8Y4P2_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, 127 string asmstr, InstrItinClass itin, 128 list<dag> pattern> 129 : PI<1, opcode, OOL, IOL, asmstr, itin> { 130 bits<3> AT; 131 bits<5> XAp; 132 bits<6> XB; 133 bits<8> XMSK; 134 bits<4> YMSK; 135 bits<2> PMSK; 136 137 let Pattern = pattern; 138 139 // The prefix. 140 let Inst{6-7} = 3; 141 let Inst{8-11} = 9; 142 let Inst{12-15} = 0; 143 let Inst{16-17} = PMSK; 144 let Inst{18-19} = 0; 145 let Inst{20-27} = XMSK; 146 let Inst{28-31} = YMSK; 147 148 // The instruction. 149 let Inst{38-40} = AT; 150 let Inst{41-42} = 0; 151 let Inst{43-46} = XAp{3-0}; 152 let Inst{47} = 0; 153 let Inst{48-52} = XB{4-0}; 154 let Inst{53-60} = xo; 155 let Inst{61} = XAp{4}; 156 let Inst{62} = XB{5}; 157 let Inst{63} = 0; 158} 159 160multiclass DMR_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 161 string asmstr> { 162 let Predicates = [MMA, IsISAFuture] in { 163 def NAME : 164 XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x01), (outs dmr:$AT), IOL, 165 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 166 RegConstraint<"@earlyclobber $AT">; 167 def PP : 168 XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 169 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 170 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 171 } 172} 173 174multiclass DMR_UM_M448_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 175 string asmstr> { 176 defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 177 let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 178 def PM#NAME : 179 MMIRR_XX3Form_X8YP4_XAp5B6< 180 opcode, !or(xo, 0x01), (outs dmr:$AT), 181 !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)), 182 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 183 IIC_VecFP, []>, 184 RegConstraint<"@earlyclobber $AT">; 185 def PM#NAME#PP : 186 MMIRR_XX3Form_X8YP4_XAp5B6< 187 opcode, xo, (outs dmr:$AT), 188 !con((ins dmr:$ATi), 189 !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))), 190 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 191 IIC_VecFP, []>, 192 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 193 } 194} 195 196multiclass DMR_BF16_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 197 string asmstr> { 198 let Predicates = [MMA, IsISAFuture] in { 199 def NAME : 200 XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x11), (outs dmr:$AT), IOL, 201 !strconcat(asmbase#" ", asmstr), IIC_VecFP, []>, 202 RegConstraint<"@earlyclobber $AT">; 203 def PP : 204 XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 205 !strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>, 206 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 207 } 208} 209 210multiclass DMR_BF16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 211 string asmstr> { 212 defm NAME : DMR_BF16_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 213 let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 214 def PM#NAME : 215 MMIRR_XX3Form_X8Y4P2_XAp5B6< 216 opcode, !or(xo, 0x11), (outs dmr:$AT), 217 !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 218 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 219 IIC_VecFP, []>, 220 RegConstraint<"@earlyclobber $AT">; 221 def PM#NAME#PP : 222 MMIRR_XX3Form_X8Y4P2_XAp5B6< 223 opcode, xo, (outs dmr:$AT), 224 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 225 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 226 IIC_VecFP, []>, 227 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 228 } 229} 230 231multiclass DMR_F16_UM_M284_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase, 232 string asmstr> { 233 defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>; 234 let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 235 def PM#NAME : 236 MMIRR_XX3Form_X8Y4P2_XAp5B6< 237 opcode, !or(xo, 0x01), (outs dmr:$AT), 238 !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK)), 239 !strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"), 240 IIC_VecFP, []>, 241 RegConstraint<"@earlyclobber $AT">; 242 def PM#NAME#PP : 243 MMIRR_XX3Form_X8Y4P2_XAp5B6< 244 opcode, xo, (outs dmr:$AT), 245 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 246 !strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"), 247 IIC_VecFP, []>, 248 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 249 } 250} 251 252multiclass DMR_NEG_UM_M284_XOXORf939a0<bits<6> opcode, bits<8> xo, dag IOL, 253 string asmbase, string asmstr> { 254 defm NAME : DMR_BF16_UM_M284_XOEO<opcode, xo, IOL, asmbase, asmstr>; 255 let Predicates = [MMA, IsISAFuture] in { 256 def PN : XX3Form_AT3_XAp5B6< 257 opcode, !xor(xo, 0xF9), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 258 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 259 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 260 def NP : XX3Form_AT3_XAp5B6< 261 opcode, !xor(xo, 0x39), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 262 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 263 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 264 def NN : XX3Form_AT3_XAp5B6< 265 opcode, !xor(xo, 0xA0), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 266 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 267 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 268 } 269 let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 270 def PM#NAME#PN : 271 MMIRR_XX3Form_X8Y4P2_XAp5B6< 272 opcode, !xor(xo, 0xF9), (outs dmr:$AT), 273 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 274 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"), 275 IIC_VecFP, []>, 276 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 277 def PM#NAME#NP : 278 MMIRR_XX3Form_X8Y4P2_XAp5B6< 279 opcode, !xor(xo, 0x39), (outs dmr:$AT), 280 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 281 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"), 282 IIC_VecFP, []>, 283 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 284 def PM#NAME#NN : 285 MMIRR_XX3Form_X8Y4P2_XAp5B6< 286 opcode, !xor(xo, 0xA0), (outs dmr:$AT), 287 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 288 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"), 289 IIC_VecFP, []>, 290 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 291 } 292} 293 294multiclass DMR_NEG_UM_M284_XOXORd11188<bits<6> opcode, bits<8> xo, dag IOL, 295 string asmbase, string asmstr> { 296 defm NAME : DMR_F16_UM_M284_XOEO<opcode, xo, IOL, asmbase, asmstr>; 297 let Predicates = [MMA, IsISAFuture] in { 298 def PN : XX3Form_AT3_XAp5B6< 299 opcode, !xor(xo, 0xD1), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 300 !strconcat(asmbase#"pn ", asmstr), IIC_VecFP, []>, 301 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 302 def NP : XX3Form_AT3_XAp5B6< 303 opcode, !xor(xo, 0x11), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 304 !strconcat(asmbase#"np ", asmstr), IIC_VecFP, []>, 305 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 306 def NN : XX3Form_AT3_XAp5B6< 307 opcode, !xor(xo, 0x88), (outs dmr:$AT), !con((ins dmr:$ATi), IOL), 308 !strconcat(asmbase#"nn ", asmstr), IIC_VecFP, []>, 309 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 310 } 311 let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 312 def PM#NAME#PN : 313 MMIRR_XX3Form_X8Y4P2_XAp5B6< 314 opcode, !xor(xo, 0xD1), (outs dmr:$AT), 315 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 316 !strconcat("pm"#asmbase#"pn ", asmstr#", $XMSK, $YMSK, $PMSK"), 317 IIC_VecFP, []>, 318 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 319 def PM#NAME#NP : 320 MMIRR_XX3Form_X8Y4P2_XAp5B6< 321 opcode, !xor(xo, 0x11), (outs dmr:$AT), 322 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 323 !strconcat("pm"#asmbase#"np ", asmstr#", $XMSK, $YMSK, $PMSK"), 324 IIC_VecFP, []>, 325 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 326 def PM#NAME#NN : 327 MMIRR_XX3Form_X8Y4P2_XAp5B6< 328 opcode, !xor(xo, 0x88), (outs dmr:$AT), 329 !con((ins dmr:$ATi), !con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u2imm:$PMSK))), 330 !strconcat("pm"#asmbase#"nn ", asmstr#", $XMSK, $YMSK, $PMSK"), 331 IIC_VecFP, []>, 332 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 333 } 334} 335 336class XForm_AT3_T1_AB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL, 337 string asmstr, list<dag> pattern> 338 : I <opcode, OOL, IOL, asmstr, NoItinerary> { 339 bits<3> AT; 340 bits<3> AB; 341 bits<1> T; 342 343 let Pattern = pattern; 344 345 let Inst{6-8} = AT{2-0}; 346 let Inst{9} = 0; 347 let Inst{10} = T; 348 let Inst{11-15} = o; 349 let Inst{16-18} = AB{2-0}; 350 let Inst{19-20} = 0; 351 let Inst{21-30} = xo; 352 let Inst{31} = 0; 353} 354 355class XForm_ATp2_SR5<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL, 356 string asmstr, list<dag> pattern> 357 : I <opcode, OOL, IOL, asmstr, NoItinerary> { 358 bits<2> ATp; 359 bits<5> SR; 360 361 let Pattern = pattern; 362 363 let Inst{6-7} = ATp{1-0}; 364 let Inst{8-10} = 0; 365 let Inst{11-15} = o; 366 let Inst{16-20} = SR{4-0}; 367 let Inst{21-30} = xo; 368 let Inst{31} = 0; 369} 370 371class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 372 string asmstr, list<dag> pattern> 373 : I<opcode, OOL, IOL, asmstr, NoItinerary> { 374 bits<3> AT; 375 bits<6> XB; 376 bits<2> ID; 377 bits<1> E; 378 bits<2> BL; 379 380 let Pattern = pattern; 381 382 let Inst{6-8} = AT{2-0}; 383 let Inst{9-10} = 0; 384 let Inst{11-12} = ID{1-0}; 385 let Inst{13} = E; 386 let Inst{14-15} = BL{1-0}; 387 let Inst{16-20} = XB{4-0}; 388 let Inst{21-29} = xo; 389 let Inst{30} = XB{5}; 390 let Inst{31} = 0; 391} 392 393let Predicates = [IsISAFuture] in { 394 def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226, 395 (outs vsrprc:$XAp, vsrprc:$XBp), 396 (ins wacc:$AT), 397 "dmxxextfdmr512 $XAp, $XBp, $AT, 0", []> { 398 let P = 0; 399 } 400 401 def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226, 402 (outs vsrprc:$XAp, vsrprc:$XBp), 403 (ins wacc_hi:$AT), 404 "dmxxextfdmr512 $XAp, $XBp, $AT, 1", []> { 405 let P = 1; 406 } 407 408 def DMXXINSTDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT), 409 (ins vsrprc:$XAp, vsrprc:$XBp), 410 "dmxxinstdmr512 $AT, $XAp, $XBp, 0", []> { 411 let P = 0; 412 } 413 414 def DMXXINSTDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT), 415 (ins vsrprc:$XAp, vsrprc:$XBp), 416 "dmxxinstdmr512 $AT, $XAp, $XBp, 1", []> { 417 let P = 1; 418 } 419 420 def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp), 421 (ins dmrrowp:$AT, u2imm:$P), 422 "dmxxextfdmr256 $XBp, $AT, $P", []>; 423 424 def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT), 425 (ins vsrprc:$XBp, u2imm:$P), 426 "dmxxinstdmr256 $AT, $XBp, $P", []>; 427 428 def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB), 429 "dmmr $AT, $AB", 430 [(set v1024i1:$AT, (int_ppc_mma_dmmr v1024i1:$AB))]>; 431 432 def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB), 433 "dmxor $AT, $AB", 434 [(set v1024i1:$AT, (int_ppc_mma_dmxor v1024i1:$ATi, v1024i1:$AB))]>, 435 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 436 437 def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins), 438 "dmsetdmrz $AT", NoItinerary, 439 [(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>; 440} 441 442// MMA+ accumulating/non-accumulating instructions. 443 444// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP 445defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB), 446 "dmxvi8gerx4", "$AT, $XAp, $XB">; 447 448let Predicates = [MMA, IsISAFuture] in { 449 def DMXVI8GERX4SPP : 450 XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB), 451 "dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>, 452 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 453} 454 455let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 456 def PMDMXVI8GERX4SPP : 457 MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT), 458 (ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK, 459 u4imm:$YMSK, u4imm:$PMSK), 460 "pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK", 461 IIC_VecGeneral, []>, 462 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 463} 464 465// DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP, DMXVBF16GERX2NN 466// PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN, PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN 467defm DMXVBF16GERX2 : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB), 468 "dmxvbf16gerx2", "$AT, $XAp, $XB">; 469 470// DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP, DMXVF16GERX2NN 471// PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN, PMDMXVF16GERX2NP, PMDMXVF16GERX2NN 472defm DMXVF16GERX2 : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB), 473 "dmxvf16gerx2", "$AT, $XAp, $XB">; 474 475// DMF cryptography [support] Instructions 476let Predicates = [IsISAFuture] in { 477 def DMSHA2HASH : 478 XForm_AT3_T1_AB3<31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T), 479 "dmsha2hash $AT, $AB, $T", 480 [(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi, v1024i1:$AB, timm:$T))]>, 481 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 482 483 def DMSHA3HASH : 484 XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp), (ins dmrp:$ATpi , u5imm:$SR), 485 "dmsha3hash $ATp, $SR", 486 [(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>, 487 RegConstraint<"$ATpi = $ATp">, NoEncode<"$ATpi">; 488 489 def DMXXSHAPAD : 490 XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT), 491 (ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E, u2imm:$BL), 492 "dmxxshapad $AT, $XB, $ID, $E, $BL", []>, 493 RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">; 494} 495 496// MMA+ Intrinsics 497let Predicates = [MMA, IsISAFuture] in { 498 def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)), 499 (DMXVI8GERX4 $XAp, RCCp.BToVSRC)>; 500 def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 501 (DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>; 502 503 def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 504 (DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>; 505 506 def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)), 507 (DMXVBF16GERX2 $XAp, RCCp.BToVSRC)>; 508 509 def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 510 (DMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>; 511 512 def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 513 (DMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>; 514 515 def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 516 (DMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>; 517 518 def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 519 (DMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>; 520 521 def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)), 522 (DMXVF16GERX2 $XAp, RCCp.BToVSRC)>; 523 524 def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 525 (DMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>; 526 527 def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 528 (DMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>; 529 530 def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 531 (DMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>; 532 533 def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)), 534 (DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>; 535} 536 537let Predicates = [MMA, PrefixInstrs, IsISAFuture] in { 538 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK, 539 Msk4Imm:$YMSK, Msk4Imm:$PMSK)), 540 (PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 541 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 542 543 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 544 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 545 Msk4Imm:$PMSK)), 546 (PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 547 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 548 549 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 550 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 551 Msk4Imm:$PMSK)), 552 (PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 553 Msk4Imm:$YMSK, Msk4Imm:$PMSK)>; 554 555 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK, 556 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 557 (PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 558 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 559 560 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 561 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 562 Msk2Imm:$PMSK)), 563 (PMDMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 564 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 565 566 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 567 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 568 Msk2Imm:$PMSK)), 569 (PMDMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 570 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 571 572 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 573 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 574 Msk2Imm:$PMSK)), 575 (PMDMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 576 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 577 578 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 579 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 580 Msk2Imm:$PMSK)), 581 (PMDMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 582 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 583 584 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK, 585 Msk4Imm:$YMSK, Msk2Imm:$PMSK)), 586 (PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 587 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 588 589 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 590 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 591 Msk2Imm:$PMSK)), 592 (PMDMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 593 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 594 595 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 596 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 597 Msk2Imm:$PMSK)), 598 (PMDMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 599 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 600 601 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 602 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 603 Msk2Imm:$PMSK)), 604 (PMDMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 605 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 606 607 def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB, 608 Msk8Imm:$XMSK, Msk4Imm:$YMSK, 609 Msk2Imm:$PMSK)), 610 (PMDMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, 611 Msk4Imm:$YMSK, Msk2Imm:$PMSK)>; 612} 613 614// Cryptography Intrinsic 615let Predicates = [IsISAFuture] in { 616 def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID, 617 timm:$E, timm:$BL)), (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>; 618} 619 620// MMA+ Instruction aliases 621let Predicates = [IsISAFuture] in { 622 def : InstAlias<"dmsha256hash $AT, $AB", 623 (DMSHA2HASH dmr:$AT, dmr:$AB, 0)>; 624 625 def : InstAlias<"dmsha512hash $AT, $AB", 626 (DMSHA2HASH dmr:$AT, dmr:$AB, 1)>; 627 628 def : InstAlias<"dmsha3dw $ATp", 629 (DMSHA3HASH dmrp:$ATp, 0)>; 630 631 def : InstAlias<"dmcryshash $ATp", 632 (DMSHA3HASH dmrp:$ATp, 12)>; 633 634 def : InstAlias<"dmxxsha3512pad $AT, $XB, $E", 635 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 0)>; 636 637 def : InstAlias<"dmxxsha3384pad $AT, $XB, $E", 638 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 1)>; 639 640 def : InstAlias<"dmxxsha3256pad $AT, $XB, $E", 641 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 2)>; 642 643 def : InstAlias<"dmxxsha3224pad $AT, $XB, $E", 644 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 0, u1imm:$E, 3)>; 645 646 def : InstAlias<"dmxxshake256pad $AT, $XB, $E", 647 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 0)>; 648 649 def : InstAlias<"dmxxshake128pad $AT, $XB, $E", 650 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 1, u1imm:$E, 1)>; 651 652 def : InstAlias<"dmxxsha384512pad $AT, $XB", 653 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 2, 0, 0)>; 654 655 def : InstAlias<"dmxxsha224256pad $AT, $XB", 656 (DMXXSHAPAD dmr:$AT, vsrc:$XB, 3, 0, 0)>; 657} 658