1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28/* 29 * Eversholt rules for Oberon ASICs 30 */ 31 32#pragma dictionary "SUN4U" 33 34#define HB_FIT 1000 35 36/* 37 * Test for primary or secondary ereports 38 */ 39#define IS_PRIMARY (payloadprop("primary")) 40#define IS_SECONDARY (! payloadprop("primary")) 41 42event error.io.oberon.pec.secondary@hostbridge/pciexrc; 43event error.io.oberon.pec.fabric_error@hostbridge/pciexrc; 44 45/* 46 * Ereports derived from the 47 * UBC Status Clear Register 48 * 49 * dmarduea-channel DMA read uncorrectable error (UE) in leaf A 50 * dmawtuea DMA write UE in leaf A 51 * memrdaxa Memory read invalid address error in leaf A 52 * memwtaxa Memory write invalid address error in leaf A 53 * dmardueb-channel DMA read uncorrectable error (UE) in leaf B 54 * dmawtueb DMA write UE in leaf B 55 * memrdaxb Memory read invalid address error in leaf B 56 * memwtaxb Memory write invalid address error in leaf B 57 * piowtue-channel PIO write UE 58 * piowbeue-channel PIO write byte enable UE 59 * piorbeue-channel PIO read byte enable UE 60 */ 61event ereport.io.oberon.ubc.dmarduea-channel@hostbridge/pciexrc{within(5s)}; 62event ereport.io.oberon.ubc.dmawtuea@hostbridge/pciexrc{within(5s)}; 63event ereport.io.oberon.ubc.memrdaxa@hostbridge/pciexrc{within(5s)}; 64event ereport.io.oberon.ubc.memwtaxa@hostbridge/pciexrc{within(5s)}; 65event ereport.io.oberon.ubc.dmardueb-channel@hostbridge/pciexrc{within(5s)}; 66event ereport.io.oberon.ubc.dmawtueb@hostbridge/pciexrc{within(5s)}; 67event ereport.io.oberon.ubc.memrdaxb@hostbridge/pciexrc{within(5s)}; 68event ereport.io.oberon.ubc.memwtaxb@hostbridge/pciexrc{within(5s)}; 69event ereport.io.oberon.ubc.piowtue-channel@hostbridge/pciexrc{within(5s)}; 70event ereport.io.oberon.ubc.piowbeue-channel@hostbridge/pciexrc{within(5s)}; 71event ereport.io.oberon.ubc.piorbeue-channel@hostbridge/pciexrc{within(5s)}; 72 73/* 74 * tlueitmo TLU Egress Issue Timeout 75 */ 76event ereport.io.oberon.pec.tlueitmo@hostbridge/pciexrc{within(5s)}; 77 78/* 79 * TLU Uncorrectable and Correctable ereports 80 * 81 * ecrc End-to-end CRC error 82 */ 83event ereport.io.oberon.pec.ecrc@hostbridge/pciexrc{within(5s)}; 84 85/* 86 * A faulty Oberon may cause; 87 * 88 * - DMA write internal RAM UE: dmawtuea, dmawtueb 89 * - TLU ECRC 90 * 91 * Errors marked with * may cause PCI-E abort 92 */ 93 94fru hostbridge; 95asru hostbridge; 96event fault.io.oberon@hostbridge, 97 FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge; 98prop fault.io.oberon@hostbridge (0)-> 99 ereport.io.oberon.ubc.dmawtuea@hostbridge/pciexrc, 100 ereport.io.oberon.ubc.dmawtueb@hostbridge/pciexrc; 101event fault.io.oberon@hostbridge/pciexrc, 102 FITrate=HB_FIT, FRU=hostbridge, ASRU=hostbridge; 103prop fault.io.oberon@hostbridge/pciexrc (0)-> 104 ereport.io.oberon.pec.ecrc@hostbridge/pciexrc { IS_PRIMARY }; 105 106/* 107 * A faulty PX nexus driver can cause 108 * - Jbus unmapped error 109 * - mmu invalid, out of range, protection etc. all except data parity 110 * - invalid pio r/w 111 * - unsolicited read or interrupt return 112 * - msg received to unenabled queue 113 */ 114 115#define SW_FIT 5000 /* No real fit rate, SW */ 116event fault.io.fire.hb.sw-config@hostbridge/pciexrc, retire=0, response=0, 117 FITrate=SW_FIT; 118 119prop fault.io.fire.hb.sw-config@hostbridge/pciexrc (0)-> 120 ereport.io.oberon.ubc.memrdaxa@hostbridge/pciexrc, 121 ereport.io.oberon.ubc.memrdaxb@hostbridge/pciexrc, 122 ereport.io.oberon.ubc.memwtaxa@hostbridge/pciexrc, 123 ereport.io.oberon.ubc.memwtaxb@hostbridge/pciexrc; 124 125/* 126 * Secondary errors of the ereport that the device is at fault. 127 * Undiagnosed the secondary errors since the payload is invalid. 128 */ 129prop error.io.oberon.pec.secondary@hostbridge/pciexrc (0) -> 130 ereport.io.oberon.pec.ecrc@hostbridge/pciexrc{ IS_SECONDARY }; 131 132/* 133 * For logging purpose only. 134 * The px nexus driver generates equivalent pciex ereports for the 135 * common pciex rules to diagnose. 136 */ 137prop error.io.oberon.pec.fabric_error@hostbridge/pciexrc(0) -> 138 ereport.io.oberon.pec.ecrc@hostbridge/pciexrc; 139 140event ereport.io.oberon.nodiag@hostbridge; 141 142/* 143 * Upset used to hide ereports that are not currently diagnosed. 144 */ 145engine serd.io.oberon.nodiag@hostbridge, 146 N=1000, T=1s, method=persistent, 147 trip=ereport.io.oberon.nodiag@hostbridge; 148 149event upset.io.oberon.nodiag@hostbridge, 150 engine=serd.io.oberon.nodiag@hostbridge; 151 152prop upset.io.oberon.nodiag@hostbridge (0)-> 153 ereport.io.oberon.ubc.dmarduea-channel@hostbridge/pciexrc, 154 ereport.io.oberon.ubc.dmardueb-channel@hostbridge/pciexrc, 155 ereport.io.oberon.ubc.piowtue-channel@hostbridge/pciexrc, 156 ereport.io.oberon.ubc.piowbeue-channel@hostbridge/pciexrc, 157 ereport.io.oberon.ubc.piorbeue-channel@hostbridge/pciexrc, 158 ereport.io.oberon.pec.tlueitmo@hostbridge/pciexrc, 159 error.io.oberon.pec.fabric_error@hostbridge/pciexrc, 160 ereport.io.oberon.nodiag@hostbridge; 161