1 //===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Mips implementation of the TargetInstrInfo class. 10 // 11 // FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in 12 // order for MipsLongBranch pass to work correctly when the code has inline 13 // assembly. The returned value doesn't have to be the asm instruction's exact 14 // size in bytes; MipsLongBranch only expects it to be the correct upper bound. 15 //===----------------------------------------------------------------------===// 16 17 #ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 18 #define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 19 20 #include "MCTargetDesc/MipsMCTargetDesc.h" 21 #include "Mips.h" 22 #include "MipsRegisterInfo.h" 23 #include "llvm/ADT/ArrayRef.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineMemOperand.h" 27 #include "llvm/CodeGen/TargetInstrInfo.h" 28 #include <cstdint> 29 30 #define GET_INSTRINFO_HEADER 31 #include "MipsGenInstrInfo.inc" 32 33 namespace llvm { 34 35 class MachineInstr; 36 class MachineOperand; 37 class MipsSubtarget; 38 class TargetRegisterClass; 39 class TargetRegisterInfo; 40 41 class MipsInstrInfo : public MipsGenInstrInfo { 42 virtual void anchor(); 43 44 protected: 45 const MipsSubtarget &Subtarget; 46 unsigned UncondBrOpc; 47 48 public: 49 enum BranchType { 50 BT_None, // Couldn't analyze branch. 51 BT_NoBranch, // No branches found. 52 BT_Uncond, // One unconditional branch. 53 BT_Cond, // One conditional branch. 54 BT_CondUncond, // A conditional branch followed by an unconditional branch. 55 BT_Indirect // One indirct branch. 56 }; 57 58 explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); 59 60 MCInst getNop() const override; 61 62 static const MipsInstrInfo *create(MipsSubtarget &STI); 63 64 /// Branch Analysis 65 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 66 MachineBasicBlock *&FBB, 67 SmallVectorImpl<MachineOperand> &Cond, 68 bool AllowModify) const override; 69 70 unsigned removeBranch(MachineBasicBlock &MBB, 71 int *BytesRemoved = nullptr) const override; 72 73 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 74 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 75 const DebugLoc &DL, 76 int *BytesAdded = nullptr) const override; 77 78 bool 79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 80 81 BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 82 MachineBasicBlock *&FBB, 83 SmallVectorImpl<MachineOperand> &Cond, 84 bool AllowModify, 85 SmallVectorImpl<MachineInstr *> &BranchInstrs) const; 86 87 /// Determine the opcode of a non-delay slot form for a branch if one exists. 88 unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; 89 90 /// Determine if the branch target is in range. 91 bool isBranchOffsetInRange(unsigned BranchOpc, 92 int64_t BrOffset) const override; 93 94 bool SafeAfterMflo(const MachineInstr &MI) const; 95 96 /// Predicate to determine if an instruction can go in a forbidden slot. 97 bool SafeInForbiddenSlot(const MachineInstr &MI) const; 98 99 /// Predicate to determine if an instruction can go in an FPU delay slot. 100 bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot, 101 const MachineInstr &FPUMI) const; 102 103 /// Predicate to determine if an instruction can go in a load delay slot. 104 bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot, 105 const MachineInstr &LoadMI) const; 106 107 bool IsMfloOrMfhi(const MachineInstr &MI) const; 108 109 /// Predicate to determine if an instruction has a forbidden slot. 110 bool HasForbiddenSlot(const MachineInstr &MI) const; 111 112 /// Predicate to determine if an instruction has an FPU delay slot. 113 bool HasFPUDelaySlot(const MachineInstr &MI) const; 114 115 /// Predicate to determine if an instruction has a load delay slot. 116 bool HasLoadDelaySlot(const MachineInstr &MI) const; 117 118 bool isAsCheapAsAMove(const MachineInstr &MI) const override; 119 120 /// Insert nop instruction when hazard condition is found 121 void insertNoop(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MI) const override; 123 124 /// Insert an ISA appropriate `nop`. 125 // FIXME: Add support for MIPS16e. 126 MachineInstrBuilder insertNop(MachineBasicBlock &MBB, 127 MachineBasicBlock::iterator MI, 128 DebugLoc DL) const; 129 130 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 131 /// such, whenever a client has an instance of instruction info, it should 132 /// always be able to get register info as well (through this method). 133 virtual const MipsRegisterInfo &getRegisterInfo() const = 0; 134 135 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; 136 isBranchWithImm(unsigned Opc)137 virtual bool isBranchWithImm(unsigned Opc) const { 138 return false; 139 } 140 141 /// Return the number of bytes of code the specified instruction may be. 142 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 143 144 void storeRegToStackSlot( 145 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, 146 bool isKill, int FrameIndex, const TargetRegisterClass *RC, 147 const TargetRegisterInfo *TRI, Register VReg, 148 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { 149 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0, Flags); 150 } 151 152 void loadRegFromStackSlot( 153 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 154 Register DestReg, int FrameIndex, const TargetRegisterClass *RC, 155 const TargetRegisterInfo *TRI, Register VReg, 156 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override { 157 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0, Flags); 158 } 159 160 virtual void 161 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 162 Register SrcReg, bool isKill, int FrameIndex, 163 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 164 int64_t Offset, 165 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; 166 167 virtual void loadRegFromStack( 168 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, 169 int FrameIndex, const TargetRegisterClass *RC, 170 const TargetRegisterInfo *TRI, int64_t Offset, 171 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const = 0; 172 173 virtual void adjustStackPtr(unsigned SP, int64_t Amount, 174 MachineBasicBlock &MBB, 175 MachineBasicBlock::iterator I) const = 0; 176 177 /// Create an instruction which has the same operands and memory operands 178 /// as MI but has a new opcode. 179 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc, 180 MachineBasicBlock::iterator I) const; 181 182 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 183 unsigned &SrcOpIdx2) const override; 184 185 /// Perform target specific instruction verification. 186 bool verifyInstruction(const MachineInstr &MI, 187 StringRef &ErrInfo) const override; 188 189 std::pair<unsigned, unsigned> 190 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 191 192 ArrayRef<std::pair<unsigned, const char *>> 193 getSerializableDirectMachineOperandTargetFlags() const override; 194 195 std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI, 196 Register Reg) const override; 197 198 std::optional<ParamLoadedValue> 199 describeLoadedValue(const MachineInstr &MI, Register Reg) const override; 200 201 protected: 202 bool isZeroImm(const MachineOperand &op) const; 203 204 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI, 205 MachineMemOperand::Flags Flags) const; 206 207 private: 208 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0; 209 210 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc, 211 MachineBasicBlock *&BB, 212 SmallVectorImpl<MachineOperand> &Cond) const; 213 214 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 215 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const; 216 }; 217 218 /// Create MipsInstrInfo objects. 219 const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); 220 const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); 221 222 namespace Mips { 223 // Mask assignments for floating-point. 224 enum FClassMask { 225 FClassMaskSignalingNaN = 1 << 0, 226 FClassMaskQuietNaN = 1 << 1, 227 FClassMaskNegativeInfinity = 1 << 2, 228 FClassMaskNegativeNormal = 1 << 3, 229 FClassMaskNegativeSubnormal = 1 << 4, 230 FClassMaskNegativeZero = 1 << 5, 231 FClassMaskPositiveInfinity = 1 << 6, 232 FClassMaskPositiveNormal = 1 << 7, 233 FClassMaskPositiveSubnormal = 1 << 8, 234 FClassMaskPositiveZero = 1 << 9 235 }; 236 237 } // namespace Mips 238 239 } // end namespace llvm 240 241 #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H 242