1 //===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the MSP430 implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MSP430RegisterInfo.h"
14 #include "MSP430TargetMachine.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/IR/Function.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22
23 using namespace llvm;
24
25 #define DEBUG_TYPE "msp430-reg-info"
26
27 #define GET_REGINFO_TARGET_DESC
28 #include "MSP430GenRegisterInfo.inc"
29
30 // FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo()31 MSP430RegisterInfo::MSP430RegisterInfo()
32 : MSP430GenRegisterInfo(MSP430::PC) {}
33
34 const MCPhysReg*
getCalleeSavedRegs(const MachineFunction * MF) const35 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36 const MSP430FrameLowering *TFI = getFrameLowering(*MF);
37 const Function* F = &MF->getFunction();
38 static const MCPhysReg CalleeSavedRegs[] = {
39 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
40 MSP430::R8, MSP430::R9, MSP430::R10,
41 0
42 };
43 static const MCPhysReg CalleeSavedRegsFP[] = {
44 MSP430::R5, MSP430::R6, MSP430::R7,
45 MSP430::R8, MSP430::R9, MSP430::R10,
46 0
47 };
48 static const MCPhysReg CalleeSavedRegsIntr[] = {
49 MSP430::R4, MSP430::R5, MSP430::R6, MSP430::R7,
50 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
51 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
52 0
53 };
54 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
55 MSP430::R5, MSP430::R6, MSP430::R7,
56 MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
57 MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15,
58 0
59 };
60
61 if (TFI->hasFP(*MF))
62 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
63 CalleeSavedRegsIntrFP : CalleeSavedRegsFP);
64 else
65 return (F->getCallingConv() == CallingConv::MSP430_INTR ?
66 CalleeSavedRegsIntr : CalleeSavedRegs);
67
68 }
69
getReservedRegs(const MachineFunction & MF) const70 BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
71 BitVector Reserved(getNumRegs());
72 const MSP430FrameLowering *TFI = getFrameLowering(MF);
73
74 // Mark 4 special registers with subregisters as reserved.
75 Reserved.set(MSP430::PCB);
76 Reserved.set(MSP430::SPB);
77 Reserved.set(MSP430::SRB);
78 Reserved.set(MSP430::CGB);
79 Reserved.set(MSP430::PC);
80 Reserved.set(MSP430::SP);
81 Reserved.set(MSP430::SR);
82 Reserved.set(MSP430::CG);
83
84 // Mark frame pointer as reserved if needed.
85 if (TFI->hasFP(MF)) {
86 Reserved.set(MSP430::R4B);
87 Reserved.set(MSP430::R4);
88 }
89
90 return Reserved;
91 }
92
93 const TargetRegisterClass *
getPointerRegClass(const MachineFunction & MF,unsigned Kind) const94 MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
95 const {
96 return &MSP430::GR16RegClass;
97 }
98
99 bool
eliminateFrameIndex(MachineBasicBlock::iterator II,int SPAdj,unsigned FIOperandNum,RegScavenger * RS) const100 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
101 int SPAdj, unsigned FIOperandNum,
102 RegScavenger *RS) const {
103 assert(SPAdj == 0 && "Unexpected");
104
105 MachineInstr &MI = *II;
106 MachineBasicBlock &MBB = *MI.getParent();
107 MachineFunction &MF = *MBB.getParent();
108 const MSP430FrameLowering *TFI = getFrameLowering(MF);
109 DebugLoc dl = MI.getDebugLoc();
110 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
111
112 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP);
113 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex);
114
115 // Skip the saved PC
116 Offset += 2;
117
118 if (!TFI->hasFP(MF))
119 Offset += MF.getFrameInfo().getStackSize();
120 else
121 Offset += 2; // Skip the saved FP
122
123 // Fold imm into offset
124 Offset += MI.getOperand(FIOperandNum + 1).getImm();
125
126 if (MI.getOpcode() == MSP430::ADDframe) {
127 // This is actually "load effective address" of the stack slot
128 // instruction. We have only two-address instructions, thus we need to
129 // expand it into mov + add
130 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
131
132 MI.setDesc(TII.get(MSP430::MOV16rr));
133 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
134
135 // Remove the now unused Offset operand.
136 MI.removeOperand(FIOperandNum + 1);
137
138 if (Offset == 0)
139 return false;
140
141 // We need to materialize the offset via add instruction.
142 Register DstReg = MI.getOperand(0).getReg();
143 if (Offset < 0)
144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
145 .addReg(DstReg).addImm(-Offset);
146 else
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
148 .addReg(DstReg).addImm(Offset);
149
150 return false;
151 }
152
153 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
155 return false;
156 }
157
getFrameRegister(const MachineFunction & MF) const158 Register MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
159 const MSP430FrameLowering *TFI = getFrameLowering(MF);
160 return TFI->hasFP(MF) ? MSP430::R4 : MSP430::SP;
161 }
162