1//===- IntrinsicsHexagon.td - Defines Hexagon intrinsics ---*- tablegen -*-===// 2// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 3// See https://llvm.org/LICENSE.txt for license information. 4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 5// 6//===----------------------------------------------------------------------===// 7// 8// This file defines all of the Hexagon-specific intrinsics. 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Definitions for all Hexagon intrinsics. 14// 15// All Hexagon intrinsics start with "llvm.hexagon.". 16let TargetPrefix = "hexagon" in { 17 /// Hexagon_Intrinsic - Base class for the majority of Hexagon intrinsics. 18 class Hexagon_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types, 19 list<LLVMType> param_types, 20 list<IntrinsicProperty> properties> 21 : ClangBuiltin<!strconcat("__builtin_", GCCIntSuffix)>, 22 DefaultAttrsIntrinsic<ret_types, param_types, properties>; 23 24 /// Hexagon_NonGCC_Intrinsic - Base class for bitcode convertible Hexagon 25 /// intrinsics. 26 class Hexagon_NonGCC_Intrinsic<list<LLVMType> ret_types, 27 list<LLVMType> param_types, 28 list<IntrinsicProperty> properties> 29 : DefaultAttrsIntrinsic<ret_types, param_types, properties>; 30} 31 32class Hexagon_mem_memmemsi_Intrinsic<string GCCIntSuffix> 33 : Hexagon_Intrinsic<GCCIntSuffix, 34 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 35 llvm_i32_ty], 36 [IntrArgMemOnly]>; 37 38class Hexagon_mem_memsisi_Intrinsic<string GCCIntSuffix> 39 : Hexagon_Intrinsic<GCCIntSuffix, 40 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 41 llvm_i32_ty], 42 [IntrWriteMem]>; 43 44class Hexagon_mem_memdisi_Intrinsic<string GCCIntSuffix> 45 : Hexagon_Intrinsic<GCCIntSuffix, 46 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 47 llvm_i32_ty], 48 [IntrWriteMem]>; 49 50class Hexagon_mem_memmemsisi_Intrinsic<string GCCIntSuffix> 51 : Hexagon_Intrinsic<GCCIntSuffix, 52 [llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty, 53 llvm_i32_ty, llvm_i32_ty], 54 [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>; 55 56class Hexagon_mem_memsisisi_Intrinsic<string GCCIntSuffix> 57 : Hexagon_Intrinsic<GCCIntSuffix, 58 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, 59 llvm_i32_ty, llvm_i32_ty], 60 [IntrWriteMem, ImmArg<ArgIndex<3>>]>; 61 62class Hexagon_mem_memdisisi_Intrinsic<string GCCIntSuffix> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty, 65 llvm_i32_ty, llvm_i32_ty], 66 [IntrWriteMem, ImmArg<ArgIndex<3>>]>; 67 68// 69// BUILTIN_INFO_NONCONST(circ_ldd,PTR_ftype_PTRPTRSISI,4) 70// 71def int_hexagon_circ_ldd : 72Hexagon_mem_memmemsisi_Intrinsic<"circ_ldd">; 73// 74// BUILTIN_INFO_NONCONST(circ_ldw,PTR_ftype_PTRPTRSISI,4) 75// 76def int_hexagon_circ_ldw : 77Hexagon_mem_memmemsisi_Intrinsic<"circ_ldw">; 78// 79// BUILTIN_INFO_NONCONST(circ_ldh,PTR_ftype_PTRPTRSISI,4) 80// 81def int_hexagon_circ_ldh : 82Hexagon_mem_memmemsisi_Intrinsic<"circ_ldh">; 83// 84// BUILTIN_INFO_NONCONST(circ_lduh,PTR_ftype_PTRPTRSISI,4) 85// 86def int_hexagon_circ_lduh : 87Hexagon_mem_memmemsisi_Intrinsic<"circ_lduh">; 88// 89// BUILTIN_INFO_NONCONST(circ_ldb,PTR_ftype_PTRPTRSISI,4) 90// 91def int_hexagon_circ_ldb : 92Hexagon_mem_memmemsisi_Intrinsic<"circ_ldb">; 93// 94// BUILTIN_INFO_NONCONST(circ_ldub,PTR_ftype_PTRPTRSISI,4) 95// 96def int_hexagon_circ_ldub : 97Hexagon_mem_memmemsisi_Intrinsic<"circ_ldub">; 98 99// 100// BUILTIN_INFO_NONCONST(circ_std,PTR_ftype_PTRDISISI,4) 101// 102def int_hexagon_circ_std : 103Hexagon_mem_memdisisi_Intrinsic<"circ_std">; 104// 105// BUILTIN_INFO_NONCONST(circ_stw,PTR_ftype_PTRSISISI,4) 106// 107def int_hexagon_circ_stw : 108Hexagon_mem_memsisisi_Intrinsic<"circ_stw">; 109// 110// BUILTIN_INFO_NONCONST(circ_sth,PTR_ftype_PTRSISISI,4) 111// 112def int_hexagon_circ_sth : 113Hexagon_mem_memsisisi_Intrinsic<"circ_sth">; 114// 115// BUILTIN_INFO_NONCONST(circ_sthhi,PTR_ftype_PTRSISISI,4) 116// 117def int_hexagon_circ_sthhi : 118Hexagon_mem_memsisisi_Intrinsic<"circ_sthhi">; 119// 120// BUILTIN_INFO_NONCONST(circ_stb,PTR_ftype_PTRSISISI,4) 121// 122def int_hexagon_circ_stb : 123Hexagon_mem_memsisisi_Intrinsic<"circ_stb">; 124 125def int_hexagon_prefetch : 126Hexagon_Intrinsic<"HEXAGON_prefetch", [], [llvm_ptr_ty], []>; 127 128// Mark locked loads as read/write to prevent any accidental reordering. 129// These don't use Hexagon_Intrinsic, because they are not nosync, and as such 130// cannot use default attributes. 131let TargetPrefix = "hexagon" in { 132 def int_hexagon_L2_loadw_locked : 133 ClangBuiltin<"__builtin_HEXAGON_L2_loadw_locked">, 134 Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], 135 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 136 def int_hexagon_L4_loadd_locked : 137 ClangBuiltin<"__builtin__HEXAGON_L4_loadd_locked">, 138 Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], 139 [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 140 141 def int_hexagon_S2_storew_locked : 142 ClangBuiltin<"__builtin_HEXAGON_S2_storew_locked">, 143 Intrinsic<[llvm_i32_ty], 144 [llvm_ptr_ty, llvm_i32_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 145 def int_hexagon_S4_stored_locked : 146 ClangBuiltin<"__builtin_HEXAGON_S4_stored_locked">, 147 Intrinsic<[llvm_i32_ty], 148 [llvm_ptr_ty, llvm_i64_ty], [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>; 149} 150 151def int_hexagon_vmemcpy : Hexagon_Intrinsic<"hexagon_vmemcpy", 152 [], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], 153 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, NoCapture<ArgIndex<1>>, WriteOnly<ArgIndex<0>>, ReadOnly<ArgIndex<1>>]>; 154 155def int_hexagon_vmemset : Hexagon_Intrinsic<"hexagon_vmemset", 156 [], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], 157 [IntrArgMemOnly, NoCapture<ArgIndex<0>>, WriteOnly<ArgIndex<0>>]>; 158 159multiclass Hexagon_custom_circ_ld_Intrinsic<LLVMType ElTy> { 160 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 161 [ElTy, llvm_ptr_ty], 162 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], 163 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 164 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 165 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty], 166 [IntrArgMemOnly, NoCapture<ArgIndex<2>>]>; 167} 168 169defm int_hexagon_L2_loadrub : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 170defm int_hexagon_L2_loadrb : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 171defm int_hexagon_L2_loadruh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 172defm int_hexagon_L2_loadrh : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 173defm int_hexagon_L2_loadri : Hexagon_custom_circ_ld_Intrinsic<llvm_i32_ty>; 174defm int_hexagon_L2_loadrd : Hexagon_custom_circ_ld_Intrinsic<llvm_i64_ty>; 175 176multiclass Hexagon_custom_circ_st_Intrinsic<LLVMType ElTy> { 177 def NAME#_pci : Hexagon_NonGCC_Intrinsic< 178 [llvm_ptr_ty], 179 [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 180 [IntrArgMemOnly, NoCapture<ArgIndex<4>>]>; 181 def NAME#_pcr : Hexagon_NonGCC_Intrinsic< 182 [llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty, ElTy, llvm_ptr_ty], 183 [IntrArgMemOnly, NoCapture<ArgIndex<3>>]>; 184} 185 186defm int_hexagon_S2_storerb : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 187defm int_hexagon_S2_storerh : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 188defm int_hexagon_S2_storerf : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 189defm int_hexagon_S2_storeri : Hexagon_custom_circ_st_Intrinsic<llvm_i32_ty>; 190defm int_hexagon_S2_storerd : Hexagon_custom_circ_st_Intrinsic<llvm_i64_ty>; 191 192// The front-end emits the intrinsic call with only two arguments. The third 193// argument from the builtin is already used by front-end to write to memory 194// by generating a store. 195class Hexagon_custom_brev_ld_Intrinsic<LLVMType ElTy> 196 : Hexagon_NonGCC_Intrinsic< 197 [ElTy, llvm_ptr_ty], [llvm_ptr_ty, llvm_i32_ty], 198 [IntrReadMem]>; 199 200def int_hexagon_L2_loadrub_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 201def int_hexagon_L2_loadrb_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 202def int_hexagon_L2_loadruh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 203def int_hexagon_L2_loadrh_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 204def int_hexagon_L2_loadri_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i32_ty>; 205def int_hexagon_L2_loadrd_pbr : Hexagon_custom_brev_ld_Intrinsic<llvm_i64_ty>; 206 207def int_hexagon_S2_storerb_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stb">; 208def int_hexagon_S2_storerh_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sth">; 209def int_hexagon_S2_storerf_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_sthhi">; 210def int_hexagon_S2_storeri_pbr : Hexagon_mem_memsisi_Intrinsic<"brev_stw">; 211def int_hexagon_S2_storerd_pbr : Hexagon_mem_memdisi_Intrinsic<"brev_std">; 212 213// tag : V6_vrmpybub_rtt 214class Hexagon_v32i32_v16i32i64_rtt_Intrinsic<string GCCIntSuffix> 215 : Hexagon_Intrinsic<GCCIntSuffix, 216 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 217 [IntrNoMem]>; 218 219// tag : V6_vrmpybub_rtt_128B 220class Hexagon_v64i32_v32i32i64_rtt_Intrinsic<string GCCIntSuffix> 221 : Hexagon_Intrinsic<GCCIntSuffix, 222 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 223 [IntrNoMem]>; 224 225// tag : V6_vrmpybub_rtt_acc 226class Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<string GCCIntSuffix> 227 : Hexagon_Intrinsic<GCCIntSuffix, 228 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i64_ty], 229 [IntrNoMem]>; 230 231// tag : V6_vrmpybub_rtt_acc_128B 232class Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<string GCCIntSuffix> 233 : Hexagon_Intrinsic<GCCIntSuffix, 234 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i64_ty], 235 [IntrNoMem]>; 236 237def int_hexagon_V6_vrmpybub_rtt : 238Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt">; 239 240def int_hexagon_V6_vrmpybub_rtt_128B : 241Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_128B">; 242 243def int_hexagon_V6_vrmpybub_rtt_acc : 244Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc">; 245 246def int_hexagon_V6_vrmpybub_rtt_acc_128B : 247Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpybub_rtt_acc_128B">; 248 249def int_hexagon_V6_vrmpyub_rtt : 250Hexagon_v32i32_v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt">; 251 252def int_hexagon_V6_vrmpyub_rtt_128B : 253Hexagon_v64i32_v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_128B">; 254 255def int_hexagon_V6_vrmpyub_rtt_acc : 256Hexagon_v32i32_v32i32v16i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc">; 257 258def int_hexagon_V6_vrmpyub_rtt_acc_128B : 259Hexagon_v64i32_v64i32v32i32i64_rtt_Intrinsic<"HEXAGON_V6_vrmpyub_rtt_acc_128B">; 260 261// HVX conditional loads/stores 262 263class Hexagon_pred_vload_imm<LLVMType ValTy> 264 : Hexagon_NonGCC_Intrinsic< 265 [ValTy], 266 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty], 267 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 268 ImmArg<ArgIndex<2>>]>; 269 270class Hexagon_pred_vload_imm_64B: Hexagon_pred_vload_imm<llvm_v16i32_ty>; 271class Hexagon_pred_vload_imm_128B: Hexagon_pred_vload_imm<llvm_v32i32_ty>; 272 273def int_hexagon_V6_vL32b_pred_ai: Hexagon_pred_vload_imm_64B; 274def int_hexagon_V6_vL32b_npred_ai: Hexagon_pred_vload_imm_64B; 275def int_hexagon_V6_vL32b_nt_pred_ai: Hexagon_pred_vload_imm_64B; 276def int_hexagon_V6_vL32b_nt_npred_ai: Hexagon_pred_vload_imm_64B; 277def int_hexagon_V6_vL32b_pred_ai_128B: Hexagon_pred_vload_imm_128B; 278def int_hexagon_V6_vL32b_npred_ai_128B: Hexagon_pred_vload_imm_128B; 279def int_hexagon_V6_vL32b_nt_pred_ai_128B: Hexagon_pred_vload_imm_128B; 280def int_hexagon_V6_vL32b_nt_npred_ai_128B: Hexagon_pred_vload_imm_128B; 281 282class Hexagom_pred_vload_upd<LLVMType ValTy, bit TakesImm> 283 : Hexagon_NonGCC_Intrinsic< 284 [ValTy, llvm_ptr_ty], 285 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty], 286 !if(TakesImm, 287 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 288 ImmArg<ArgIndex<2>>], 289 [IntrReadMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; 290 291class Hexagom_pred_vload_upd_64B<bit TakesImm> 292 : Hexagom_pred_vload_upd<llvm_v16i32_ty, TakesImm>; 293class Hexagom_pred_vload_upd_128B<bit TakesImm> 294 : Hexagom_pred_vload_upd<llvm_v32i32_ty, TakesImm>; 295 296def int_hexagon_V6_vL32b_pred_pi: Hexagom_pred_vload_upd_64B<1>; 297def int_hexagon_V6_vL32b_npred_pi: Hexagom_pred_vload_upd_64B<1>; 298def int_hexagon_V6_vL32b_nt_pred_pi: Hexagom_pred_vload_upd_64B<1>; 299def int_hexagon_V6_vL32b_nt_npred_pi: Hexagom_pred_vload_upd_64B<1>; 300def int_hexagon_V6_vL32b_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 301def int_hexagon_V6_vL32b_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 302def int_hexagon_V6_vL32b_nt_pred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 303def int_hexagon_V6_vL32b_nt_npred_pi_128B: Hexagom_pred_vload_upd_128B<1>; 304 305def int_hexagon_V6_vL32b_pred_ppu: Hexagom_pred_vload_upd_64B<0>; 306def int_hexagon_V6_vL32b_npred_ppu: Hexagom_pred_vload_upd_64B<0>; 307def int_hexagon_V6_vL32b_nt_pred_ppu: Hexagom_pred_vload_upd_64B<0>; 308def int_hexagon_V6_vL32b_nt_npred_ppu: Hexagom_pred_vload_upd_64B<0>; 309def int_hexagon_V6_vL32b_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 310def int_hexagon_V6_vL32b_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 311def int_hexagon_V6_vL32b_nt_pred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 312def int_hexagon_V6_vL32b_nt_npred_ppu_128B: Hexagom_pred_vload_upd_128B<0>; 313 314 315class Hexagon_pred_vstore_imm<LLVMType ValTy> 316 : Hexagon_NonGCC_Intrinsic< 317 [], 318 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty, ValTy], 319 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 320 ImmArg<ArgIndex<2>>]>; 321 322class Hexagon_pred_vstore_imm_64B: Hexagon_pred_vstore_imm<llvm_v16i32_ty>; 323class Hexagon_pred_vstore_imm_128B: Hexagon_pred_vstore_imm<llvm_v32i32_ty>; 324 325def int_hexagon_V6_vS32b_pred_ai: Hexagon_pred_vstore_imm_64B; 326def int_hexagon_V6_vS32b_npred_ai: Hexagon_pred_vstore_imm_64B; 327def int_hexagon_V6_vS32Ub_pred_ai: Hexagon_pred_vstore_imm_64B; 328def int_hexagon_V6_vS32Ub_npred_ai: Hexagon_pred_vstore_imm_64B; 329def int_hexagon_V6_vS32b_nt_pred_ai: Hexagon_pred_vstore_imm_64B; 330def int_hexagon_V6_vS32b_nt_npred_ai: Hexagon_pred_vstore_imm_64B; 331def int_hexagon_V6_vS32b_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 332def int_hexagon_V6_vS32b_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 333def int_hexagon_V6_vS32Ub_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 334def int_hexagon_V6_vS32Ub_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 335def int_hexagon_V6_vS32b_nt_pred_ai_128B: Hexagon_pred_vstore_imm_128B; 336def int_hexagon_V6_vS32b_nt_npred_ai_128B: Hexagon_pred_vstore_imm_128B; 337 338class Hexagon_pred_vstore_upd<LLVMType ValTy, bit TakesImm> 339 : Hexagon_NonGCC_Intrinsic< 340 [llvm_ptr_ty], 341 [llvm_i1_ty, llvm_ptr_ty, llvm_i32_ty, ValTy], 342 !if(TakesImm, 343 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>, 344 ImmArg<ArgIndex<2>>], 345 [IntrWriteMem, IntrArgMemOnly, NoCapture<ArgIndex<1>>])>; 346 347class Hexagon_pred_vstore_upd_64B<bit TakesImm> 348 : Hexagon_pred_vstore_upd<llvm_v16i32_ty, TakesImm>; 349class Hexagon_pred_vstore_upd_128B<bit TakesImm> 350 : Hexagon_pred_vstore_upd<llvm_v32i32_ty, TakesImm>; 351 352def int_hexagon_V6_vS32b_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 353def int_hexagon_V6_vS32b_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 354def int_hexagon_V6_vS32Ub_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 355def int_hexagon_V6_vS32Ub_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 356def int_hexagon_V6_vS32b_nt_pred_pi: Hexagon_pred_vstore_upd_64B<1>; 357def int_hexagon_V6_vS32b_nt_npred_pi: Hexagon_pred_vstore_upd_64B<1>; 358def int_hexagon_V6_vS32b_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 359def int_hexagon_V6_vS32b_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 360def int_hexagon_V6_vS32Ub_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 361def int_hexagon_V6_vS32Ub_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 362def int_hexagon_V6_vS32b_nt_pred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 363def int_hexagon_V6_vS32b_nt_npred_pi_128B: Hexagon_pred_vstore_upd_128B<1>; 364 365def int_hexagon_V6_vS32b_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 366def int_hexagon_V6_vS32b_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 367def int_hexagon_V6_vS32Ub_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 368def int_hexagon_V6_vS32Ub_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 369def int_hexagon_V6_vS32b_nt_pred_ppu: Hexagon_pred_vstore_upd_64B<0>; 370def int_hexagon_V6_vS32b_nt_npred_ppu: Hexagon_pred_vstore_upd_64B<0>; 371def int_hexagon_V6_vS32b_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 372def int_hexagon_V6_vS32b_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 373def int_hexagon_V6_vS32Ub_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 374def int_hexagon_V6_vS32Ub_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 375def int_hexagon_V6_vS32b_nt_pred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 376def int_hexagon_V6_vS32b_nt_npred_ppu_128B: Hexagon_pred_vstore_upd_128B<0>; 377 378 379// HVX Vector predicate casts. 380// These intrinsics do not emit (nor do they correspond to) any instructions, 381// they are no-ops. 382 383def int_hexagon_V6_pred_typecast : 384Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 385 386def int_hexagon_V6_pred_typecast_128B : 387Hexagon_NonGCC_Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 388 389// HVX full-precision multiplication. 390// V6_vmpyss_parts(Vu,Vv) = (MulHS(Vu,Vv), Mul(Vu,Vv)) 391// V6_vmpyuu_parts(Vu,Vv) = (MulHU(Vu,Vv), Mul(Vu,Vv)) 392// V6_vmpyus_parts(Vu,Vv) = (MulHUS(Vu,Vv), Mul(Vu,Vv)) 393// 394// Both, the (purportedly) 64b and the _128B versions are exactly equivalent 395// regardless of the HVX mode, they are both defined for consistency. 396// The purpose of these intrinsics is to have a uniform way of multiplying two 397// integer vectors in the LLVM IR. Many HVX multiply operations interleave 398// the even-odd results, except for 32x32 multiplications. Also, different 399// HVX versions have different instructions that can be used, so defer the 400// instruction choice to the isel. 401class Hexagon_vv_vv_pure: 402 Hexagon_NonGCC_Intrinsic< 403 [llvm_anyvector_ty, LLVMMatchType<0>], 404 [LLVMMatchType<0>, LLVMMatchType<0>], 405 [IntrNoMem]>; 406 407def int_hexagon_V6_vmpyss_parts: Hexagon_vv_vv_pure; 408def int_hexagon_V6_vmpyss_parts_128B: Hexagon_vv_vv_pure; 409def int_hexagon_V6_vmpyuu_parts: Hexagon_vv_vv_pure; 410def int_hexagon_V6_vmpyuu_parts_128B: Hexagon_vv_vv_pure; 411def int_hexagon_V6_vmpyus_parts: Hexagon_vv_vv_pure; 412def int_hexagon_V6_vmpyus_parts_128B: Hexagon_vv_vv_pure; 413 414 415// Masked vector stores 416// 417// These are all deprecated, the intrinsics matching instruction names 418// should be used instead, e.g. int_hexagon_V6_vS32b_qpred_ai, etc. 419 420class Hexagon_custom_vms_Intrinsic 421 : Hexagon_NonGCC_Intrinsic< 422 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], [IntrWriteMem]>; 423 424class Hexagon_custom_vms_Intrinsic_128B 425 : Hexagon_NonGCC_Intrinsic< 426 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], [IntrWriteMem]>; 427 428def int_hexagon_V6_vmaskedstoreq: Hexagon_custom_vms_Intrinsic; 429def int_hexagon_V6_vmaskedstorenq: Hexagon_custom_vms_Intrinsic; 430def int_hexagon_V6_vmaskedstorentq: Hexagon_custom_vms_Intrinsic; 431def int_hexagon_V6_vmaskedstorentnq: Hexagon_custom_vms_Intrinsic; 432 433def int_hexagon_V6_vmaskedstoreq_128B: Hexagon_custom_vms_Intrinsic_128B; 434def int_hexagon_V6_vmaskedstorenq_128B: Hexagon_custom_vms_Intrinsic_128B; 435def int_hexagon_V6_vmaskedstorentq_128B: Hexagon_custom_vms_Intrinsic_128B; 436def int_hexagon_V6_vmaskedstorentnq_128B: Hexagon_custom_vms_Intrinsic_128B; 437 438 439// Intrinsic for instrumentation based profiling using a custom handler. The 440// name of the handler is passed as the first operand to the intrinsic. The 441// handler can take only one int32 input which is passed as the second 442// operand to the intrinsic. 443def int_hexagon_instrprof_custom 444 : Hexagon_NonGCC_Intrinsic<[], 445 [llvm_ptr_ty, llvm_i32_ty], 446 [IntrInaccessibleMemOnly]>; 447 448 449include "llvm/IR/IntrinsicsHexagonDep.td" 450