1 //===-- HexagonMCTargetDesc.cpp - Hexagon Target Descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides Hexagon specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/HexagonMCTargetDesc.h"
14 #include "HexagonDepArch.h"
15 #include "HexagonTargetStreamer.h"
16 #include "MCTargetDesc/HexagonInstPrinter.h"
17 #include "MCTargetDesc/HexagonMCAsmInfo.h"
18 #include "MCTargetDesc/HexagonMCELFStreamer.h"
19 #include "MCTargetDesc/HexagonMCInstrInfo.h"
20 #include "TargetInfo/HexagonTargetInfo.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/BinaryFormat/ELF.h"
24 #include "llvm/MC/MCAsmBackend.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCCodeEmitter.h"
27 #include "llvm/MC/MCContext.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/MC/MCELFObjectWriter.h"
30 #include "llvm/MC/MCELFStreamer.h"
31 #include "llvm/MC/MCInstrAnalysis.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCRegisterInfo.h"
34 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/MC/MCSubtargetInfo.h"
36 #include "llvm/MC/TargetRegistry.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/HexagonAttributes.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include <cassert>
42 #include <cstdint>
43 #include <mutex>
44 #include <new>
45 #include <string>
46 #include <unordered_map>
47
48 using namespace llvm;
49
50 #define GET_INSTRINFO_MC_DESC
51 #define ENABLE_INSTR_PREDICATE_VERIFIER
52 #include "HexagonGenInstrInfo.inc"
53
54 #define GET_SUBTARGETINFO_MC_DESC
55 #include "HexagonGenSubtargetInfo.inc"
56
57 #define GET_REGINFO_MC_DESC
58 #include "HexagonGenRegisterInfo.inc"
59
60 cl::opt<bool> llvm::HexagonDisableCompound
61 ("mno-compound",
62 cl::desc("Disable looking for compound instructions for Hexagon"));
63
64 cl::opt<bool> llvm::HexagonDisableDuplex
65 ("mno-pairing",
66 cl::desc("Disable looking for duplex instructions for Hexagon"));
67
68 namespace { // These flags are to be deprecated
69 cl::opt<bool> MV5("mv5", cl::Hidden, cl::desc("Build for Hexagon V5"),
70 cl::init(false));
71 cl::opt<bool> MV55("mv55", cl::Hidden, cl::desc("Build for Hexagon V55"),
72 cl::init(false));
73 cl::opt<bool> MV60("mv60", cl::Hidden, cl::desc("Build for Hexagon V60"),
74 cl::init(false));
75 cl::opt<bool> MV62("mv62", cl::Hidden, cl::desc("Build for Hexagon V62"),
76 cl::init(false));
77 cl::opt<bool> MV65("mv65", cl::Hidden, cl::desc("Build for Hexagon V65"),
78 cl::init(false));
79 cl::opt<bool> MV66("mv66", cl::Hidden, cl::desc("Build for Hexagon V66"),
80 cl::init(false));
81 cl::opt<bool> MV67("mv67", cl::Hidden, cl::desc("Build for Hexagon V67"),
82 cl::init(false));
83 cl::opt<bool> MV67T("mv67t", cl::Hidden, cl::desc("Build for Hexagon V67T"),
84 cl::init(false));
85 cl::opt<bool> MV68("mv68", cl::Hidden, cl::desc("Build for Hexagon V68"),
86 cl::init(false));
87 cl::opt<bool> MV69("mv69", cl::Hidden, cl::desc("Build for Hexagon V69"),
88 cl::init(false));
89 cl::opt<bool> MV71("mv71", cl::Hidden, cl::desc("Build for Hexagon V71"),
90 cl::init(false));
91 cl::opt<bool> MV71T("mv71t", cl::Hidden, cl::desc("Build for Hexagon V71T"),
92 cl::init(false));
93 cl::opt<bool> MV73("mv73", cl::Hidden, cl::desc("Build for Hexagon V73"),
94 cl::init(false));
95 cl::opt<bool> MV75("mv75", cl::Hidden, cl::desc("Build for Hexagon V75"),
96 cl::init(false));
97 cl::opt<bool> MV79("mv79", cl::Hidden, cl::desc("Build for Hexagon V79"),
98 cl::init(false));
99 } // namespace
100
101 static cl::opt<Hexagon::ArchEnum> EnableHVX(
102 "mhvx", cl::desc("Enable Hexagon Vector eXtensions"),
103 cl::values(clEnumValN(Hexagon::ArchEnum::V60, "v60", "Build for HVX v60"),
104 clEnumValN(Hexagon::ArchEnum::V62, "v62", "Build for HVX v62"),
105 clEnumValN(Hexagon::ArchEnum::V65, "v65", "Build for HVX v65"),
106 clEnumValN(Hexagon::ArchEnum::V66, "v66", "Build for HVX v66"),
107 clEnumValN(Hexagon::ArchEnum::V67, "v67", "Build for HVX v67"),
108 clEnumValN(Hexagon::ArchEnum::V68, "v68", "Build for HVX v68"),
109 clEnumValN(Hexagon::ArchEnum::V69, "v69", "Build for HVX v69"),
110 clEnumValN(Hexagon::ArchEnum::V71, "v71", "Build for HVX v71"),
111 clEnumValN(Hexagon::ArchEnum::V73, "v73", "Build for HVX v73"),
112 clEnumValN(Hexagon::ArchEnum::V75, "v75", "Build for HVX v75"),
113 clEnumValN(Hexagon::ArchEnum::V79, "v79", "Build for HVX v79"),
114 // Sentinel for no value specified.
115 clEnumValN(Hexagon::ArchEnum::Generic, "", "")),
116 // Sentinel for flag not present.
117 cl::init(Hexagon::ArchEnum::NoArch), cl::ValueOptional);
118
119 static cl::opt<bool>
120 DisableHVX("mno-hvx", cl::Hidden,
121 cl::desc("Disable Hexagon Vector eXtensions"));
122
123 static cl::opt<bool>
124 EnableHvxIeeeFp("mhvx-ieee-fp", cl::Hidden,
125 cl::desc("Enable HVX IEEE floating point extensions"));
126 static cl::opt<bool> EnableHexagonCabac
127 ("mcabac", cl::desc("tbd"), cl::init(false));
128
129 static constexpr StringRef DefaultArch = "hexagonv68";
130
HexagonGetArchVariant()131 static StringRef HexagonGetArchVariant() {
132 if (MV5)
133 return "hexagonv5";
134 if (MV55)
135 return "hexagonv55";
136 if (MV60)
137 return "hexagonv60";
138 if (MV62)
139 return "hexagonv62";
140 if (MV65)
141 return "hexagonv65";
142 if (MV66)
143 return "hexagonv66";
144 if (MV67)
145 return "hexagonv67";
146 if (MV67T)
147 return "hexagonv67t";
148 if (MV68)
149 return "hexagonv68";
150 if (MV69)
151 return "hexagonv69";
152 if (MV71)
153 return "hexagonv71";
154 if (MV71T)
155 return "hexagonv71t";
156 if (MV73)
157 return "hexagonv73";
158 if (MV75)
159 return "hexagonv75";
160 if (MV79)
161 return "hexagonv79";
162
163 return "";
164 }
165
selectHexagonCPU(StringRef CPU)166 StringRef Hexagon_MC::selectHexagonCPU(StringRef CPU) {
167 StringRef ArchV = HexagonGetArchVariant();
168 if (!ArchV.empty() && !CPU.empty()) {
169 // Tiny cores have a "t" suffix that is discarded when creating a secondary
170 // non-tiny subtarget. See: addArchSubtarget
171 std::pair<StringRef, StringRef> ArchP = ArchV.split('t');
172 std::pair<StringRef, StringRef> CPUP = CPU.split('t');
173 if (ArchP.first != CPUP.first)
174 report_fatal_error("conflicting architectures specified.");
175 return CPU;
176 }
177 if (ArchV.empty()) {
178 if (CPU.empty())
179 CPU = DefaultArch;
180 return CPU;
181 }
182 return ArchV;
183 }
184
HexagonGetLastSlot()185 unsigned llvm::HexagonGetLastSlot() { return HexagonItinerariesV5FU::SLOT3; }
186
HexagonConvertUnits(unsigned ItinUnits,unsigned * Lanes)187 unsigned llvm::HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes) {
188 enum {
189 CVI_NONE = 0,
190 CVI_XLANE = 1 << 0,
191 CVI_SHIFT = 1 << 1,
192 CVI_MPY0 = 1 << 2,
193 CVI_MPY1 = 1 << 3,
194 CVI_ZW = 1 << 4
195 };
196
197 if (ItinUnits == HexagonItinerariesV62FU::CVI_ALL ||
198 ItinUnits == HexagonItinerariesV62FU::CVI_ALL_NOMEM)
199 return (*Lanes = 4, CVI_XLANE);
200 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01 &&
201 ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
202 return (*Lanes = 2, CVI_XLANE | CVI_MPY0);
203 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY01)
204 return (*Lanes = 2, CVI_MPY0);
205 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLSHF)
206 return (*Lanes = 2, CVI_XLANE);
207 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
208 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT &&
209 ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
210 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
211 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1);
212 else if (ItinUnits & HexagonItinerariesV62FU::CVI_XLANE &&
213 ItinUnits & HexagonItinerariesV62FU::CVI_SHIFT)
214 return (*Lanes = 1, CVI_XLANE | CVI_SHIFT);
215 else if (ItinUnits & HexagonItinerariesV62FU::CVI_MPY0 &&
216 ItinUnits & HexagonItinerariesV62FU::CVI_MPY1)
217 return (*Lanes = 1, CVI_MPY0 | CVI_MPY1);
218 else if (ItinUnits == HexagonItinerariesV62FU::CVI_ZW)
219 return (*Lanes = 1, CVI_ZW);
220 else if (ItinUnits == HexagonItinerariesV62FU::CVI_XLANE)
221 return (*Lanes = 1, CVI_XLANE);
222 else if (ItinUnits == HexagonItinerariesV62FU::CVI_SHIFT)
223 return (*Lanes = 1, CVI_SHIFT);
224
225 return (*Lanes = 0, CVI_NONE);
226 }
227
228
229 namespace llvm {
230 namespace HexagonFUnits {
isSlot0Only(unsigned units)231 bool isSlot0Only(unsigned units) {
232 return HexagonItinerariesV62FU::SLOT0 == units;
233 }
234 } // namespace HexagonFUnits
235 } // namespace llvm
236
237 namespace {
238
239 class HexagonTargetAsmStreamer : public HexagonTargetStreamer {
240 formatted_raw_ostream &OS;
241
242 public:
HexagonTargetAsmStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter & IP)243 HexagonTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS,
244 MCInstPrinter &IP)
245 : HexagonTargetStreamer(S), OS(OS) {}
246
prettyPrintAsm(MCInstPrinter & InstPrinter,uint64_t Address,const MCInst & Inst,const MCSubtargetInfo & STI,raw_ostream & OS)247 void prettyPrintAsm(MCInstPrinter &InstPrinter, uint64_t Address,
248 const MCInst &Inst, const MCSubtargetInfo &STI,
249 raw_ostream &OS) override {
250 assert(HexagonMCInstrInfo::isBundle(Inst));
251 assert(HexagonMCInstrInfo::bundleSize(Inst) <= HEXAGON_PACKET_SIZE);
252 std::string Buffer;
253 {
254 raw_string_ostream TempStream(Buffer);
255 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
256 InstPrinter.printInst(I.getInst(), Address, "", STI, TempStream);
257 TempStream << "\n";
258 }
259 }
260
261 std::string LoopString = "";
262 bool IsLoop0 = HexagonMCInstrInfo::isInnerLoop(Inst);
263 bool IsLoop1 = HexagonMCInstrInfo::isOuterLoop(Inst);
264 if (IsLoop0) {
265 LoopString += (IsLoop1 ? " :endloop01" : " :endloop0");
266 } else if (IsLoop1) {
267 LoopString += " :endloop1";
268 }
269
270 StringRef Contents(Buffer);
271 auto PacketBundle = Contents.rsplit('\n');
272 auto HeadTail = PacketBundle.first.split('\n');
273 StringRef Separator = "\n";
274 StringRef Indent = "\t";
275 OS << "\t{\n";
276 while (!HeadTail.first.empty()) {
277 StringRef InstTxt;
278 auto Duplex = HeadTail.first.split('\v');
279 if (!Duplex.second.empty()) {
280 OS << Indent << Duplex.first << Separator;
281 InstTxt = Duplex.second;
282 } else if (!HeadTail.first.trim().starts_with("immext")) {
283 InstTxt = Duplex.first;
284 }
285 if (!InstTxt.empty())
286 OS << Indent << InstTxt << Separator;
287 HeadTail = HeadTail.second.split('\n');
288 }
289
290 if (HexagonMCInstrInfo::isMemReorderDisabled(Inst))
291 OS << "\n\t} :mem_noshuf" << LoopString;
292 else
293 OS << "\t}" << LoopString;
294 }
295
finish()296 void finish() override { finishAttributeSection(); }
297
finishAttributeSection()298 void finishAttributeSection() override {}
299
emitAttribute(unsigned Attribute,unsigned Value)300 void emitAttribute(unsigned Attribute, unsigned Value) override {
301 OS << "\t.attribute\t" << Attribute << ", " << Twine(Value);
302 if (getStreamer().isVerboseAsm()) {
303 StringRef Name = ELFAttrs::attrTypeAsString(
304 Attribute, HexagonAttrs::getHexagonAttributeTags());
305 if (!Name.empty())
306 OS << "\t// " << Name;
307 }
308 OS << "\n";
309 }
310 };
311
312 class HexagonTargetELFStreamer : public HexagonTargetStreamer {
313 public:
getStreamer()314 MCELFStreamer &getStreamer() {
315 return static_cast<MCELFStreamer &>(Streamer);
316 }
HexagonTargetELFStreamer(MCStreamer & S,MCSubtargetInfo const & STI)317 HexagonTargetELFStreamer(MCStreamer &S, MCSubtargetInfo const &STI)
318 : HexagonTargetStreamer(S) {
319 getStreamer().getWriter().setELFHeaderEFlags(Hexagon_MC::GetELFFlags(STI));
320 }
321
emitCommonSymbolSorted(MCSymbol * Symbol,uint64_t Size,unsigned ByteAlignment,unsigned AccessSize)322 void emitCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
323 unsigned ByteAlignment,
324 unsigned AccessSize) override {
325 HexagonMCELFStreamer &HexagonELFStreamer =
326 static_cast<HexagonMCELFStreamer &>(getStreamer());
327 HexagonELFStreamer.HexagonMCEmitCommonSymbol(
328 Symbol, Size, Align(ByteAlignment), AccessSize);
329 }
330
emitLocalCommonSymbolSorted(MCSymbol * Symbol,uint64_t Size,unsigned ByteAlignment,unsigned AccessSize)331 void emitLocalCommonSymbolSorted(MCSymbol *Symbol, uint64_t Size,
332 unsigned ByteAlignment,
333 unsigned AccessSize) override {
334 HexagonMCELFStreamer &HexagonELFStreamer =
335 static_cast<HexagonMCELFStreamer &>(getStreamer());
336 HexagonELFStreamer.HexagonMCEmitLocalCommonSymbol(
337 Symbol, Size, Align(ByteAlignment), AccessSize);
338 }
339
finish()340 void finish() override { finishAttributeSection(); }
341
reset()342 void reset() override { AttributeSection = nullptr; }
343
344 private:
345 MCSection *AttributeSection = nullptr;
346
finishAttributeSection()347 void finishAttributeSection() override {
348 MCELFStreamer &S = getStreamer();
349 if (S.Contents.empty())
350 return;
351
352 S.emitAttributesSection("hexagon", ".hexagon.attributes",
353 ELF::SHT_HEXAGON_ATTRIBUTES, AttributeSection);
354 }
355
emitAttribute(uint32_t Attribute,uint32_t Value)356 void emitAttribute(uint32_t Attribute, uint32_t Value) override {
357 getStreamer().setAttributeItem(Attribute, Value,
358 /*OverwriteExisting=*/true);
359 }
360 };
361
362 } // end anonymous namespace
363
createHexagonMCInstrInfo()364 llvm::MCInstrInfo *llvm::createHexagonMCInstrInfo() {
365 MCInstrInfo *X = new MCInstrInfo();
366 InitHexagonMCInstrInfo(X);
367 return X;
368 }
369
createHexagonMCRegisterInfo(const Triple & TT)370 static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
371 MCRegisterInfo *X = new MCRegisterInfo();
372 InitHexagonMCRegisterInfo(X, Hexagon::R31, /*DwarfFlavour=*/0,
373 /*EHFlavour=*/0, /*PC=*/Hexagon::PC);
374 return X;
375 }
376
createHexagonMCAsmInfo(const MCRegisterInfo & MRI,const Triple & TT,const MCTargetOptions & Options)377 static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI,
378 const Triple &TT,
379 const MCTargetOptions &Options) {
380 MCAsmInfo *MAI = new HexagonMCAsmInfo(TT);
381
382 // VirtualFP = (R30 + #0).
383 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(
384 nullptr, MRI.getDwarfRegNum(Hexagon::R30, true), 0);
385 MAI->addInitialFrameState(Inst);
386
387 return MAI;
388 }
389
createHexagonMCInstPrinter(const Triple & T,unsigned SyntaxVariant,const MCAsmInfo & MAI,const MCInstrInfo & MII,const MCRegisterInfo & MRI)390 static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T,
391 unsigned SyntaxVariant,
392 const MCAsmInfo &MAI,
393 const MCInstrInfo &MII,
394 const MCRegisterInfo &MRI)
395 {
396 if (SyntaxVariant == 0)
397 return new HexagonInstPrinter(MAI, MII, MRI);
398 else
399 return nullptr;
400 }
401
createMCAsmTargetStreamer(MCStreamer & S,formatted_raw_ostream & OS,MCInstPrinter * IP)402 static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S,
403 formatted_raw_ostream &OS,
404 MCInstPrinter *IP) {
405 return new HexagonTargetAsmStreamer(S, OS, *IP);
406 }
407
createMCStreamer(Triple const & T,MCContext & Context,std::unique_ptr<MCAsmBackend> && MAB,std::unique_ptr<MCObjectWriter> && OW,std::unique_ptr<MCCodeEmitter> && Emitter)408 static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context,
409 std::unique_ptr<MCAsmBackend> &&MAB,
410 std::unique_ptr<MCObjectWriter> &&OW,
411 std::unique_ptr<MCCodeEmitter> &&Emitter) {
412 return createHexagonELFStreamer(T, Context, std::move(MAB), std::move(OW),
413 std::move(Emitter));
414 }
415
416 static MCTargetStreamer *
createHexagonObjectTargetStreamer(MCStreamer & S,const MCSubtargetInfo & STI)417 createHexagonObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
418 return new HexagonTargetELFStreamer(S, STI);
419 }
420
createHexagonNullTargetStreamer(MCStreamer & S)421 static MCTargetStreamer *createHexagonNullTargetStreamer(MCStreamer &S) {
422 return new HexagonTargetStreamer(S);
423 }
424
clearFeature(MCSubtargetInfo * STI,uint64_t F)425 static void LLVM_ATTRIBUTE_UNUSED clearFeature(MCSubtargetInfo* STI, uint64_t F) {
426 if (STI->hasFeature(F))
427 STI->ToggleFeature(F);
428 }
429
checkFeature(MCSubtargetInfo * STI,uint64_t F)430 static bool LLVM_ATTRIBUTE_UNUSED checkFeature(MCSubtargetInfo* STI, uint64_t F) {
431 return STI->hasFeature(F);
432 }
433
434 namespace {
selectHexagonFS(StringRef CPU,StringRef FS)435 std::string selectHexagonFS(StringRef CPU, StringRef FS) {
436 SmallVector<StringRef, 3> Result;
437 if (!FS.empty())
438 Result.push_back(FS);
439
440 switch (EnableHVX) {
441 case Hexagon::ArchEnum::V5:
442 case Hexagon::ArchEnum::V55:
443 break;
444 case Hexagon::ArchEnum::V60:
445 Result.push_back("+hvxv60");
446 break;
447 case Hexagon::ArchEnum::V62:
448 Result.push_back("+hvxv62");
449 break;
450 case Hexagon::ArchEnum::V65:
451 Result.push_back("+hvxv65");
452 break;
453 case Hexagon::ArchEnum::V66:
454 Result.push_back("+hvxv66");
455 break;
456 case Hexagon::ArchEnum::V67:
457 Result.push_back("+hvxv67");
458 break;
459 case Hexagon::ArchEnum::V68:
460 Result.push_back("+hvxv68");
461 break;
462 case Hexagon::ArchEnum::V69:
463 Result.push_back("+hvxv69");
464 break;
465 case Hexagon::ArchEnum::V71:
466 Result.push_back("+hvxv71");
467 break;
468 case Hexagon::ArchEnum::V73:
469 Result.push_back("+hvxv73");
470 break;
471 case Hexagon::ArchEnum::V75:
472 Result.push_back("+hvxv75");
473 break;
474 case Hexagon::ArchEnum::V79:
475 Result.push_back("+hvxv79");
476 break;
477
478 case Hexagon::ArchEnum::Generic: {
479 Result.push_back(StringSwitch<StringRef>(CPU)
480 .Case("hexagonv60", "+hvxv60")
481 .Case("hexagonv62", "+hvxv62")
482 .Case("hexagonv65", "+hvxv65")
483 .Case("hexagonv66", "+hvxv66")
484 .Case("hexagonv67", "+hvxv67")
485 .Case("hexagonv67t", "+hvxv67")
486 .Case("hexagonv68", "+hvxv68")
487 .Case("hexagonv69", "+hvxv69")
488 .Case("hexagonv71", "+hvxv71")
489 .Case("hexagonv71t", "+hvxv71")
490 .Case("hexagonv73", "+hvxv73")
491 .Case("hexagonv75", "+hvxv75")
492 .Case("hexagonv79", "+hvxv79"));
493 break;
494 }
495 case Hexagon::ArchEnum::NoArch:
496 // Sentinel if -mhvx isn't specified
497 break;
498 }
499 if (EnableHvxIeeeFp)
500 Result.push_back("+hvx-ieee-fp");
501 if (EnableHexagonCabac)
502 Result.push_back("+cabac");
503
504 return join(Result.begin(), Result.end(), ",");
505 }
506 }
507
isCPUValid(StringRef CPU)508 static bool isCPUValid(StringRef CPU) {
509 return Hexagon::getCpu(CPU).has_value();
510 }
511
512 namespace {
selectCPUAndFS(StringRef CPU,StringRef FS)513 std::pair<std::string, std::string> selectCPUAndFS(StringRef CPU,
514 StringRef FS) {
515 std::pair<std::string, std::string> Result;
516 Result.first = std::string(Hexagon_MC::selectHexagonCPU(CPU));
517 Result.second = selectHexagonFS(Result.first, FS);
518 return Result;
519 }
520 std::mutex ArchSubtargetMutex;
521 std::unordered_map<std::string, std::unique_ptr<MCSubtargetInfo const>>
522 ArchSubtarget;
523 } // namespace
524
525 MCSubtargetInfo const *
getArchSubtarget(MCSubtargetInfo const * STI)526 Hexagon_MC::getArchSubtarget(MCSubtargetInfo const *STI) {
527 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
528 auto Existing = ArchSubtarget.find(std::string(STI->getCPU()));
529 if (Existing == ArchSubtarget.end())
530 return nullptr;
531 return Existing->second.get();
532 }
533
completeHVXFeatures(const FeatureBitset & S)534 FeatureBitset Hexagon_MC::completeHVXFeatures(const FeatureBitset &S) {
535 using namespace Hexagon;
536 // Make sure that +hvx-length turns hvx on, and that "hvx" alone
537 // turns on hvxvNN, corresponding to the existing ArchVNN.
538 FeatureBitset FB = S;
539 unsigned CpuArch = ArchV5;
540 for (unsigned F :
541 {ArchV79, ArchV75, ArchV73, ArchV71, ArchV69, ArchV68, ArchV67, ArchV66,
542 ArchV65, ArchV62, ArchV60, ArchV55, ArchV5}) {
543 if (!FB.test(F))
544 continue;
545 CpuArch = F;
546 break;
547 }
548 bool UseHvx = false;
549 for (unsigned F : {ExtensionHVX, ExtensionHVX64B, ExtensionHVX128B}) {
550 if (!FB.test(F))
551 continue;
552 UseHvx = true;
553 break;
554 }
555 bool HasHvxVer = false;
556 for (unsigned F :
557 {ExtensionHVXV60, ExtensionHVXV62, ExtensionHVXV65, ExtensionHVXV66,
558 ExtensionHVXV67, ExtensionHVXV68, ExtensionHVXV69, ExtensionHVXV71,
559 ExtensionHVXV73, ExtensionHVXV75, ExtensionHVXV79}) {
560 if (!FB.test(F))
561 continue;
562 HasHvxVer = true;
563 UseHvx = true;
564 break;
565 }
566
567 if (!UseHvx || HasHvxVer)
568 return FB;
569
570 // HasHvxVer is false, and UseHvx is true.
571 switch (CpuArch) {
572 case ArchV79:
573 FB.set(ExtensionHVXV79);
574 [[fallthrough]];
575 case ArchV75:
576 FB.set(ExtensionHVXV75);
577 [[fallthrough]];
578 case ArchV73:
579 FB.set(ExtensionHVXV73);
580 [[fallthrough]];
581 case ArchV71:
582 FB.set(ExtensionHVXV71);
583 [[fallthrough]];
584 case ArchV69:
585 FB.set(ExtensionHVXV69);
586 [[fallthrough]];
587 case ArchV68:
588 FB.set(ExtensionHVXV68);
589 [[fallthrough]];
590 case ArchV67:
591 FB.set(ExtensionHVXV67);
592 [[fallthrough]];
593 case ArchV66:
594 FB.set(ExtensionHVXV66);
595 [[fallthrough]];
596 case ArchV65:
597 FB.set(ExtensionHVXV65);
598 [[fallthrough]];
599 case ArchV62:
600 FB.set(ExtensionHVXV62);
601 [[fallthrough]];
602 case ArchV60:
603 FB.set(ExtensionHVXV60);
604 break;
605 }
606 return FB;
607 }
608
createHexagonMCSubtargetInfo(const Triple & TT,StringRef CPU,StringRef FS)609 MCSubtargetInfo *Hexagon_MC::createHexagonMCSubtargetInfo(const Triple &TT,
610 StringRef CPU,
611 StringRef FS) {
612 std::pair<std::string, std::string> Features = selectCPUAndFS(CPU, FS);
613 StringRef CPUName = Features.first;
614 StringRef ArchFS = Features.second;
615
616 MCSubtargetInfo *X = createHexagonMCSubtargetInfoImpl(
617 TT, CPUName, /*TuneCPU*/ CPUName, ArchFS);
618 if (X != nullptr && (CPUName == "hexagonv67t" || CPUName == "hexagon71t"))
619 addArchSubtarget(X, ArchFS);
620
621 if (CPU == "help")
622 exit(0);
623
624 if (!isCPUValid(CPUName.str())) {
625 errs() << "error: invalid CPU \"" << CPUName.str().c_str()
626 << "\" specified\n";
627 return nullptr;
628 }
629
630 // Add qfloat subtarget feature by default to v68 and above
631 // unless explicitly disabled
632 if (checkFeature(X, Hexagon::ExtensionHVXV68) &&
633 !ArchFS.contains("-hvx-qfloat")) {
634 llvm::FeatureBitset Features = X->getFeatureBits();
635 X->setFeatureBits(Features.set(Hexagon::ExtensionHVXQFloat));
636 }
637
638 if (HexagonDisableDuplex) {
639 llvm::FeatureBitset Features = X->getFeatureBits();
640 X->setFeatureBits(Features.reset(Hexagon::FeatureDuplex));
641 }
642
643 X->setFeatureBits(completeHVXFeatures(X->getFeatureBits()));
644
645 // The Z-buffer instructions are grandfathered in for current
646 // architectures but omitted for new ones. Future instruction
647 // sets may introduce new/conflicting z-buffer instructions.
648 const bool ZRegOnDefault =
649 (CPUName == "hexagonv67") || (CPUName == "hexagonv66");
650 if (ZRegOnDefault) {
651 llvm::FeatureBitset Features = X->getFeatureBits();
652 X->setFeatureBits(Features.set(Hexagon::ExtensionZReg));
653 }
654
655 return X;
656 }
657
addArchSubtarget(MCSubtargetInfo const * STI,StringRef FS)658 void Hexagon_MC::addArchSubtarget(MCSubtargetInfo const *STI, StringRef FS) {
659 assert(STI != nullptr);
660 if (STI->getCPU().contains("t")) {
661 auto ArchSTI = createHexagonMCSubtargetInfo(STI->getTargetTriple(),
662 STI->getCPU().drop_back(), FS);
663 std::lock_guard<std::mutex> Lock(ArchSubtargetMutex);
664 ArchSubtarget[std::string(STI->getCPU())] =
665 std::unique_ptr<MCSubtargetInfo const>(ArchSTI);
666 }
667 }
668
669 std::optional<unsigned>
getHVXVersion(const FeatureBitset & Features)670 Hexagon_MC::getHVXVersion(const FeatureBitset &Features) {
671 for (auto Arch : {Hexagon::ExtensionHVXV79, Hexagon::ExtensionHVXV75,
672 Hexagon::ExtensionHVXV73, Hexagon::ExtensionHVXV71,
673 Hexagon::ExtensionHVXV69, Hexagon::ExtensionHVXV68,
674 Hexagon::ExtensionHVXV67, Hexagon::ExtensionHVXV66,
675 Hexagon::ExtensionHVXV65, Hexagon::ExtensionHVXV62,
676 Hexagon::ExtensionHVXV60})
677 if (Features.test(Arch))
678 return Arch;
679 return {};
680 }
681
getArchVersion(const FeatureBitset & Features)682 unsigned Hexagon_MC::getArchVersion(const FeatureBitset &Features) {
683 for (auto Arch :
684 {Hexagon::ArchV79, Hexagon::ArchV75, Hexagon::ArchV73, Hexagon::ArchV71,
685 Hexagon::ArchV69, Hexagon::ArchV68, Hexagon::ArchV67, Hexagon::ArchV66,
686 Hexagon::ArchV65, Hexagon::ArchV62, Hexagon::ArchV60, Hexagon::ArchV55,
687 Hexagon::ArchV5})
688 if (Features.test(Arch))
689 return Arch;
690 llvm_unreachable("Expected arch v5-v79");
691 return 0;
692 }
693
GetELFFlags(const MCSubtargetInfo & STI)694 unsigned Hexagon_MC::GetELFFlags(const MCSubtargetInfo &STI) {
695 return StringSwitch<unsigned>(STI.getCPU())
696 .Case("generic", llvm::ELF::EF_HEXAGON_MACH_V5)
697 .Case("hexagonv5", llvm::ELF::EF_HEXAGON_MACH_V5)
698 .Case("hexagonv55", llvm::ELF::EF_HEXAGON_MACH_V55)
699 .Case("hexagonv60", llvm::ELF::EF_HEXAGON_MACH_V60)
700 .Case("hexagonv62", llvm::ELF::EF_HEXAGON_MACH_V62)
701 .Case("hexagonv65", llvm::ELF::EF_HEXAGON_MACH_V65)
702 .Case("hexagonv66", llvm::ELF::EF_HEXAGON_MACH_V66)
703 .Case("hexagonv67", llvm::ELF::EF_HEXAGON_MACH_V67)
704 .Case("hexagonv67t", llvm::ELF::EF_HEXAGON_MACH_V67T)
705 .Case("hexagonv68", llvm::ELF::EF_HEXAGON_MACH_V68)
706 .Case("hexagonv69", llvm::ELF::EF_HEXAGON_MACH_V69)
707 .Case("hexagonv71", llvm::ELF::EF_HEXAGON_MACH_V71)
708 .Case("hexagonv71t", llvm::ELF::EF_HEXAGON_MACH_V71T)
709 .Case("hexagonv73", llvm::ELF::EF_HEXAGON_MACH_V73)
710 .Case("hexagonv75", llvm::ELF::EF_HEXAGON_MACH_V75)
711 .Case("hexagonv79", llvm::ELF::EF_HEXAGON_MACH_V79);
712 }
713
GetVectRegRev()714 llvm::ArrayRef<MCPhysReg> Hexagon_MC::GetVectRegRev() {
715 return ArrayRef(VectRegRev);
716 }
717
718 namespace {
719 class HexagonMCInstrAnalysis : public MCInstrAnalysis {
720 public:
HexagonMCInstrAnalysis(MCInstrInfo const * Info)721 HexagonMCInstrAnalysis(MCInstrInfo const *Info) : MCInstrAnalysis(Info) {}
722
isUnconditionalBranch(MCInst const & Inst) const723 bool isUnconditionalBranch(MCInst const &Inst) const override {
724 //assert(!HexagonMCInstrInfo::isBundle(Inst));
725 return MCInstrAnalysis::isUnconditionalBranch(Inst);
726 }
727
isConditionalBranch(MCInst const & Inst) const728 bool isConditionalBranch(MCInst const &Inst) const override {
729 //assert(!HexagonMCInstrInfo::isBundle(Inst));
730 return MCInstrAnalysis::isConditionalBranch(Inst);
731 }
732
evaluateBranch(MCInst const & Inst,uint64_t Addr,uint64_t Size,uint64_t & Target) const733 bool evaluateBranch(MCInst const &Inst, uint64_t Addr,
734 uint64_t Size, uint64_t &Target) const override {
735 if (!(isCall(Inst) || isUnconditionalBranch(Inst) ||
736 isConditionalBranch(Inst)))
737 return false;
738
739 //assert(!HexagonMCInstrInfo::isBundle(Inst));
740 if (!HexagonMCInstrInfo::isExtendable(*Info, Inst))
741 return false;
742 auto const &Extended(HexagonMCInstrInfo::getExtendableOperand(*Info, Inst));
743 assert(Extended.isExpr());
744 int64_t Value;
745 if (!Extended.getExpr()->evaluateAsAbsolute(Value))
746 return false;
747 Target = Value;
748 return true;
749 }
750
getValueFromMask(uint32_t Instruction,uint32_t Mask) const751 uint32_t getValueFromMask(uint32_t Instruction, uint32_t Mask) const {
752 uint32_t Result = 0;
753 uint32_t Offset = 0;
754 while (Mask) {
755 if (Instruction & (Mask & -Mask))
756 Result |= (1 << Offset);
757 Mask &= (Mask - 1);
758 ++Offset;
759 }
760 return Result;
761 }
762
763 std::vector<std::pair<uint64_t, uint64_t>>
findPltEntries(uint64_t PltSectionVA,ArrayRef<uint8_t> PltContents,const MCSubtargetInfo & STI) const764 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
765 const MCSubtargetInfo &STI) const override {
766 // Do a lightweight parsing of PLT entries.
767 std::vector<std::pair<uint64_t, uint64_t>> Result;
768 for (uint64_t Byte = 0x0, End = PltContents.size(); Byte < End; Byte += 4) {
769 // Recognize immext(##gotpltn)
770 uint32_t ImmExt = support::endian::read32le(PltContents.data() + Byte);
771 if ((ImmExt & 0x00004000) != 0x00004000)
772 continue;
773 uint32_t LoadGotPlt =
774 support::endian::read32le(PltContents.data() + Byte + 4);
775 if ((LoadGotPlt & 0x6a49c00c) != 0x6a49c00c)
776 continue;
777 uint32_t Address = (getValueFromMask(ImmExt, 0xfff3fff) << 6) +
778 getValueFromMask(LoadGotPlt, 0x1f80) + PltSectionVA +
779 Byte;
780 Result.emplace_back(PltSectionVA + Byte, Address);
781 }
782 return Result;
783 }
784 };
785 } // namespace
786
createHexagonMCInstrAnalysis(const MCInstrInfo * Info)787 static MCInstrAnalysis *createHexagonMCInstrAnalysis(const MCInstrInfo *Info) {
788 return new HexagonMCInstrAnalysis(Info);
789 }
790
791 // Force static initialization.
792 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
LLVMInitializeHexagonTargetMC()793 LLVMInitializeHexagonTargetMC() {
794 // Register the MC asm info.
795 RegisterMCAsmInfoFn X(getTheHexagonTarget(), createHexagonMCAsmInfo);
796
797 // Register the MC instruction info.
798 TargetRegistry::RegisterMCInstrInfo(getTheHexagonTarget(),
799 createHexagonMCInstrInfo);
800
801 // Register the MC register info.
802 TargetRegistry::RegisterMCRegInfo(getTheHexagonTarget(),
803 createHexagonMCRegisterInfo);
804
805 // Register the MC subtarget info.
806 TargetRegistry::RegisterMCSubtargetInfo(
807 getTheHexagonTarget(), Hexagon_MC::createHexagonMCSubtargetInfo);
808
809 // Register the MC Code Emitter
810 TargetRegistry::RegisterMCCodeEmitter(getTheHexagonTarget(),
811 createHexagonMCCodeEmitter);
812
813 // Register the asm backend
814 TargetRegistry::RegisterMCAsmBackend(getTheHexagonTarget(),
815 createHexagonAsmBackend);
816
817 // Register the MC instruction analyzer.
818 TargetRegistry::RegisterMCInstrAnalysis(getTheHexagonTarget(),
819 createHexagonMCInstrAnalysis);
820
821 // Register the obj streamer
822 TargetRegistry::RegisterELFStreamer(getTheHexagonTarget(), createMCStreamer);
823
824 // Register the obj target streamer
825 TargetRegistry::RegisterObjectTargetStreamer(
826 getTheHexagonTarget(), createHexagonObjectTargetStreamer);
827
828 // Register the asm streamer
829 TargetRegistry::RegisterAsmTargetStreamer(getTheHexagonTarget(),
830 createMCAsmTargetStreamer);
831
832 // Register the null streamer
833 TargetRegistry::RegisterNullTargetStreamer(getTheHexagonTarget(),
834 createHexagonNullTargetStreamer);
835
836 // Register the MC Inst Printer
837 TargetRegistry::RegisterMCInstPrinter(getTheHexagonTarget(),
838 createHexagonMCInstPrinter);
839 }
840