1 //===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements SystemZ TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "SystemZ.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/LangOptions.h"
16 #include "clang/Basic/MacroBuilder.h"
17 #include "clang/Basic/TargetBuiltins.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20
21 using namespace clang;
22 using namespace clang::targets;
23
24 static constexpr int NumBuiltins =
25 clang::SystemZ::LastTSBuiltin - Builtin::FirstTSBuiltin;
26
27 static constexpr llvm::StringTable BuiltinStrings =
28 CLANG_BUILTIN_STR_TABLE_START
29 #define BUILTIN CLANG_BUILTIN_STR_TABLE
30 #define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
31 #include "clang/Basic/BuiltinsSystemZ.def"
32 ;
33
34 static constexpr auto BuiltinInfos = Builtin::MakeInfos<NumBuiltins>({
35 #define BUILTIN CLANG_BUILTIN_ENTRY
36 #define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
37 #include "clang/Basic/BuiltinsSystemZ.def"
38 });
39
40 const char *const SystemZTargetInfo::GCCRegNames[] = {
41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
42 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
43 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
44 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
45 /*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
46 "v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
47 "v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
48 };
49
50 const TargetInfo::AddlRegName GCCAddlRegNames[] = {
51 {{"v0"}, 16}, {{"v2"}, 17}, {{"v4"}, 18}, {{"v6"}, 19},
52 {{"v1"}, 20}, {{"v3"}, 21}, {{"v5"}, 22}, {{"v7"}, 23},
53 {{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27},
54 {{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31}
55 };
56
getGCCRegNames() const57 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
58 return llvm::ArrayRef(GCCRegNames);
59 }
60
getGCCAddlRegNames() const61 ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
62 return llvm::ArrayRef(GCCAddlRegNames);
63 }
64
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const65 bool SystemZTargetInfo::validateAsmConstraint(
66 const char *&Name, TargetInfo::ConstraintInfo &Info) const {
67 switch (*Name) {
68 default:
69 return false;
70
71 case 'Z':
72 switch (Name[1]) {
73 default:
74 return false;
75 case 'Q': // Address with base and unsigned 12-bit displacement
76 case 'R': // Likewise, plus an index
77 case 'S': // Address with base and signed 20-bit displacement
78 case 'T': // Likewise, plus an index
79 break;
80 }
81 [[fallthrough]];
82 case 'a': // Address register
83 case 'd': // Data register (equivalent to 'r')
84 case 'f': // Floating-point register
85 case 'v': // Vector register
86 Info.setAllowsRegister();
87 return true;
88
89 case 'I': // Unsigned 8-bit constant
90 case 'J': // Unsigned 12-bit constant
91 case 'K': // Signed 16-bit constant
92 case 'L': // Signed 20-bit displacement (on all targets we support)
93 case 'M': // 0x7fffffff
94 return true;
95
96 case 'Q': // Memory with base and unsigned 12-bit displacement
97 case 'R': // Likewise, plus an index
98 case 'S': // Memory with base and signed 20-bit displacement
99 case 'T': // Likewise, plus an index
100 Info.setAllowsMemory();
101 return true;
102 }
103 }
104
105 struct ISANameRevision {
106 llvm::StringLiteral Name;
107 int ISARevisionID;
108 };
109 static constexpr ISANameRevision ISARevisions[] = {
110 {{"arch8"}, 8}, {{"z10"}, 8},
111 {{"arch9"}, 9}, {{"z196"}, 9},
112 {{"arch10"}, 10}, {{"zEC12"}, 10},
113 {{"arch11"}, 11}, {{"z13"}, 11},
114 {{"arch12"}, 12}, {{"z14"}, 12},
115 {{"arch13"}, 13}, {{"z15"}, 13},
116 {{"arch14"}, 14}, {{"z16"}, 14},
117 {{"arch15"}, 15}, {{"z17"}, 15},
118 };
119
getISARevision(StringRef Name) const120 int SystemZTargetInfo::getISARevision(StringRef Name) const {
121 const auto Rev =
122 llvm::find_if(ISARevisions, [Name](const ISANameRevision &CR) {
123 return CR.Name == Name;
124 });
125 if (Rev == std::end(ISARevisions))
126 return -1;
127 return Rev->ISARevisionID;
128 }
129
fillValidCPUList(SmallVectorImpl<StringRef> & Values) const130 void SystemZTargetInfo::fillValidCPUList(
131 SmallVectorImpl<StringRef> &Values) const {
132 for (const ISANameRevision &Rev : ISARevisions)
133 Values.push_back(Rev.Name);
134 }
135
hasFeature(StringRef Feature) const136 bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
137 return llvm::StringSwitch<bool>(Feature)
138 .Case("systemz", true)
139 .Case("arch8", ISARevision >= 8)
140 .Case("arch9", ISARevision >= 9)
141 .Case("arch10", ISARevision >= 10)
142 .Case("arch11", ISARevision >= 11)
143 .Case("arch12", ISARevision >= 12)
144 .Case("arch13", ISARevision >= 13)
145 .Case("arch14", ISARevision >= 14)
146 .Case("arch15", ISARevision >= 15)
147 .Case("htm", HasTransactionalExecution)
148 .Case("vx", HasVector)
149 .Default(false);
150 }
151
getMinGlobalAlign(uint64_t Size,bool HasNonWeakDef) const152 unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
153 bool HasNonWeakDef) const {
154 // Don't enforce the minimum alignment on an external or weak symbol if
155 // -munaligned-symbols is passed.
156 if (UnalignedSymbols && !HasNonWeakDef)
157 return 0;
158
159 return MinGlobalAlign;
160 }
161
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const162 void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
163 MacroBuilder &Builder) const {
164 Builder.defineMacro("__s390__");
165 Builder.defineMacro("__s390x__");
166 Builder.defineMacro("__zarch__");
167 Builder.defineMacro("__LONG_DOUBLE_128__");
168
169 Builder.defineMacro("__ARCH__", Twine(ISARevision));
170
171 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
172 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
173 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
174 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
175
176 if (HasTransactionalExecution)
177 Builder.defineMacro("__HTM__");
178 if (HasVector)
179 Builder.defineMacro("__VX__");
180 if (Opts.ZVector)
181 Builder.defineMacro("__VEC__", "10305");
182
183 /* Set __TARGET_LIB__ only if a value was given. If no value was given */
184 /* we rely on the LE headers to define __TARGET_LIB__. */
185 if (!getTriple().getOSVersion().empty()) {
186 llvm::VersionTuple V = getTriple().getOSVersion();
187 // Create string with form: 0xPVRRMMMM, where P=4
188 std::string Str("0x");
189 unsigned int Librel = 0x40000000;
190 Librel |= V.getMajor() << 24;
191 Librel |= V.getMinor().value_or(1) << 16;
192 Librel |= V.getSubminor().value_or(0);
193 Str += llvm::utohexstr(Librel);
194
195 Builder.defineMacro("__TARGET_LIB__", Str.c_str());
196 }
197 }
198
199 llvm::SmallVector<Builtin::InfosShard>
getTargetBuiltins() const200 SystemZTargetInfo::getTargetBuiltins() const {
201 return {{&BuiltinStrings, BuiltinInfos}};
202 }
203