xref: /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AArch64Combine.td (revision 0fca6ea1d4eea4c934cfff25ac9ee8ad6fe95583)
1//=- AArch64Combine.td - Define AArch64 Combine Rules ---------*-tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12include "llvm/Target/GlobalISel/Combine.td"
13
14def fconstant_to_constant : GICombineRule<
15  (defs root:$root),
16  (match (wip_match_opcode G_FCONSTANT):$root,
17         [{ return matchFConstantToConstant(*${root}, MRI); }]),
18  (apply [{ applyFConstantToConstant(*${root}); }])>;
19
20def icmp_redundant_trunc_matchdata : GIDefMatchData<"Register">;
21def icmp_redundant_trunc : GICombineRule<
22  (defs root:$root, icmp_redundant_trunc_matchdata:$matchinfo),
23  (match (wip_match_opcode G_ICMP):$root,
24         [{ return matchICmpRedundantTrunc(*${root}, MRI, Helper.getKnownBits(), ${matchinfo}); }]),
25  (apply [{ applyICmpRedundantTrunc(*${root}, MRI, B, Observer, ${matchinfo}); }])>;
26
27// AArch64-specific offset folding for G_GLOBAL_VALUE.
28def fold_global_offset_matchdata : GIDefMatchData<"std::pair<uint64_t, uint64_t>">;
29def fold_global_offset : GICombineRule<
30  (defs root:$root, fold_global_offset_matchdata:$matchinfo),
31  (match (wip_match_opcode G_GLOBAL_VALUE):$root,
32          [{ return matchFoldGlobalOffset(*${root}, MRI, ${matchinfo}); }]),
33  (apply [{ applyFoldGlobalOffset(*${root}, MRI, B, Observer, ${matchinfo});}])
34>;
35
36// Boolean: 0 = G_ZEXT, 1 = G_SEXT
37def ext_addv_to_udot_addv_matchinfo : GIDefMatchData<"std::tuple<Register, Register, bool>">;
38let Predicates = [HasDotProd] in {
39def ext_addv_to_udot_addv : GICombineRule<
40  (defs root:$root, ext_addv_to_udot_addv_matchinfo:$matchinfo),
41  (match (wip_match_opcode G_VECREDUCE_ADD):$root,
42         [{ return matchExtAddvToUdotAddv(*${root}, MRI, STI, ${matchinfo}); }]),
43  (apply [{ applyExtAddvToUdotAddv(*${root}, MRI, B, Observer, STI, ${matchinfo}); }])
44>;
45}
46
47def ext_uaddv_to_uaddlv_matchinfo : GIDefMatchData<"std::pair<Register, bool>">;
48def ext_uaddv_to_uaddlv : GICombineRule<
49  (defs root:$root, ext_uaddv_to_uaddlv_matchinfo:$matchinfo),
50  (match (wip_match_opcode G_VECREDUCE_ADD):$root,
51         [{ return matchExtUaddvToUaddlv(*${root}, MRI, ${matchinfo}); }]),
52  (apply [{ applyExtUaddvToUaddlv(*${root}, MRI, B, Observer, ${matchinfo}); }])
53>;
54
55class push_opcode_through_ext<Instruction opcode, Instruction extOpcode> : GICombineRule <
56  (defs root:$root),
57  (match (extOpcode $ext1, $src1):$ExtMI,
58         (extOpcode $ext2, $src2),
59         (opcode $dst, $ext1, $ext2):$root,
60         [{ return matchPushAddSubExt(*${root}, MRI, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }]),
61  (apply [{ applyPushAddSubExt(*${root}, MRI, B, ${ExtMI}->getOpcode() == TargetOpcode::G_SEXT, ${dst}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }])>;
62
63def push_sub_through_zext : push_opcode_through_ext<G_SUB, G_ZEXT>;
64def push_add_through_zext : push_opcode_through_ext<G_ADD, G_ZEXT>;
65def push_sub_through_sext : push_opcode_through_ext<G_SUB, G_SEXT>;
66def push_add_through_sext : push_opcode_through_ext<G_ADD, G_SEXT>;
67
68def AArch64PreLegalizerCombiner: GICombiner<
69  "AArch64PreLegalizerCombinerImpl", [all_combines,
70                                      fconstant_to_constant,
71                                      icmp_redundant_trunc,
72                                      fold_global_offset,
73                                      shuffle_to_extract,
74                                      ext_addv_to_udot_addv,
75                                      ext_uaddv_to_uaddlv,
76                                      push_sub_through_zext,
77                                      push_add_through_zext,
78                                      push_sub_through_sext,
79                                      push_add_through_sext]> {
80  let CombineAllMethodName = "tryCombineAllImpl";
81}
82
83def AArch64O0PreLegalizerCombiner: GICombiner<
84  "AArch64O0PreLegalizerCombinerImpl", [optnone_combines]> {
85  let CombineAllMethodName = "tryCombineAllImpl";
86}
87
88// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
89// target-specific opcode.
90def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
91
92def rev : GICombineRule<
93  (defs root:$root, shuffle_matchdata:$matchinfo),
94  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
95         [{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
96  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
97>;
98
99def zip : GICombineRule<
100  (defs root:$root, shuffle_matchdata:$matchinfo),
101  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
102         [{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
103  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
104>;
105
106def uzp : GICombineRule<
107  (defs root:$root, shuffle_matchdata:$matchinfo),
108  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
109         [{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
110  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
111>;
112
113def dup: GICombineRule <
114  (defs root:$root, shuffle_matchdata:$matchinfo),
115  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
116         [{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
117  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
118>;
119
120def trn : GICombineRule<
121  (defs root:$root, shuffle_matchdata:$matchinfo),
122  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
123         [{ return matchTRN(*${root}, MRI, ${matchinfo}); }]),
124  (apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
125>;
126
127def ext: GICombineRule <
128  (defs root:$root, shuffle_matchdata:$matchinfo),
129  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
130         [{ return matchEXT(*${root}, MRI, ${matchinfo}); }]),
131  (apply [{ applyEXT(*${root}, ${matchinfo}); }])
132>;
133
134def insertelt_nonconst: GICombineRule <
135  (defs root:$root, shuffle_matchdata:$matchinfo),
136  (match (wip_match_opcode G_INSERT_VECTOR_ELT):$root,
137         [{ return matchNonConstInsert(*${root}, MRI); }]),
138  (apply [{ applyNonConstInsert(*${root}, MRI, B); }])
139>;
140
141def shuf_to_ins_matchdata : GIDefMatchData<"std::tuple<Register, int, Register, int>">;
142def shuf_to_ins: GICombineRule <
143  (defs root:$root, shuf_to_ins_matchdata:$matchinfo),
144  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
145         [{ return matchINS(*${root}, MRI, ${matchinfo}); }]),
146  (apply [{ applyINS(*${root}, MRI, B, ${matchinfo}); }])
147>;
148
149def vashr_vlshr_imm_matchdata : GIDefMatchData<"int64_t">;
150def vashr_vlshr_imm : GICombineRule<
151  (defs root:$root, vashr_vlshr_imm_matchdata:$matchinfo),
152  (match (wip_match_opcode G_ASHR, G_LSHR):$root,
153          [{ return matchVAshrLshrImm(*${root}, MRI, ${matchinfo}); }]),
154  (apply [{ applyVAshrLshrImm(*${root}, MRI, ${matchinfo}); }])
155>;
156
157def form_duplane_matchdata :
158  GIDefMatchData<"std::pair<unsigned, int>">;
159def form_duplane : GICombineRule <
160  (defs root:$root, form_duplane_matchdata:$matchinfo),
161  (match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
162          [{ return matchDupLane(*${root}, MRI, ${matchinfo}); }]),
163  (apply [{ applyDupLane(*${root}, MRI, B, ${matchinfo}); }])
164>;
165
166def shuffle_vector_lowering : GICombineGroup<[dup, rev, ext, zip, uzp, trn,
167                                              form_duplane, shuf_to_ins]>;
168
169// Turn G_UNMERGE_VALUES -> G_EXTRACT_VECTOR_ELT's
170def vector_unmerge_lowering : GICombineRule <
171  (defs root:$root),
172  (match (wip_match_opcode G_UNMERGE_VALUES):$root,
173          [{ return matchScalarizeVectorUnmerge(*${root}, MRI); }]),
174  (apply [{ applyScalarizeVectorUnmerge(*${root}, MRI, B); }])
175>;
176
177def adjust_icmp_imm_matchdata :
178  GIDefMatchData<"std::pair<uint64_t, CmpInst::Predicate>">;
179def adjust_icmp_imm : GICombineRule <
180  (defs root:$root, adjust_icmp_imm_matchdata:$matchinfo),
181  (match (wip_match_opcode G_ICMP):$root,
182          [{ return matchAdjustICmpImmAndPred(*${root}, MRI, ${matchinfo}); }]),
183  (apply [{ applyAdjustICmpImmAndPred(*${root}, ${matchinfo}, B, Observer); }])
184>;
185
186def swap_icmp_operands : GICombineRule <
187  (defs root:$root),
188  (match (wip_match_opcode G_ICMP):$root,
189          [{ return trySwapICmpOperands(*${root}, MRI); }]),
190  (apply [{ applySwapICmpOperands(*${root}, Observer); }])
191>;
192
193def icmp_lowering : GICombineGroup<[adjust_icmp_imm, swap_icmp_operands]>;
194
195def extractvecelt_pairwise_add_matchdata : GIDefMatchData<"std::tuple<unsigned, LLT, Register>">;
196def extractvecelt_pairwise_add : GICombineRule<
197  (defs root:$root, extractvecelt_pairwise_add_matchdata:$matchinfo),
198  (match (wip_match_opcode G_EXTRACT_VECTOR_ELT):$root,
199          [{ return matchExtractVecEltPairwiseAdd(*${root}, MRI, ${matchinfo}); }]),
200  (apply [{ applyExtractVecEltPairwiseAdd(*${root}, MRI, B, ${matchinfo}); }])
201>;
202
203def mul_const_matchdata : GIDefMatchData<"std::function<void(MachineIRBuilder&, Register)>">;
204def mul_const : GICombineRule<
205  (defs root:$root, mul_const_matchdata:$matchinfo),
206  (match (wip_match_opcode G_MUL):$root,
207          [{ return matchAArch64MulConstCombine(*${root}, MRI, ${matchinfo}); }]),
208  (apply [{ applyAArch64MulConstCombine(*${root}, MRI, B, ${matchinfo}); }])
209>;
210
211def lower_mull : GICombineRule<
212  (defs root:$root),
213  (match (wip_match_opcode G_MUL):$root,
214          [{ return matchExtMulToMULL(*${root}, MRI); }]),
215  (apply [{ applyExtMulToMULL(*${root}, MRI, B, Observer); }])
216>;
217
218def build_vector_to_dup : GICombineRule<
219  (defs root:$root),
220  (match (wip_match_opcode G_BUILD_VECTOR):$root,
221          [{ return matchBuildVectorToDup(*${root}, MRI); }]),
222  (apply [{ applyBuildVectorToDup(*${root}, MRI, B); }])
223>;
224
225def build_vector_lowering : GICombineGroup<[build_vector_to_dup]>;
226
227def lower_vector_fcmp : GICombineRule<
228  (defs root:$root),
229  (match (wip_match_opcode G_FCMP):$root,
230    [{ return matchLowerVectorFCMP(*${root}, MRI, B); }]),
231  (apply [{ applyLowerVectorFCMP(*${root}, MRI, B); }])>;
232
233def form_truncstore_matchdata : GIDefMatchData<"Register">;
234def form_truncstore : GICombineRule<
235  (defs root:$root, form_truncstore_matchdata:$matchinfo),
236  (match (wip_match_opcode G_STORE):$root,
237          [{ return matchFormTruncstore(*${root}, MRI, ${matchinfo}); }]),
238  (apply [{ applyFormTruncstore(*${root}, MRI, B, Observer, ${matchinfo}); }])
239>;
240
241def fold_merge_to_zext : GICombineRule<
242  (defs root:$d),
243  (match (wip_match_opcode G_MERGE_VALUES):$d,
244          [{ return matchFoldMergeToZext(*${d}, MRI); }]),
245  (apply [{ applyFoldMergeToZext(*${d}, MRI, B, Observer); }])
246>;
247
248def mutate_anyext_to_zext : GICombineRule<
249  (defs root:$d),
250  (match (wip_match_opcode G_ANYEXT):$d,
251          [{ return matchMutateAnyExtToZExt(*${d}, MRI); }]),
252  (apply [{ applyMutateAnyExtToZExt(*${d}, MRI, B, Observer); }])
253>;
254
255def split_store_zero_128 : GICombineRule<
256  (defs root:$d),
257  (match (wip_match_opcode G_STORE):$d,
258          [{ return matchSplitStoreZero128(*${d}, MRI); }]),
259  (apply [{ applySplitStoreZero128(*${d}, MRI, B, Observer); }])
260>;
261
262def vector_sext_inreg_to_shift : GICombineRule<
263  (defs root:$d),
264  (match (wip_match_opcode G_SEXT_INREG):$d,
265          [{ return matchVectorSextInReg(*${d}, MRI); }]),
266  (apply [{ applyVectorSextInReg(*${d}, MRI, B, Observer); }])
267>;
268
269def unmerge_ext_to_unmerge_matchdata : GIDefMatchData<"Register">;
270def unmerge_ext_to_unmerge : GICombineRule<
271  (defs root:$d, unmerge_ext_to_unmerge_matchdata:$matchinfo),
272  (match (wip_match_opcode G_UNMERGE_VALUES):$d,
273          [{ return matchUnmergeExtToUnmerge(*${d}, MRI, ${matchinfo}); }]),
274  (apply [{ applyUnmergeExtToUnmerge(*${d}, MRI, B, Observer, ${matchinfo}); }])
275>;
276
277def regtriple_matchdata : GIDefMatchData<"std::tuple<Register, Register, Register>">;
278def or_to_bsp: GICombineRule <
279  (defs root:$root, regtriple_matchdata:$matchinfo),
280  (match (wip_match_opcode G_OR):$root,
281         [{ return matchOrToBSP(*${root}, MRI, ${matchinfo}); }]),
282  (apply [{ applyOrToBSP(*${root}, MRI, B, ${matchinfo}); }])
283>;
284
285// Combines Mul(And(Srl(X, 15), 0x10001), 0xffff) into CMLTz
286def combine_mul_cmlt : GICombineRule<
287  (defs root:$root, register_matchinfo:$matchinfo),
288  (match (wip_match_opcode G_MUL):$root,
289        [{ return matchCombineMulCMLT(*${root}, MRI, ${matchinfo}); }]),
290  (apply [{ applyCombineMulCMLT(*${root}, MRI, B, ${matchinfo}); }])
291>;
292
293// Post-legalization combines which should happen at all optimization levels.
294// (E.g. ones that facilitate matching for the selector) For example, matching
295// pseudos.
296def AArch64PostLegalizerLowering
297    : GICombiner<"AArch64PostLegalizerLoweringImpl",
298                       [shuffle_vector_lowering, vashr_vlshr_imm,
299                        icmp_lowering, build_vector_lowering,
300                        lower_vector_fcmp, form_truncstore,
301                        vector_sext_inreg_to_shift,
302                        unmerge_ext_to_unmerge, lower_mull,
303                        vector_unmerge_lowering, insertelt_nonconst]> {
304}
305
306// Post-legalization combines which are primarily optimizations.
307def AArch64PostLegalizerCombiner
308    : GICombiner<"AArch64PostLegalizerCombinerImpl",
309                       [copy_prop, combines_for_extload,
310                        combine_indexed_load_store,
311                        sext_trunc_sextload, mutate_anyext_to_zext,
312                        hoist_logic_op_with_same_opcode_hands,
313                        redundant_and, xor_of_and_with_same_reg,
314                        extractvecelt_pairwise_add, redundant_or,
315                        mul_const, redundant_sext_inreg,
316                        form_bitfield_extract, rotate_out_of_range,
317                        icmp_to_true_false_known_bits, merge_unmerge,
318                        select_combines, fold_merge_to_zext,
319                        constant_fold_binops, identity_combines,
320                        ptr_add_immed_chain, overlapping_and,
321                        split_store_zero_128, undef_combines,
322                        select_to_minmax, or_to_bsp, combine_concat_vector,
323                        commute_constant_to_rhs,
324                        push_freeze_to_prevent_poison_from_propagating,
325                        combine_mul_cmlt]> {
326}
327