xref: /illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/clc.h (revision b01ab2de0c818b0ee650585b54613701d6e50349)
1 
2 
3 #ifndef __ELINK_H
4 #define __ELINK_H
5 
6 #if defined(_VBD_)
7 #include <SAL.h>
8 #include "debug.h"
9 #endif
10 
11 #ifndef _In_
12 #define _In_
13 #endif
14 #ifndef _Out_
15 #define _Out_
16 #endif
17 
18 /***********************************************************/
19 /*                  CLC Call backs functions               */
20 /***********************************************************/
21 /* CLC device structure */
22 struct elink_dev;
23 
24 extern u32 elink_cb_reg_read(struct elink_dev *cb, u32 reg_addr);
25 extern void elink_cb_reg_write(struct elink_dev *cb, u32 reg_addr, u32 val);
26 /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
27 extern void elink_cb_reg_wb_write(struct elink_dev *cb, u32 offset,
28 				u32 *wb_write, u16 len);
29 extern void elink_cb_reg_wb_read(struct elink_dev *cb, u32 offset,
30 			       u32 *wb_write, u16 len);
31 
32 /* mode - 0( LOW ) /1(HIGH)*/
33 extern u8 elink_cb_gpio_write(struct elink_dev *cb,
34 			    u16 gpio_num,
35 			    u8 mode, u8 port);
36 extern u8 elink_cb_gpio_mult_write(struct elink_dev *cb,
37 			    u8 pins,
38 			    u8 mode);
39 
40 extern u32 elink_cb_gpio_read(struct elink_dev *cb, u16 gpio_num, u8 port);
41 extern u8 elink_cb_gpio_int_write(struct elink_dev *cb,
42 				u16 gpio_num,
43 				u8 mode, u8 port);
44 
45 extern u32 elink_cb_fw_command(struct elink_dev *cb, u32 command, u32 param);
46 
47 /* Delay */
48 extern void elink_cb_udelay(struct elink_dev *cb, u32 microsecond);
49 
50 /* This function is called every 1024 bytes downloading of phy firmware.
51 Driver can use it to print to screen indication for download progress */
52 extern void elink_cb_download_progress(struct elink_dev *cb, u32 cur, u32 total);
53 
54 /* Each log type has its own parameters */
55 typedef enum elink_log_id {
56 	ELINK_LOG_ID_UNQUAL_IO_MODULE	= 0, /* u8 port, const char* vendor_name, const char* vendor_pn */
57 	ELINK_LOG_ID_OVER_CURRENT	= 1, /* u8 port */
58 	ELINK_LOG_ID_PHY_UNINITIALIZED	= 2, /* u8 port */
59 	ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
60 	ELINK_LOG_ID_NON_10G_MODULE	= 4, /* u8 port */
61 }elink_log_id_t;
62 
63 typedef enum elink_status {
64 	ELINK_STATUS_OK = 0,
65 	ELINK_STATUS_ERROR,
66 	ELINK_STATUS_TIMEOUT,
67 	ELINK_STATUS_NO_LINK,
68 	ELINK_STATUS_INVALID_IMAGE,
69 	ELINK_OP_NOT_SUPPORTED = 122
70 } elink_status_t;
71 #ifndef EDEBUG
72 extern void elink_cb_event_log(struct elink_dev *cb, const elink_log_id_t log_id, ...);
73 #endif
74 extern void elink_cb_load_warpcore_microcode(void);
75 
76 extern u8 elink_cb_path_id(struct elink_dev *cb);
77 
78 extern void elink_cb_notify_link_changed(struct elink_dev *cb);
79 
80 #define ELINK_EVENT_LOG_LEVEL_ERROR 	1
81 #define ELINK_EVENT_LOG_LEVEL_WARNING 	2
82 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 	1
83 #define ELINK_EVENT_ID_SFP_POWER_FAULT 		2
84 
85 #ifndef ARRAY_SIZE
86 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
87 #endif
88 /* Debug prints */
89 #ifdef ELINK_DEBUG
90 
91 #if defined(_VBD_)
92 #define ELINK_DEBUG_P0(cb, fmt) 		DbgMessage(cb, WARNelink, fmt)
93 #define ELINK_DEBUG_P1(cb, fmt, arg1) 		DbgMessage(cb, WARNelink, fmt, arg1)
94 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2)	DbgMessage(cb, WARNelink, fmt, arg1, arg2)
95 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \
96 					DbgMessage(cb, WARNelink, fmt, arg1, arg2, arg3)
97 #else
98 extern void elink_cb_dbg(struct elink_dev *cb, _In_ char *fmt);
99 extern void elink_cb_dbg1(struct elink_dev *cb, _In_ char *fmt, u32 arg1);
100 extern void elink_cb_dbg2(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2);
101 extern void elink_cb_dbg3(struct elink_dev *cb, _In_ char *fmt, u32 arg1, u32 arg2,
102 			  u32 arg3);
103 
104 #define ELINK_DEBUG_P0(cb, fmt) 		elink_cb_dbg(cb, fmt)
105 #define ELINK_DEBUG_P1(cb, fmt, arg1) 		elink_cb_dbg1(cb, fmt, arg1)
106 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2)	elink_cb_dbg2(cb, fmt, arg1, arg2)
107 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3) \
108 					elink_cb_dbg3(cb, fmt, arg1, arg2, arg3)
109 #endif // _VBD_
110 
111 #else
112 #define ELINK_DEBUG_P0(cb, fmt)
113 #define ELINK_DEBUG_P1(cb, fmt, arg1)
114 #define ELINK_DEBUG_P2(cb, fmt, arg1, arg2)
115 #define ELINK_DEBUG_P3(cb, fmt, arg1, arg2, arg3)
116 #endif
117 
118 /***********************************************************/
119 /*                         Defines                         */
120 /***********************************************************/
121 #define ELINK_DEFAULT_PHY_DEV_ADDR	3
122 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR	5
123 
124 
125 #ifndef DUPLEX_FULL
126 #define DUPLEX_FULL			1
127 #endif
128 #ifndef DUPLEX_HALF
129 #define DUPLEX_HALF			2
130 #endif
131 
132 #define ELINK_FLOW_CTRL_AUTO		PORT_FEATURE_FLOW_CONTROL_AUTO
133 #define ELINK_FLOW_CTRL_TX		PORT_FEATURE_FLOW_CONTROL_TX
134 #define ELINK_FLOW_CTRL_RX		PORT_FEATURE_FLOW_CONTROL_RX
135 #define ELINK_FLOW_CTRL_BOTH		PORT_FEATURE_FLOW_CONTROL_BOTH
136 #define ELINK_FLOW_CTRL_NONE		PORT_FEATURE_FLOW_CONTROL_NONE
137 
138 #define ELINK_NET_SERDES_IF_XFI		1
139 #define ELINK_NET_SERDES_IF_SFI		2
140 #define ELINK_NET_SERDES_IF_KR		3
141 #define ELINK_NET_SERDES_IF_DXGXS	4
142 
143 #define ELINK_SPEED_AUTO_NEG		0
144 #define ELINK_SPEED_10			10
145 #define ELINK_SPEED_100			100
146 #define ELINK_SPEED_1000		1000
147 #define ELINK_SPEED_2500		2500
148 #define ELINK_SPEED_10000		10000
149 #define ELINK_SPEED_20000		20000
150 
151 #define ELINK_I2C_DEV_ADDR_A0			0xa0
152 #define ELINK_I2C_DEV_ADDR_A2			0xa2
153 
154 #define ELINK_SFP_EEPROM_PAGE_SIZE			16
155 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR		0x14
156 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE		16
157 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR		0x25
158 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE		3
159 #define ELINK_SFP_EEPROM_PART_NO_ADDR			0x28
160 #define ELINK_SFP_EEPROM_PART_NO_SIZE			16
161 #define ELINK_SFP_EEPROM_REVISION_ADDR		0x38
162 #define ELINK_SFP_EEPROM_REVISION_SIZE		4
163 #define ELINK_SFP_EEPROM_SERIAL_ADDR			0x44
164 #define ELINK_SFP_EEPROM_SERIAL_SIZE			16
165 #define ELINK_SFP_EEPROM_DATE_ADDR			0x54 /* ASCII YYMMDD */
166 #define ELINK_SFP_EEPROM_DATE_SIZE			6
167 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR			0x5c
168 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE			1
169 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ		(1<<2)
170 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR		0x5e
171 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE		1
172 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_ADDR	0x60
173 #define ELINK_SFP_EEPROM_VENDOR_SPECIFIC_SIZE	16
174 
175 
176 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE		0x5e
177 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR			0x5f
178 
179 #define ELINK_PWR_FLT_ERR_MSG_LEN			250
180 
181 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
182 		((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
183 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
184 		(((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
185 		 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
186 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
187 		((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
188 
189 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
190 #define ELINK_SINGLE_MEDIA_DIRECT(params)	(params->num_phys == 1)
191 /* Single Media board contains single external phy */
192 #define ELINK_SINGLE_MEDIA(params)		(params->num_phys == 2)
193 /* Dual Media board contains two external phy with different media */
194 #define ELINK_DUAL_MEDIA(params)		(params->num_phys == 3)
195 
196 #define ELINK_FW_PARAM_PHY_ADDR_MASK		0x000000FF
197 #define ELINK_FW_PARAM_PHY_TYPE_MASK		0x0000FF00
198 #define ELINK_FW_PARAM_MDIO_CTRL_MASK		0xFFFF0000
199 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET		16
200 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
201 					   ELINK_FW_PARAM_PHY_ADDR_MASK)
202 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
203 					   ELINK_FW_PARAM_PHY_TYPE_MASK)
204 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
205 					    ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
206 					    ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
207 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
208 	(phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
209 
210 
211 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD				170
212 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD				250
213 
214 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
215 
216 #define ELINK_BMAC_CONTROL_RX_ENABLE		2
217 /***********************************************************/
218 /*                         Structs                         */
219 /***********************************************************/
220 #define ELINK_INT_PHY		0
221 #define ELINK_EXT_PHY1	1
222 #define ELINK_EXT_PHY2	2
223 #define ELINK_MAX_PHYS	3
224 
225 /* Same configuration is shared between the XGXS and the first external phy */
226 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
227 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
228 					 0 : (_phy_idx - 1))
229 /***********************************************************/
230 /*                      elink_phy struct                   */
231 /*  Defines the required arguments and function per phy    */
232 /***********************************************************/
233 struct elink_vars;
234 struct elink_params;
235 struct elink_phy;
236 
237 typedef elink_status_t (*config_init_t)(struct elink_phy *phy,
238     struct elink_params *params, struct elink_vars *vars);
239 typedef elink_status_t (*read_status_t)(struct elink_phy *phy,
240     struct elink_params *params, struct elink_vars *vars);
241 typedef void (*link_reset_t)(struct elink_phy *phy,
242 			     struct elink_params *params);
243 typedef void (*config_loopback_t)(struct elink_phy *phy,
244 				  struct elink_params *params);
245 typedef elink_status_t (*format_fw_ver_t)(u32 raw, u8 *str, u16 *len);
246 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
247 typedef void (*set_link_led_t)(struct elink_phy *phy,
248 			       struct elink_params *params, u8 mode);
249 typedef void (*phy_specific_func_t)(struct elink_phy *phy,
250 				    struct elink_params *params, u32 action);
251 struct elink_reg_set {
252 	u8  devad;
253 	u16 reg;
254 	u16 val;
255 };
256 
257 struct elink_phy {
258 	u32 type;
259 
260 	/* Loaded during init */
261 	u8 addr;
262 	u8 def_md_devad;
263 	u16 flags;
264 	/* No Over-Current detection */
265 #define ELINK_FLAGS_NOC			(1<<1)
266 	/* Fan failure detection required */
267 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ	(1<<2)
268 	/* Initialize first the XGXS and only then the phy itself */
269 #define ELINK_FLAGS_INIT_XGXS_FIRST		(1<<3)
270 #define ELINK_FLAGS_WC_DUAL_MODE		(1<<4)
271 #define ELINK_FLAGS_4_PORT_MODE		(1<<5)
272 #define ELINK_FLAGS_REARM_LATCH_SIGNAL		(1<<6)
273 #define ELINK_FLAGS_SFP_NOT_APPROVED		(1<<7)
274 #define ELINK_FLAGS_MDC_MDIO_WA		(1<<8)
275 #define ELINK_FLAGS_DUMMY_READ			(1<<9)
276 #define ELINK_FLAGS_MDC_MDIO_WA_B0		(1<<10)
277 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC	(1<<11)
278 #define ELINK_FLAGS_TX_ERROR_CHECK		(1<<12)
279 #define ELINK_FLAGS_EEE			(1<<13)
280 #define ELINK_FLAGS_TEMPERATURE		(1<<14)
281 #define ELINK_FLAGS_MDC_MDIO_WA_G		(1<<15)
282 
283 	/* preemphasis values for the rx side */
284 	u16 rx_preemphasis[4];
285 
286 	/* preemphasis values for the tx side */
287 	u16 tx_preemphasis[4];
288 
289 	/* EMAC address for access MDIO */
290 	u32 mdio_ctrl;
291 
292 	u32 supported;
293 #define ELINK_SUPPORTED_10baseT_Half		(1<<0)
294 #define ELINK_SUPPORTED_10baseT_Full		(1<<1)
295 #define ELINK_SUPPORTED_100baseT_Half		(1<<2)
296 #define ELINK_SUPPORTED_100baseT_Full 		(1<<3)
297 #define ELINK_SUPPORTED_1000baseT_Full 	(1<<4)
298 #define ELINK_SUPPORTED_2500baseX_Full 	(1<<5)
299 #define ELINK_SUPPORTED_10000baseT_Full 	(1<<6)
300 #define ELINK_SUPPORTED_TP 			(1<<7)
301 #define ELINK_SUPPORTED_FIBRE 			(1<<8)
302 #define ELINK_SUPPORTED_Autoneg 		(1<<9)
303 #define ELINK_SUPPORTED_Pause 			(1<<10)
304 #define ELINK_SUPPORTED_Asym_Pause		(1<<11)
305 #define ELINK_SUPPORTED_20000baseMLD2_Full	(1<<21)
306 #define ELINK_SUPPORTED_20000baseKR2_Full	(1<<22)
307 
308 	u32 media_type;
309 #define	ELINK_ETH_PHY_UNSPECIFIED	0x0
310 #define	ELINK_ETH_PHY_SFPP_10G_FIBER	0x1
311 #define	ELINK_ETH_PHY_XFP_FIBER		0x2
312 #define	ELINK_ETH_PHY_DA_TWINAX		0x3
313 #define	ELINK_ETH_PHY_BASE_T		0x4
314 #define ELINK_ETH_PHY_SFP_1G_FIBER	0x5
315 #define	ELINK_ETH_PHY_KR		0xf0
316 #define	ELINK_ETH_PHY_CX4		0xf1
317 #define	ELINK_ETH_PHY_NOT_PRESENT	0xff
318 
319 	u32 sfp_media;
320 #define	ELINK_ETH_SFP_UNKNOWN		0x00
321 #define	ELINK_ETH_SFP_DAC		0x01
322 #define	ELINK_ETH_SFP_ACC		0x02
323 #define	ELINK_ETH_SFP_1GBASE_T		0x03
324 #define	ELINK_ETH_SFP_1GBASE_SX		0x04
325 #define	ELINK_ETH_SFP_1GBASE_LX		0x05
326 #define	ELINK_ETH_SFP_1GBASE_CX		0x06
327 #define	ELINK_ETH_SFP_10GBASE_SR	0x07
328 #define	ELINK_ETH_SFP_10GBASE_LR	0x09
329 #define	ELINK_ETH_SFP_10GBASE_LRM	0x09
330 #define	ELINK_ETH_SFP_10GBASE_ER	0x0a
331 
332 	/* The address in which version is located*/
333 	u32 ver_addr;
334 
335 	u16 req_flow_ctrl;
336 
337 	u16 req_line_speed;
338 
339 	u32 speed_cap_mask;
340 
341 	u16 req_duplex;
342 	u16 rsrv;
343 	/* Called per phy/port init, and it configures LASI, speed, autoneg,
344 	 duplex, flow control negotiation, etc. */
345 	config_init_t config_init;
346 
347 	/* Called due to interrupt. It determines the link, speed */
348 	read_status_t read_status;
349 
350 	/* Called when driver is unloading. Should reset the phy */
351 	link_reset_t link_reset;
352 
353 	/* Set the loopback configuration for the phy */
354 	config_loopback_t config_loopback;
355 
356 	/* Format the given raw number into str up to len */
357 	format_fw_ver_t format_fw_ver;
358 
359 	/* Reset the phy (both ports) */
360 	hw_reset_t hw_reset;
361 
362 	/* Set link led mode (on/off/oper)*/
363 	set_link_led_t set_link_led;
364 
365 	/* PHY Specific tasks */
366 	phy_specific_func_t phy_specific_func;
367 #define ELINK_DISABLE_TX	1
368 #define ELINK_ENABLE_TX	2
369 #define ELINK_PHY_INIT	3
370 };
371 
372 /* Inputs parameters to the CLC */
373 struct elink_params {
374 
375 	u8 port;
376 
377 	/* Default / User Configuration */
378 	u8 loopback_mode;
379 #define ELINK_LOOPBACK_NONE		0
380 #define ELINK_LOOPBACK_EMAC		1
381 #define ELINK_LOOPBACK_BMAC		2
382 #define ELINK_LOOPBACK_XGXS		3
383 #define ELINK_LOOPBACK_EXT_PHY		4
384 #define ELINK_LOOPBACK_EXT		5
385 #define ELINK_LOOPBACK_UMAC		6
386 #define ELINK_LOOPBACK_XMAC		7
387 
388 	/* Device parameters */
389 	u8 mac_addr[6];
390 
391 	u16 req_duplex[ELINK_LINK_CONFIG_SIZE];
392 	u16 req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
393 
394 	u16 req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
395 
396 	/* shmem parameters */
397 	u32 shmem_base;
398 	u32 shmem2_base;
399 	u32 speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
400 	u32 switch_cfg;
401 #define ELINK_SWITCH_CFG_1G		PORT_FEATURE_CON_SWITCH_1G_SWITCH
402 #define ELINK_SWITCH_CFG_10G		PORT_FEATURE_CON_SWITCH_10G_SWITCH
403 #define ELINK_SWITCH_CFG_AUTO_DETECT	PORT_FEATURE_CON_SWITCH_AUTO_DETECT
404 
405 	u32 lane_config;
406 
407 	/* Phy register parameter */
408 	u32 chip_id;
409 
410 	/* features */
411 	u32 feature_config_flags;
412 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED	(1<<0)
413 #define ELINK_FEATURE_CONFIG_PFC_ENABLED			(1<<1)
414 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY		(1<<2)
415 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY	(1<<3)
416 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC			(1<<4)
417 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC			(1<<5)
418 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC			(1<<6)
419 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC			(1<<7)
420 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX			(1<<8)
421 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED		(1<<9)
422 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED	(1<<10)
423 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET		(1<<11)
424 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST			(1<<12)
425 #define ELINK_FEATURE_CONFIG_MT_SUPPORT			(1<<13)
426 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN			(1<<14)
427 
428 	/* Will be populated during common init */
429 	struct elink_phy phy[ELINK_MAX_PHYS];
430 
431 	/* Will be populated during common init */
432 	u8 num_phys;
433 
434 	u8 rsrv;
435 
436 	/* Used to configure the EEE Tx LPI timer, has several modes of
437 	 * operation, according to bits 29:28 -
438 	 * 2'b00: Timer will be configured by nvram, output will be the value
439 	 *        from nvram.
440 	 * 2'b01: Timer will be configured by nvram, output will be in
441 	 *        microseconds.
442 	 * 2'b10: bits 1:0 contain an nvram value which will be used instead
443 	 *        of the one located in the nvram. Output will be that value.
444 	 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
445 	 *        will be in microseconds.
446 	 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
447 	 */
448 	u32 eee_mode;
449 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME		(0xa00)
450 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME		(0x100)
451 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME		(0x6000)
452 #define ELINK_EEE_MODE_NVRAM_MASK		(0x3)
453 #define ELINK_EEE_MODE_TIMER_MASK		(0xfffff)
454 #define ELINK_EEE_MODE_OUTPUT_TIME		(1<<28)
455 #define ELINK_EEE_MODE_OVERRIDE_NVRAM		(1<<29)
456 #define ELINK_EEE_MODE_ENABLE_LPI		(1<<30)
457 #define ELINK_EEE_MODE_ADV_LPI			(1<<31)
458 
459 	u16 hw_led_mode; /* part of the hw_config read from the shmem */
460 	u32 multi_phy_config;
461 
462 	/* Device pointer passed to all callback functions */
463 	struct elink_dev *cb;
464 	u16 req_fc_auto_adv; /* Should be set to TX / BOTH when
465 				req_flow_ctrl is set to AUTO */
466 	u16 link_flags;
467 #define ELINK_LINK_FLAGS_INT_DISABLED		(1<<0)
468 #define ELINK_PHY_INITIALIZED		(1<<1)
469 	u32 lfa_base;
470 
471 	/* The same definitions as the shmem2 parameter */
472 	u32 link_attr_sync;
473 };
474 
475 /* Output parameters */
476 struct elink_vars {
477 	u8 phy_flags;
478 #define PHY_XGXS_FLAG			(1<<0)
479 #define PHY_SGMII_FLAG			(1<<1)
480 #define PHY_PHYSICAL_LINK_FLAG		(1<<2)
481 #define PHY_HALF_OPEN_CONN_FLAG		(1<<3)
482 #define PHY_OVER_CURRENT_FLAG		(1<<4)
483 #define PHY_SFP_TX_FAULT_FLAG		(1<<5)
484 
485 	u8 mac_type;
486 #define ELINK_MAC_TYPE_NONE		0
487 #define ELINK_MAC_TYPE_EMAC		1
488 #define ELINK_MAC_TYPE_BMAC		2
489 #define ELINK_MAC_TYPE_UMAC		3
490 #define ELINK_MAC_TYPE_XMAC		4
491 
492 	u8 phy_link_up; /* internal phy link indication */
493 	u8 link_up;
494 
495 	u16 line_speed;
496 	u16 duplex;
497 
498 	u16 flow_ctrl;
499 	u16 ieee_fc;
500 
501 	/* The same definitions as the shmem parameter */
502 	u32 link_status;
503 	u32 eee_status;
504 	u8 fault_detected;
505 	u8 check_kr2_recovery_cnt;
506 #define ELINK_CHECK_KR2_RECOVERY_CNT	5
507 	u16 periodic_flags;
508 #define ELINK_PERIODIC_FLAGS_LINK_EVENT	0x0001
509 
510 	u32 aeu_int_mask;
511 	u8 rx_tx_asic_rst;
512 	u8 turn_to_run_wc_rt;
513 	u16 rsrv2;
514 
515 };
516 
517 /***********************************************************/
518 /*                         Functions                       */
519 /***********************************************************/
520 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
521 
522 #ifndef EXCLUDE_LINK_RESET
523 /* Reset the link. Should be called when driver or interface goes down
524    Before calling phy firmware upgrade, the reset_ext_phy should be set
525    to 0 */
526 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
527 		     u8 reset_ext_phy);
528 #endif
529 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
530 /* elink_link_update should be called upon link interrupt */
531 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
532 
533 /* use the following phy functions to read/write from external_phy
534   In order to use it to read/write internal phy registers, use
535   ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
536   the register */
537 elink_status_t elink_phy_read(struct elink_params *params, u8 phy_addr,
538 		   u8 devad, u16 reg, u16 *ret_val);
539 
540 elink_status_t elink_phy_write(struct elink_params *params, u8 phy_addr,
541 		    u8 devad, u16 reg, u16 val);
542 
543 /* Reads the link_status from the shmem,
544    and update the link vars accordingly */
545 void elink_link_status_update(struct elink_params *input,
546 			    struct elink_vars *output);
547 #ifdef ELINK_ENHANCEMENTS
548 /* returns string representing the fw_version of the external phy */
549 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, u8 *version,
550 				 u16 len);
551 #endif
552 
553 /* Set/Unset the led
554    Basically, the CLC takes care of the led for the link, but in case one needs
555    to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
556    blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
557 elink_status_t elink_set_led(struct elink_params *params,
558 		  struct elink_vars *vars, u8 mode, u32 speed);
559 #define ELINK_LED_MODE_OFF			0
560 #define ELINK_LED_MODE_ON			1
561 #define ELINK_LED_MODE_OPER			2
562 #define ELINK_LED_MODE_FRONT_PANEL_OFF	3
563 
564 #ifdef ELINK_ENHANCEMENTS
565 /* elink_handle_module_detect_int should be called upon module detection
566    interrupt */
567 void elink_handle_module_detect_int(struct elink_params *params);
568 
569 /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
570 	otherwise link is down*/
571 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
572 		    u8 is_serdes);
573 
574 #endif
575 
576 /* One-time initialization for external phy after power up */
577 elink_status_t elink_common_init_phy(struct elink_dev *cb, u32 shmem_base_path[],
578 			  u32 shmem2_base_path[], u32 chip_id, u8 one_port_enabled);
579 
580 /* Reset the external PHY using GPIO */
581 void elink_ext_phy_hw_reset(struct elink_dev *cb, u8 port);
582 
583 #ifdef ELINK_ENHANCEMENTS
584 /* Reset the external of SFX7101 */
585 void elink_sfx7101_sp_sw_reset(struct elink_dev *cb, struct elink_phy *phy);
586 #endif
587 
588 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
589 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
590 				 struct elink_params *params, u8 dev_addr,
591 				 u16 addr, u16 byte_cnt, u8 *o_buf);
592 
593 void elink_hw_reset_phy(struct elink_params *params);
594 
595 /* Check swap bit and adjust PHY order */
596 u32 elink_phy_selection(struct elink_params *params);
597 
598 #ifndef EXCLUDE_COMMON_INIT
599 /* Probe the phys on board, and populate them in "params" */
600 elink_status_t elink_phy_probe(struct elink_params *params);
601 
602 /* Checks if fan failure detection is required on one of the phys on board */
603 u8 elink_fan_failure_det_req(struct elink_dev *cb, u32 shmem_base,
604 			     u32 shmem2_base, u8 port);
605 
606 /* Open / close the gate between the NIG and the BRB */
607 void elink_set_rx_filter(struct elink_params *params, u8 en);
608 #endif /* EXCLUDE_COMMON_INIT */
609 
610 /* DCBX structs */
611 
612 /* Number of maximum COS per chip */
613 #define ELINK_DCBX_E2E3_MAX_NUM_COS		(2)
614 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0	(6)
615 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1	(3)
616 #define ELINK_DCBX_E3B0_MAX_NUM_COS		( \
617 			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
618 			    ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
619 
620 #define ELINK_DCBX_MAX_NUM_COS			( \
621 			ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
622 			    ELINK_DCBX_E2E3_MAX_NUM_COS))
623 
624 /* PFC port configuration params */
625 struct elink_nig_brb_pfc_port_params {
626 	/* NIG */
627 	u32 pause_enable;
628 	u32 llfc_out_en;
629 	u32 llfc_enable;
630 	u32 pkt_priority_to_cos;
631 	u8 num_of_rx_cos_priority_mask;
632 	u32 rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
633 	u32 llfc_high_priority_classes;
634 	u32 llfc_low_priority_classes;
635 };
636 
637 
638 /* ETS port configuration params */
639 struct elink_ets_bw_params {
640 	u8 bw;
641 };
642 
643 struct elink_ets_sp_params {
644 	/**
645 	 * valid values are 0 - 5. 0 is highest strict priority.
646 	 * There can't be two COS's with the same pri.
647 	 */
648 	u8 pri;
649 };
650 
651 enum elink_cos_state {
652 	elink_cos_state_strict = 0,
653 	elink_cos_state_bw = 1,
654 };
655 
656 struct elink_ets_cos_params {
657 	enum elink_cos_state state ;
658 	union {
659 		struct elink_ets_bw_params bw_params;
660 		struct elink_ets_sp_params sp_params;
661 	} params;
662 };
663 
664 struct elink_ets_params {
665 	u8 num_of_cos; /* Number of valid COS entries*/
666 	struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
667 };
668 
669 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
670  * when link is already up
671  */
672 elink_status_t elink_update_pfc(struct elink_params *params,
673 		      struct elink_vars *vars,
674 		      struct elink_nig_brb_pfc_port_params *pfc_params);
675 
676 
677 /* Used to configure the ETS to disable */
678 elink_status_t elink_ets_disabled(struct elink_params *params,
679 		       struct elink_vars *vars);
680 
681 /* Used to configure the ETS to BW limited */
682 void elink_ets_bw_limit(const struct elink_params *params, const u32 cos0_bw,
683 			const u32 cos1_bw);
684 
685 /* Used to configure the ETS to strict */
686 elink_status_t elink_ets_strict(const struct elink_params *params, const u8 strict_cos);
687 
688 
689 /*  Configure the COS to ETS according to BW and SP settings.*/
690 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
691 			 const struct elink_vars *vars,
692 			 struct elink_ets_params *ets_params);
693 /* Read pfc statistic*/
694 #ifndef BNX2X_UPSTREAM /* ! BNX2X_UPSTREAM */
695 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
696 						 u32 pfc_frames_sent[2],
697 						 u32 pfc_frames_received[2]);
698 #endif
699 void elink_init_mod_abs_int(struct elink_dev *cb, struct elink_vars *vars,
700 			    u32 chip_id, u32 shmem_base, u32 shmem2_base,
701 			    u8 port);
702 #ifndef BNX2X_ADD /* ! BNX2X_ADD */
703 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
704 			       struct elink_params *params);
705 #endif
706 
707 void elink_period_func(struct elink_params *params, struct elink_vars *vars);
708 
709 #ifndef BNX2X_ADD /* ! BNX2X_ADD */
710 elink_status_t elink_check_half_open_conn(struct elink_params *params,
711 			            struct elink_vars *vars, u8 notify);
712 #endif
713 
714 void elink_enable_pmd_tx(struct elink_params *params);
715 
716 #ifndef EXCLUDE_FROM_BNX2X
717 elink_status_t elink_pre_init_phy(struct elink_dev *cb,
718 				  u32 shmem_base,
719 				  u32 shmem2_base,
720 				  u32 chip_id,
721 				  u8 port);
722 elink_status_t elink_validate_cc_dmi(u8 *sfp_a2_buf);
723 
724 #endif /* EXCLUDE_FROM_BNX2X */
725 #ifdef ELINK_AUX_POWER
726 void elink_adjust_phy_func_ptr(struct elink_params *params);
727 
728 elink_status_t elink_get_phy_temperature(struct elink_params *params,
729 			      u32 *temp_reading, u8 path, u8 port);
730 
731 u8 elink_phy_is_temperature_support(struct elink_params *params);
732 void set_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 val);
733 int get_cfg_pin(struct elink_dev *cb, u32 pin_cfg, u32 *val);
734 int elink_warpcore_get_sigdet(struct elink_phy *phy,
735 			      struct elink_params *params);
736 void elink_force_link(struct elink_params *params, int enable);
737 #endif
738 
739 #endif /* __ELINK_H */
740 
741